CN108156754B - Vertical connection interface structure, circuit board with the structure and manufacturing method thereof - Google Patents
Vertical connection interface structure, circuit board with the structure and manufacturing method thereof Download PDFInfo
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- CN108156754B CN108156754B CN201710066115.4A CN201710066115A CN108156754B CN 108156754 B CN108156754 B CN 108156754B CN 201710066115 A CN201710066115 A CN 201710066115A CN 108156754 B CN108156754 B CN 108156754B
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- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
- H05K3/365—Assembling flexible printed circuits with other printed circuits by abutting, i.e. without alloying process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
Abstract
The invention relates to a vertical connection interface structure, a circuit board with the structure and a manufacturing method thereof, wherein at least one layer of circuit board is connected through the vertical connection interface structure to solve the processing problem of high aspect ratio of the circuit board, solve the problem of longer signal transmission path among the multilayer circuit boards, and simultaneously have the functions of improving the stacking structure of the circuit board and pin pitch conversion.
Description
[ technical field ] A method for producing a semiconductor device
The present invention relates to a circuit board, and more particularly, to a vertical connection interface structure, a circuit board having the same, and a method for manufacturing the same.
[ background of the invention ]
With the development of electronic products toward precision and multi-functionalization, the chip structure of the integrated circuit in the electronic product tends to be complex, and the operating frequency of the chip structure is greatly increased, so as to be used in the field of electronic products with higher frequency bands. As the size of the tested chip is reduced and the pitch of the pins is also reduced, the pitch of the through holes (pitch) of the circuit board used for testing the electrical characteristics of the chip is reduced, i.e., the hole diameter of the through holes must be reduced. However, the circuit board is a multi-layer circuit board formed by laminating a plurality of material layers at one time, which results in a high aspect ratio structure and causes difficulty in drilling. Fig. 1 is a schematic diagram of a prior art circuit board connection interface. In the multilayer circuit board 10, the through hole 12 connects the conductive patterns 16 on the upper surface 14a and the lower surface 14b, and the vertical height H of the through hole 12 is much larger than the horizontal pitch P between the two conductive patterns 16, i.e. a structure with a high aspect ratio is formed, so that it is difficult to drill the through hole 12.
In order to solve the above-mentioned problems, the prior art proposes a multi-press or multi-layer structure, such as another multi-press structure 11 of the circuit board connection interface shown in fig. 2, in which a first through hole 12a connects a first conductive pattern 16a of an upper surface 14a, a second through hole 12b connects the first conductive pattern 16a of a lower surface 14b and a second conductive pattern 16b of the upper surface 14a, and the other end of the first through hole 12a connects the middle region of the second through hole 12b, forming an extension section 18 and an excess section (stub)20, although this way can reduce the aspect ratio, i.e. the ratio of H to P in fig. 2 is smaller than the ratio of H to P in fig. 1, when a signal is transmitted between the first conductive pattern 16a of the upper surface 14a of the first through hole 12a and the second conductive pattern 16b of the lower surface 14b of the second through hole 12b, the extension section 18 forms a longer signal transmission path, the loss of signal transmission is serious, and the extra segment (stub)20 will affect the signal transmission of different frequencies due to the depth of the through hole, and the transmission quality of signal will be deteriorated due to the above problems. Therefore, a new interface structure is needed to solve the above-mentioned problems.
[ summary of the invention ]
An object of the present invention is to provide a vertical connection interface structure, a circuit board having the same and a method for manufacturing the same, which is used to connect at least one circuit board layer through the vertical connection interface structure, so as to solve the problem of high aspect ratio processing of the circuit board.
Another objective of the present invention is to provide a vertical connection interface structure, a circuit board having the same and a method for manufacturing the same, wherein at least one layer of circuit board is connected through the vertical connection interface structure, so as to solve the problem of long signal transmission path between the multiple layers of circuit boards.
It is another objective of the present invention to provide a vertical connection interface structure, a circuit board having the same and a method for manufacturing the same, wherein at least one layer of circuit board, such as a flexible circuit board and a rigid circuit board, is connected to the vertical connection interface structure, so as to improve the problems of the stacked structure and the pin pitch conversion of the circuit board.
To achieve the above object, a method for manufacturing a vertical connection interface structure according to an embodiment of the present invention is applied to a circuit board, and includes the following steps: forming a conductive layer on a substrate; forming a photoresist layer on the conductive layer; performing a photolithography process to define a contact pad pattern by the photoresist layer and expose a portion of the conductive layer; etching the exposed conductive layer using the contact pad pattern as an etching mask to form a plurality of conductive contact pads, wherein each of the plurality of conductive contact pads is electrically insulated from each other; removing the photoresist layer to expose the conductive contact pads; forming a dielectric insulating layer on the conductive contact pads and the substrate to cover the conductive contact pads; forming a plurality of openings in the substrate and the dielectric insulating layer at positions corresponding to the plurality of conductive contact pads, respectively, and exposing the conductive contact pads in the plurality of openings of the substrate and the dielectric insulating layer; and forming a conductive material filled in each of the plurality of openings to form a conductive bump group, so that the two side surfaces of each of the plurality of conductive contact pads are electrically connected to the conductive bump group respectively.
In one embodiment, the substrate is a dielectric insulating material.
In one embodiment, the step of forming a dielectric insulating layer on the conductive contact pads and the substrate to cover the conductive contact pads includes attaching a dielectric insulating layer on the conductive contact pads and the substrate.
In an embodiment, the conductive bump set is made of a conductive paste or a conductive adhesive.
In an embodiment, the step of forming and filling a conductive material in each of the plurality of openings to form the conductive bump group such that both side surfaces of each of the plurality of conductive contact pads are electrically connected to the conductive bump group includes forming a plurality of first conductive bumps and a plurality of second conductive bumps of the conductive bump group, the plurality of first conductive bumps being disposed in the substrate, the plurality of second conductive bumps being disposed in the dielectric insulating layer, wherein both side surfaces of each of the plurality of conductive contact pads are electrically connected between each of the plurality of first conductive bumps and each of the plurality of second conductive bumps.
The manufacturing method of the vertical connection interface structure in one embodiment of the invention is used for a circuit board and comprises the following steps: forming a conductive layer on a substrate; forming a photoresist layer on the conductive layer; performing a photolithography process to define a contact pad pattern by the photoresist layer and expose a portion of the conductive layer; etching the exposed conductive layer using the contact pad pattern as an etching mask to form a plurality of conductive contact pads, each of the plurality of conductive contact pads being electrically insulated from each other; forming a plurality of openings on the substrate at positions corresponding to the plurality of conductive contact pads, and exposing the conductive contact pads in the plurality of openings of the substrate; filling a conductive material into the openings to form a plurality of first conductive bumps, so that one side surface of each conductive contact pad is correspondingly and electrically connected with each first conductive bump; and removing the photoresist layer.
In one embodiment, the substrate is a dielectric insulating material.
In one embodiment, the first conductive bump is a conductive paste or a conductive adhesive material.
In one embodiment, the step of removing the photoresist layer is performed before the step of forming the first conductive bumps or after the step of forming the first conductive bumps.
In one embodiment of the present invention, a circuit board with a vertical connection interface structure includes: the first multilayer circuit board is provided with a first multilayer board and a plurality of first through hole structures penetrating through the first multilayer board; the second multilayer circuit board is provided with a second multilayer board and a plurality of second through hole structures penetrating through the second multilayer board; and a vertical connection interface structure disposed between the first multilayer circuit board and the second multilayer circuit board for electrically connecting the first multilayer circuit board and the second multilayer circuit board, the vertical connection interface structure comprising: a substrate; a plurality of conductive contact pads disposed on the substrate, each of the plurality of conductive contact pads being electrically insulated from each other; a dielectric insulating layer disposed on the conductive contact pads and on the substrate to cover the conductive contact pads; and a conductive bump set disposed between the substrate and the dielectric insulating layer, the conductive bump set electrically connecting each of the plurality of conductive pads to the first via structure and the second via structure, respectively.
In an embodiment, the conductive bump set includes a plurality of first conductive bumps disposed in the substrate and a plurality of second conductive bumps disposed in the dielectric insulating layer, two side surfaces of each of the plurality of conductive contact pads are respectively and correspondingly electrically connected between each of the plurality of first conductive bumps and each of the plurality of second conductive bumps, the plurality of first conductive bumps are electrically connected to the first via structures of the first multi-layer circuit board, and the plurality of second conductive bumps are electrically connected to the second via structures of the second multi-layer circuit board.
In one embodiment, each of the plurality of conductive contact pads is electrically connected to each of the plurality of first conductive bumps and each of the plurality of second conductive bumps along a common transmission path.
In an embodiment, each of the plurality of conductive contact pads is electrically connected to each of the plurality of first conductive bumps, each of the plurality of second conductive bumps, the first via structure, and the second via structure along a common transmission path.
In one embodiment, the collinear transmission path is a vertical transmission path.
In an embodiment, the conductive bump sets are electrically connected to the first via structure and the second via structure respectively by heating and pressing.
In one embodiment of the present invention, a circuit board with a vertical connection interface structure includes: the single-layer circuit board is provided with a single-layer board and a plurality of first through hole structures penetrating through the single-layer board; and a vertical connection interface structure, set up in on the single-deck circuit board, for electric connection the single-deck circuit board, the vertical connection interface structure includes: a substrate; a plurality of conductive contact pads disposed on the substrate, each of the plurality of conductive contact pads being electrically insulated from each other; and a plurality of first conductive bumps arranged in the substrate, wherein each of the plurality of first conductive bumps is correspondingly and electrically connected with each of the plurality of conductive contact pads to each of the plurality of first through hole structures.
In one embodiment, the single-layer circuit board is a flexible circuit board.
In an embodiment, each of the plurality of conductive contact pads is electrically connected to each of the plurality of first conductive bumps and the first via structure along a common transmission path.
In one embodiment, the collinear transmission path is a vertical transmission path.
In an embodiment, each of the plurality of first conductive bumps is electrically connected to each of the plurality of conductive pads to each of the plurality of first via structures by a thermal pressing method.
In one embodiment of the present invention, a circuit board with a vertical connection interface structure includes: the single-layer circuit board is provided with a single-layer board and a plurality of first through hole structures penetrating through the single-layer board; and two sets of perpendicular connection interface structures, set up respectively in on the both sides surface of individual layer circuit board for each electric connection the both ends of a plurality of first through-hole structures, each set of perpendicular connection interface structure includes: a substrate; a plurality of conductive contact pads disposed on the substrate, each of the plurality of conductive contact pads being electrically insulated from each other; and a plurality of first conductive bumps arranged in the substrate, wherein each of the plurality of first conductive bumps is correspondingly and electrically connected with each of the plurality of conductive contact pads to the first through hole structure.
In one embodiment, the single-layer circuit board is a rigid circuit board.
In one embodiment, each of the plurality of conductive contact pads and each of the plurality of first conductive bumps of the two sets of vertical connection interface structures are electrically connected to the first via structure along a common transmission path.
In one embodiment, the collinear transmission path is a vertical transmission path.
In an embodiment, each of the plurality of first conductive bumps is electrically connected to each of the plurality of conductive pads to the first via structure by a thermal pressing method.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the detailed description of the embodiments will be described below.
FIG. 1 is a schematic diagram of a circuit board connection interface according to the prior art.
FIG. 2 is a schematic diagram of another prior art circuit board connection interface.
FIGS. 3A-3D are schematic structural diagrams illustrating a process for fabricating a vertical interconnect structure according to a first embodiment of the present invention.
FIGS. 4A-4C are schematic structural diagrams illustrating a process for fabricating a vertical interconnect structure according to a second embodiment of the present invention.
FIG. 5 is a schematic diagram of a circuit board with a vertical connection interface structure according to a first embodiment of the invention.
FIG. 6 is a schematic diagram of a circuit board with a vertical connection interface structure according to a second embodiment of the present invention.
FIG. 7 is a schematic diagram of a circuit board with a vertical connection interface structure according to a third embodiment of the present invention.
[ detailed description ] embodiments
Referring to the drawings, wherein like reference numbers represent the same element or similar elements, the principles of the present invention are illustrated in an exemplary operating environment. The following description is based on illustrated embodiments of the invention and should not be taken as limiting the invention with regard to other embodiments that are not detailed herein.
Referring to fig. 3A-3D, schematic structural diagrams illustrating a manufacturing process of the vertical connection interface structure according to the first embodiment of the invention are shown. In fig. 3A, a conductive layer 102 is formed on a substrate 100. The conductive layer 102 is formed by, for example, lamination, transfer, deposition methods. In one embodiment, the substrate 100 is a dielectric insulating material, and the conductive layer 102 is made of a metal, such as copper, aluminum, and gold, but not limited thereto. In fig. 3A, a photoresist layer 104 is formed on the conductive layer 102, such as a top-coating photoresist and/or a bottom-coating photoresist on the substrate 100.
In fig. 3A and 3B, a photolithography process is performed to define a contact pad pattern 106 by the photoresist layer 104 and expose a portion of the conductive layer 102.
In fig. 3B, the exposed conductive layer 102 is etched using the contact pad pattern 106 as an etching mask (etching mask) to form a plurality of conductive contact pads 106a, wherein each of the plurality of conductive contact pads 106 is electrically insulated from each other or each of the plurality of conductive contact pads 106a is separated from each other. In fig. 3B, the photoresist layer 104 is removed to expose the conductive contact pads 106 a. The photoresist layer 104 is removed, for example, by stripping or ashing.
In fig. 3C, a dielectric insulating layer 108 is formed on the conductive contact pads 106a and the substrate 100 to cover the conductive contact pads 106 a. The dielectric insulating layer 108 is formed on the conductive contact pads 106a and the substrate 100, for example, in a fitting manner.
In fig. 3D, a plurality of openings 110 are formed in the substrate 100 and the dielectric insulating layer 108 at positions corresponding to the plurality of conductive contact pads 106a, respectively, and the plurality of openings 110 in the substrate 100 and the dielectric insulating layer 108 expose the conductive contact pads 106 a. In one embodiment, the openings 110 are formed, for example, by a laser thermal reaction method. In fig. 3D, a conductive material is filled into each of the openings 110 to form a conductive bump set 112, such that the two side surfaces 106b of each of the conductive contact pads 106a are electrically connected to the conductive bump set 112, respectively, and the conductive bump set 112 includes a plurality of first conductive bumps 112a and a plurality of second conductive bumps 112 b. In one embodiment, the conductive bump sets 112 are formed by a transfer printing, filling or deposition method, for example, according to different materials of the conductive bump sets 112. In one embodiment, the conductive bump set 112 is made of conductive paste or conductive adhesive. In one embodiment, the first conductive bumps 112a are disposed in the substrate 100, and the second conductive bumps 112b are disposed in the dielectric insulating layer 108, wherein the two side surfaces 106b of each conductive contact pad 106a are respectively and correspondingly electrically connected between each of the first conductive bumps 112a and each of the second conductive bumps 112 b.
Referring to fig. 4A-4C, schematic structural diagrams illustrating a manufacturing process of a vertical connection interface structure according to a second embodiment of the present invention are shown. In fig. 4A, a conductive layer 102 is formed on a substrate 100. The conductive layer 102 is formed by, for example, lamination, transfer, deposition methods. In one embodiment, the substrate 100 is a dielectric insulating material, and the conductive layer 102 is made of a metal, such as copper, aluminum, and gold, but not limited thereto. In fig. 4A, a photoresist layer 104 is formed on the conductive layer 102, such as an upper surface coating forming photoresist and/or a lower surface coating forming photoresist on the substrate 100, where the upper and lower surfaces of the substrate 100 are coated forming photoresist.
In fig. 4A and 4B, a photolithography process is performed to define a contact pad pattern 106 by the photoresist layer 104 and expose a portion of the conductive layer 102.
In fig. 4B, the exposed conductive layer 102 is etched using the contact pad pattern 106 as an etching mask (etching mask) to form a plurality of conductive contact pads 106a, wherein each of the plurality of conductive contact pads 106 is electrically insulated from each other or each of the plurality of conductive contact pads 106a is separated from each other.
In fig. 4C, a plurality of openings 110 are formed in the substrate 100 at positions corresponding to the plurality of conductive contact pads 106a, and the plurality of openings 110 of the substrate 100 expose the conductive contact pads 106 a. In one embodiment, the openings 110 are formed, for example, by a laser thermal reaction method. In fig. 4C, a conductive material is filled into each of the openings 110 to form a plurality of first conductive bumps 112a, such that the two side surfaces 106b of each of the plurality of conductive contact pads 106a are electrically connected to the plurality of first conductive bumps 112a, respectively. In one embodiment, the first conductive bump 112a is formed by a transfer printing, filling or deposition method according to different materials of the first conductive bump 112 a. In one embodiment, the first conductive bump 112a is made of a conductive paste or a conductive adhesive. In one embodiment, the plurality of first conductive bumps 112a are disposed in the substrate 100, wherein a side surface 106b of each conductive contact pad 106a is electrically connected to the bottom of each first conductive bump 112a correspondingly. In fig. 4C, the photoresist layer 104 is removed, such as by stripping or ashing the photoresist layer 104. In various embodiments, the photoresist layer 104 is removed before or after the step of forming the first conductive bumps 112a, as shown in fig. 4C, the photoresist layer 104 is removed after forming the first conductive bumps 112a, and the photoresist layer 104 is removed to prevent the first conductive bumps 112a from overflowing towards two sides, so that the adjacent first conductive bumps 112a are effectively electrically isolated or separated from each other.
Referring to fig. 5, a schematic diagram of a circuit board with a vertical connection interface structure according to a first embodiment of the invention is shown. The circuit board having the vertical connection interface structure includes a first multi-layer circuit board 114, a second multi-layer circuit board 116, and a vertical connection interface structure, which is shown in fig. 3D. In one embodiment, the vertical connection interface structure is electrically connected to the first multi-layer circuit board 114 and the second multi-layer circuit board 116 in a vertical manner, for example. As shown in fig. 5, the first multilayer circuit board 114 is provided with a first multilayer board 114a and a plurality of first via structures 118a penetrating the first multilayer board 114 a. The second multi-layer circuit board 116 is provided with a second multi-layer board 116a and a plurality of second via structures 118b penetrating the second multi-layer board 116 a.
As shown in fig. 5, the vertical connection interface structure is disposed between the first multi-layer circuit board 114 and the second multi-layer circuit board 116 for electrically connecting the first multi-layer circuit board 114 and the second multi-layer circuit board 116, and includes a substrate 100, a plurality of conductive contact pads 106a, a dielectric insulating layer 108, and a set of conductive bumps 112. A plurality of conductive contact pads 106a are disposed on the substrate 100, and each of the plurality of conductive contact pads 106a is electrically insulated from or separated from each other. A dielectric insulating layer 108 is disposed on the conductive contact pads 106a and the substrate 100 to cover the conductive contact pads 106 a. The conductive bump sets 112 are disposed in the substrate 100 and the dielectric insulating layer 108, and the conductive bump sets 112 electrically connect each of the plurality of conductive contact pads 106a to the first via structure 118a and the second via structure 118b, respectively.
In the embodiment shown in fig. 5, the conductive bump set 112 includes a plurality of first conductive bumps 112a and a plurality of second conductive bumps 112b, the plurality of first conductive bumps 112a are disposed in the substrate 100, the plurality of second conductive bumps 112b are disposed in the dielectric insulating layer 108, two side surfaces 106b of each of the plurality of conductive contact pads 106a are respectively and correspondingly electrically connected between each of the plurality of first conductive bumps 112a and each of the plurality of second conductive bumps 112b, the plurality of first conductive bumps 112a are electrically connected to the first via structures 118a of the first multi-layer circuit board 114, and the plurality of second conductive bumps 112b are electrically connected to the second via structures 118b of the second multi-layer circuit board 116. In one embodiment, the first conductive bump 112a of the vertical connection interface structure is attached to the first via structure 118a by a heating and pressing method, for example, the melting point temperature of the first conductive bump 112a is equal to or less than a pressing temperature, wherein the pressing temperature is a temperature at which the substrate 100 of the vertical connection interface structure and the first multi-layer circuit board 114 and/or the dielectric insulating layer 108 and the second multi-layer circuit board 116 form a bonding state, and according to the pressing temperature, the surface of the first conductive bump 112a is melted and electrically connected to the contact pad of the first via structure 118 a. Similarly, the second conductive bump 112b of the vertical connection interface structure is attached to the second via structure 118b by a heating and pressing method, for example, the melting point temperature of the second conductive bump 112b is equal to or less than the pressing temperature, and the surface of the second conductive bump 112b is melted and electrically connected to the contact pad of the second via structure 118b according to the pressing temperature. In one embodiment, the pressing temperature is, for example, between 100 to 250 degrees celsius, but not limited thereto, for example, less than 100 degrees celsius or greater than 250 degrees celsius, depending on the material of the substrate 100, the dielectric insulating layer 108, the first conductive bump 112a and the second conductive bump 112 b.
As shown in fig. 5, in an embodiment, each of the plurality of conductive contact pads 106a is electrically connected to each of the plurality of first conductive bumps 112a and each of the plurality of second conductive bumps 112b along a common transmission path TP. In a preferred embodiment, each of the plurality of conductive contact pads 106a is electrically connected to each of the plurality of first conductive bumps 112a, each of the plurality of second conductive bumps 112b, the first via structure 118a, and the second via structure 118b along the collinear transmission path TP, which is a vertical transmission path, to solve the problem of a long signal transmission path between the multi-layered circuit boards. Further, the ratio of H to P in fig. 5 is smaller than the ratio of the longitudinal height H to the lateral pitch P in fig. 1 in the prior art, which solves the problem of processing a circuit board with a high aspect ratio.
Referring to fig. 6, a schematic diagram of a circuit board with a vertical connection interface structure according to a second embodiment of the invention is shown. The circuit board having the vertical connection interface structure includes a first multi-layer circuit board 114 and a vertical connection interface structure as shown in fig. 4C. In one embodiment, the vertical connection interface structure is, for example, electrically connected to the single-layer circuit board 114b in a vertical manner, and the single-layer circuit board 114b is provided with a single-layer board 114c and a plurality of first via structures 118a penetrating through the single-layer board 114 c.
As shown in fig. 6, the vertical connection interface structure is disposed on the single-layer circuit board 114b for electrically connecting the single-layer circuit board 114b, and includes a substrate 100, a plurality of conductive contact pads 106a and a plurality of first conductive bumps 112a, wherein the plurality of conductive contact pads 106a are disposed on the substrate 100, and each of the plurality of conductive contact pads 106a is electrically insulated from each other. A plurality of first conductive bumps 112a are disposed in the substrate 100, and each of the plurality of first conductive bumps 112a electrically connects each of the plurality of conductive contact pads 106a to each of the plurality of first via structures 118 a. In one embodiment, the single-layer circuit board 114b is a flexible circuit board. In one embodiment, each of the plurality of conductive contact pads 106a is electrically connected to each of the plurality of first conductive bumps 112a and the first via structure 118a along a common transmission path TP. The collinear transmission path TP is a vertical transmission path. In the embodiment of fig. 6, the single-layer circuit board 114b further includes a passivation layer 117 on the upper and lower surfaces of the single-layer board 114c to protect the first via structure 118a or to expose only a portion of the contact 115. In the embodiment shown in fig. 6, a circuit board having a vertical connection interface structure may be used for the pin pitch, for example, the vertical connection interface structure may be used to convert a smaller pin pitch of a circuit (not shown) above the first conductive bump 112a into a larger pin pitch (e.g., extended contact 115) of the single-layer circuit board 114 b.
In one embodiment, the first conductive bump 112a of the vertical connection interface structure is attached to the first via structure 118a by a heating and pressing method, for example, the melting point temperature of the first conductive bump 112a is equal to or less than a pressing temperature, wherein the pressing temperature refers to a temperature at which the substrate 100 of the vertical connection interface structure and the single-layer circuit board 114b form a bonding state, and the surface of the first conductive bump 112a is melted and electrically connected to the contact pad of the first via structure 118a according to the pressing temperature. In an embodiment, the pressing temperature is, for example, between 100 and 250 degrees celsius, but not limited thereto, for example, less than 100 degrees celsius or greater than 250 degrees celsius, depending on the material of the substrate 100 and the first conductive bump 112 a.
Referring to fig. 7, a schematic diagram of a circuit board with a vertical connection interface structure according to a third embodiment of the invention is shown. The circuit board with the vertical connection interface structure includes a single-layer circuit board 114b and two sets of vertical connection interface structures, wherein the single-layer circuit board 114b is provided with a single-layer board 114c and a plurality of first through hole structures 118a penetrating through the single-layer board 114 c.
As shown in fig. 7, two sets of vertical connection interface structures are respectively disposed on two side surfaces of the single-layer circuit board 114b for electrically connecting two end portions of each of the first via structures 118a, each set of vertical connection interface structures including a substrate 100, a plurality of conductive contact pads 106a, and a plurality of first conductive bumps 112 a. A plurality of conductive contact pads 106a are disposed on the substrate 100, and each of the plurality of conductive contact pads 106a is electrically insulated from each other. A plurality of first conductive bumps 112a are disposed in the substrate 100, and each of the plurality of first conductive bumps 112a electrically connects each of the plurality of conductive contact pads 106a to the first via structure 118 a.
As shown in fig. 7, in an embodiment, the single-layer circuit board 114b is a rigid circuit board. Each of the plurality of conductive contact pads 106a and each of the plurality of first conductive bumps 112a of the two sets of vertical connection interface structures are electrically connected to the first via structure 118a along a common transmission path TP. The collinear transmission path TP is a vertical transmission path. In the embodiment shown in fig. 7, the circuit board with the vertical connection interface structure can be used for stacking multiple layers of rigid circuit boards to increase the stacking number and strength of the multiple layers of circuit boards, and it should be noted that fig. 7 only uses one layer of single-layer circuit board 114b as an example, but is not limited thereto. In one embodiment, the first conductive bump 112a of the vertical connection interface structure is attached to the first via structure 118a by a heating and pressing method, for example, the melting point temperature of the first conductive bump 112a is equal to or less than a pressing temperature, wherein the pressing temperature refers to a temperature at which the substrate 100 of the vertical connection interface structure and the single-layer circuit board 114b form a bonding state, and the surface of the first conductive bump 112a is melted and electrically connected to the contact pad of the first via structure 118a according to the pressing temperature. In an embodiment, the bonding temperature is, for example, between 100 to 250 degrees celsius, but not limited thereto, for example, less than 100 degrees celsius or greater than 250 degrees celsius, depending on the material of the first conductive bump 112 a.
In summary, the vertical connection interface structure, the circuit board having the same and the manufacturing method thereof according to the present invention connect at least one layer of circuit board through the vertical connection interface structure to solve the problem of high aspect ratio processing of the circuit board. At least one layer of circuit board is connected through the vertical connection interface structure, so that the problem of long signal transmission path among the multiple layers of circuit boards is solved. And at least one layer of circuit board, such as a layer of flexible circuit board and at least one layer of rigid circuit board, is connected through the vertical connection interface structure to improve the problems of stacking structure of circuit board and pin pitch conversion.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (20)
1. A method of manufacturing a vertical connection interface structure for a circuit board, comprising the steps of:
forming a conductive layer on a substrate;
forming a photoresist layer on the conductive layer;
performing a photolithography process to define a contact pad pattern by the photoresist layer and expose a portion of the conductive layer;
etching the exposed conductive layer using the contact pad pattern as an etching mask to form a plurality of conductive contact pads, wherein each of the plurality of conductive contact pads is electrically insulated from each other;
removing the photoresist layer to expose the conductive contact pads;
forming a dielectric insulating layer on the conductive contact pads and the substrate to cover the conductive contact pads;
forming a plurality of openings in the substrate and the dielectric insulating layer at positions corresponding to the plurality of conductive contact pads, respectively, and exposing the conductive contact pads in the plurality of openings of the substrate and the dielectric insulating layer; and
forming a conductive material filled in each of the plurality of openings to form a conductive bump group, so that the two side surfaces of each of the plurality of conductive contact pads are electrically connected to the conductive bump group respectively;
the conductive bump groups are made of conductive paste or conductive adhesive, and the surface of each conductive bump group, which is far away from the conductive contact pad, does not exceed the surface of the substrate or the dielectric insulating layer.
2. The method of claim 1, wherein the substrate is a dielectric insulating material.
3. The method of claim 1, wherein the step of forming a dielectric insulating layer over the conductive pads and the substrate to cover the conductive pads comprises attaching a dielectric insulating layer over the conductive pads and the substrate.
4. The method as claimed in claim 1, wherein the step of forming a conductive material in each of the plurality of openings to form the conductive bump group such that the two side surfaces of each of the plurality of conductive pads are electrically connected to the conductive bump group respectively comprises forming a plurality of first conductive bumps and a plurality of second conductive bumps of the conductive bump group, the plurality of first conductive bumps are disposed in the substrate, the plurality of second conductive bumps are disposed in the dielectric insulating layer, and wherein the two side surfaces of each of the plurality of conductive pads are electrically connected to each of the plurality of first conductive bumps and each of the plurality of second conductive bumps respectively.
5. A method of manufacturing a vertical connection interface structure for a circuit board, comprising the steps of:
forming a conductive layer on a substrate;
forming a photoresist layer on the conductive layer;
performing a photolithography process to define a contact pad pattern by the photoresist layer and expose a portion of the conductive layer;
etching the exposed conductive layer using the contact pad pattern as an etching mask to form a plurality of conductive contact pads, each of the plurality of conductive contact pads being electrically insulated from each other;
forming a plurality of openings on the substrate at positions corresponding to the plurality of conductive contact pads, and exposing the conductive contact pads in the plurality of openings of the substrate;
filling a conductive material into the openings to form a plurality of first conductive bumps, so that one side surface of each conductive contact pad is correspondingly and electrically connected with each first conductive bump; and
removing the photoresist layer;
the first conductive bump is made of conductive paste or conductive adhesive, and the surface of the first conductive bump, which is far away from the conductive contact pad, does not exceed the surface of the substrate.
6. The method of claim 5, wherein the substrate is a dielectric insulating material.
7. The method of claim 5, wherein the step of removing the photoresist layer is performed before or after the step of forming the first conductive bumps.
8. A circuit board having a vertical connection interface structure, comprising:
the first multilayer circuit board is provided with a first multilayer board and a plurality of first through hole structures penetrating through the first multilayer board;
the second multilayer circuit board is provided with a second multilayer board and a plurality of second through hole structures penetrating through the second multilayer board; and
a vertical connection interface structure disposed between the first multilayer circuit board and the second multilayer circuit board for electrically connecting the first multilayer circuit board and the second multilayer circuit board, the vertical connection interface structure comprising:
a substrate;
a plurality of conductive contact pads disposed on the substrate, each of the plurality of conductive contact pads being electrically insulated from each other;
a dielectric insulating layer disposed on the conductive contact pads and on the substrate to cover the conductive contact pads; and
the conductive bump group is arranged in the substrate and the dielectric insulating layer, is respectively in direct contact with the first through hole structure and the second through hole structure in a heating and pressing mode and is used for electrically connecting each conductive contact pad to the first through hole structure and the second through hole structure, wherein the conductive bump group is made of conductive paste or conductive adhesive, and the surface of the conductive bump group, far away from the conductive contact pads, does not exceed the surface of the substrate.
9. The circuit board of claim 8, wherein the set of conductive bumps comprises a plurality of first conductive bumps disposed in the substrate and a plurality of second conductive bumps disposed in the dielectric insulating layer, two side surfaces of each of the plurality of conductive contact pads are electrically connected between each of the plurality of first conductive bumps and each of the plurality of second conductive bumps, respectively, and the plurality of first conductive bumps are electrically connected to the first via structures of the first multi-layer circuit board and the plurality of second conductive bumps are electrically connected to the second via structures of the second multi-layer circuit board.
10. The circuit board of claim 9, wherein each of the plurality of conductive contact pads is electrically connected to each of the plurality of first conductive bumps and each of the plurality of second conductive bumps along a common transmission path.
11. The circuit board of claim 10, wherein each of the plurality of conductive contact pads is electrically connected to each of the plurality of first conductive bumps, each of the plurality of second conductive bumps, the first via structure, and the second via structure along a common transmission path.
12. The circuit board with vertical connection interface structure as claimed in any one of claims 10 or 11, wherein said collinear transmission paths are vertical transmission paths.
13. A circuit board having a vertical connection interface structure, comprising:
the single-layer circuit board is provided with a single-layer board and a plurality of first through hole structures penetrating through the single-layer board; and
a vertical connection interface structure, set up in on the individual layer circuit board for electric connection the individual layer circuit board, vertical connection interface structure includes:
a substrate;
a plurality of conductive contact pads disposed on the substrate, each of the plurality of conductive contact pads being electrically insulated from each other; and
the plurality of first conductive bumps are arranged in the substrate, each first conductive bump is directly contacted with the corresponding first conductive bump in a heating and pressing mode and is used for electrically connecting each conductive contact pad to each first through hole structure, the plurality of first conductive bumps are made of conductive paste or conductive adhesive materials, and the surface of each first conductive bump, far away from the conductive contact pad, does not exceed the surface of the substrate.
14. The circuit board with vertical connection interface structure as claimed in claim 13, wherein the single-layer circuit board is a flexible circuit board.
15. The circuit board of claim 13, wherein each of the plurality of conductive contact pads is electrically connected to each of the plurality of first conductive bumps and the first via structure along a common transmission path.
16. The circuit board having a vertical connection interface structure of claim 15, wherein said collinear transmission paths are vertical transmission paths.
17. A circuit board having a vertical connection interface structure, comprising:
the single-layer circuit board is provided with a single-layer board and a plurality of first through hole structures penetrating through the single-layer board; and
two sets of perpendicular connection interface structures, set up respectively in the both sides of individual layer circuit board are surperficial, be used for each electric connection a plurality of first through-hole structure's both ends, each group of perpendicular connection interface structure includes:
a substrate;
a plurality of conductive contact pads disposed on the substrate, each of the plurality of conductive contact pads being electrically insulated from each other; and
the plurality of first conductive bumps are arranged in the substrate, each first conductive bump is directly contacted with the corresponding first through hole structure in a heating and pressing mode and is used for electrically connecting each conductive contact pad to the first through hole structure, the plurality of first conductive bumps are made of conductive paste or conductive adhesive materials, and the surface of each first conductive bump, far away from the conductive contact pad, does not exceed the surface of the substrate.
18. The circuit board with vertical connection interface structure as claimed in claim 17, wherein the single-layer circuit board is a rigid circuit board.
19. The circuit board of claim 17, wherein each of the conductive contact pads and each of the first conductive bumps of the two sets of vertical connection interface structures are electrically connected to the first via structures along a common transmission path.
20. The circuit board having a vertical connection interface structure of claim 19, wherein said collinear transmission paths are vertical transmission paths.
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TW105140126A TWI626870B (en) | 2016-12-05 | 2016-12-05 | Vertical connection interface structure, circuit board having interface structure and manufacturing method thereof |
TW105140126 | 2016-12-05 |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH11168279A (en) * | 1997-12-03 | 1999-06-22 | Fujitsu Ltd | Multilayer circuit board and manufacture thereof |
JP2000312063A (en) * | 1999-04-28 | 2000-11-07 | Kyocera Corp | Wiring substrate and manufacture thereof |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2000076281A1 (en) * | 1999-06-02 | 2000-12-14 | Ibiden Co., Ltd. | Multilayer printed wiring board and method of manufacturing multilayer printed wiring board |
JP4045143B2 (en) * | 2002-02-18 | 2008-02-13 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | Manufacturing method of wiring film connecting member and manufacturing method of multilayer wiring board |
JP4075673B2 (en) * | 2003-04-22 | 2008-04-16 | 松下電工株式会社 | Copper-clad laminate for multilayer printed wiring board, multilayer printed wiring board, and method for manufacturing multilayer printed wiring board |
TWI561133B (en) * | 2014-11-10 | 2016-12-01 | Boardtek Electronics Corp | Circuit board with electroplated type and manufacturing method thereof |
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2016
- 2016-12-05 TW TW105140126A patent/TWI626870B/en active
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2017
- 2017-02-06 CN CN201710066115.4A patent/CN108156754B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH11168279A (en) * | 1997-12-03 | 1999-06-22 | Fujitsu Ltd | Multilayer circuit board and manufacture thereof |
JP2000312063A (en) * | 1999-04-28 | 2000-11-07 | Kyocera Corp | Wiring substrate and manufacture thereof |
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CN108156754A (en) | 2018-06-12 |
TW201822605A (en) | 2018-06-16 |
TWI626870B (en) | 2018-06-11 |
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