CN108155905B - 用于高分辨率dco的数字控制可变电抗器结构 - Google Patents

用于高分辨率dco的数字控制可变电抗器结构 Download PDF

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CN108155905B
CN108155905B CN201711274097.5A CN201711274097A CN108155905B CN 108155905 B CN108155905 B CN 108155905B CN 201711274097 A CN201711274097 A CN 201711274097A CN 108155905 B CN108155905 B CN 108155905B
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CN108155905A (zh
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张弛
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Abstract

本发明涉及用于高分辨率DCO的数字控制可变电抗器结构，其中，一种数字控制可变电抗器装置包含：本体nMOS场效应晶体管集合，其本体绑定至接地，该本体nMOS场效应晶体管集合具有：第一晶体管，包括：源极，耦合至直流电压源；以与栅极，耦合至数字控制振荡器；第二晶体管，包括：源极，耦合至该直流电压源；以与栅极，耦合至该数字控制振荡器；以及第三晶体管，包括：源极，耦合至该第一晶体管的漏极；以及漏极，耦合至该第二晶体管的漏极。数字控制可变电抗器中的晶体管可为有耦合至直流电压源的背栅极的FDSOI nMOS装置。

Description

用于高分辨率DCO的数字控制可变电抗器结构
技术领域
揭示于本文的专利目标是有关于集成电路。更特别的是，本发明有关于一种金属氧化物半导体(MOS)可变电抗器。
背景技术
可变电抗器为具有取决于外加电压的电容的半导体二极管且常用于现代通讯系统。集成电路常包括可变电抗器(varactor也称为“variable reactor”)。可变电抗器提供有基于表现在端子的电压及控制电压的可变电容的电压控制式电容组件。金属氧化物半导体(MOS)可变电抗器可具有施加至栅极端子的控制电压，该栅极端子可控制施加特定电压至装置的其余端子所得到的电容。
由于可变电抗器基于被逆偏压的P-N结，该端子通常被偏压成没有电流流动越过P-N结，藉此形成电容器。不过，改变在MOS可变电抗器的栅极上的偏压造成在栅极下面形成改变流动通过可变电抗器的电流的空乏或累积区。所得到的有效电容因此是可变的，且相依于电压。这使得可变电抗器利于用作电压控制型电容器。可变电抗器特别有用于振荡器、RF电路及习知通讯技术以产生用作输入信号的给定频率。
有两种常用的习知MOS可变电抗器。一种为实作简单的n-MOS累积型可变电抗器。不过，在n-MOS累积型可变电抗器中，寄生二极管在Vcontrol小于0时由于衬底短路接地(shorted to ground)而被开启。这导致在调控范围(tuning range)的一半期间有低Q值(Qfactor)。另一种为防止泄露到衬底的反转MOS可变电抗器，其具有永远被逆偏压的寄生二极管。不过，反转MOS可变电抗器有狭窄的调控范围。
习知可变电抗器应用使用例如锁相回路(PLL)的控制系统以产生输出信号以响应给定的输入信号。在许多电子应用中，PLL为使用于各种计时、同步及信号处理功能的基本电路。PLL的重要应用是在电信及雷达系统，在此它们用来产生载波频率、局部振荡器频率及中间频率信号。无线通信系统的目前趋势是朝向使用全数字化PLL(ADPLL)，相较于传统的模拟PLL，它们提供以下优点：较小的芯片尺寸、更好的可扩充性、以及广阔的可再组构性(re-configurability)。
发明内容
本揭示内容的第一态样提供一种数字控制可变电抗器装置，其使用本体绑定至(bulk tied to)接地的本体nMOS场效应晶体管集合，该本体nMOS场效应晶体管集合具有：第一晶体管，包括：源极，耦合至直流电压源；以与栅极，耦合至数字控制振荡器；第二晶体管，包括：源极，耦合至该直流电压源；以与栅极，耦合至该数字控制振荡器；以及第三晶体管，包括：源极，耦合至该第一晶体管的漏极；以及漏极，耦合至该第二晶体管的漏极。
本揭示内容的第二态样提供一种数字控制可变电抗器装置，其使用栅极耦合至(gate coupled to)连接至Vbb电位电压的背栅极电压的完全耗尽型绝缘体上硅(FDSOI)nMOS场效应晶体管集合，该FDSOI nMOS场效应晶体管具有：第一晶体管，其包括：源极，耦合至直流电压源；以与栅极，耦合至数字控制振荡器；第二晶体管，其包括：源极，耦合至该直流电压源；以与栅极，耦合至该数字控制振荡器；以及第三晶体管，其包括：源极，耦合至该第一晶体管的漏极；以及漏极，耦合至该第二晶体管的漏极。
本揭示内容的第三态样提供一种实现极精细频率调控分辨率的方法，其使用以下步骤：决定一直流偏压(DC bias voltage)给数字控制振荡器电感电容(DCO LC)共振腔，该数字控制振荡器电感电容(DCO LC)共振腔栅极连接至第一NMOS晶体管装置与第二NMOS晶体管装置；施加直流偏压(DC biased voltage)至一节点，该节点连接至该第一NMOS晶体管装置的源极与该第二NMOS晶体管装置的源极；产生由第三NMOS晶体管装置的栅极接收的控制信号；设定该第一NMOS晶体管装置、该第二NMOS晶体管装置及该第三NMOS晶体管装置的背栅极电压至接地；以及调整该背栅极电压以重新组构该直流偏压及该控制信号的调控范围。
附图说明
由以下本揭示内容各方面结合描绘本发明各种具体实施例的附图的详细说明可更加明白本揭示内容以上及其他的特征。
图1根据本揭示内容的数个具体实施例图示可变电抗器电路的示意图。
图2根据本揭示内容的数个具体实施例图示可变电抗器结构的简化布置图。
图3根据本揭示内容的一具体实施例图标IC结构的简化可变电抗器精细单元模型(simplified varactor fine unit model)。
图4根据本揭示内容的一具体实施例图示处于关闭状态的可变电抗器电路的简化模型。
图5根据本揭示内容的一具体实施例图示处于开启状态的可变电抗器电路的简化模型。
图6根据本揭示内容的一具体实施例图标IC结构的可变电抗器精细单元实体设计横截面。
图7根据本揭示内容的数个具体实施例图示可变电抗器装置的电容-电压曲线图。
图8根据本揭示内容的替代具体实施例图示可变电抗器装置的电容-电压曲线图。
图9根据本揭示内容的替代具体实施例图示可变电抗器装置的电容-电压曲线图。
应注意，本揭示内容的附图不一定按比例绘制。附图只是用来图示本揭示内容的典型方面，因此不应被视为用来限制本揭示内容的范畴。附图中，类似的组件用相同的附图标记表示。
具体实施方式
在以下说明中，参考形成其一部份且举例图示可实施本发明教导的特定示范具体实施例的附图。充分详述这些具体实施例使得本领域技术人员能够实施本发明教导，且应了解，可使用其他具体实施例及做出改变而不脱离本发明教导的范畴。因此，以下说明仅供图解说明。
如上述，揭示于本文的专利目标是有关于集成电路。更特别的是，该专利目标有关于有精细信号分辨率(fine signal resolution)的金属氧化物半导体(MOS)可变电抗器。此外，本揭示内容有关于用于有极精细分辨率的先进数字锁相回路(ADPLL)的数字控制振荡器(DCO)的方法及设备的具体实施例。该分辨率主要取决于数字控制可变电抗器(DCV)的电容调控分辨率。DCV的分辨率取决于使用于DCV装置的开关致动电压的开启电容(Con)与关闭电容(Coff)，且基于每一精细代码步阶(fine code step)的电容变化。另外，在习知可变电抗器中，Con永远等于装置在形成时的栅极至沟道氧化物电容(Cox)。由于这些习知应用为了较高的速度而想要较高的Cox，所以解析能力中存在折衷。当前的办法避免此一折衷。
推荐的本发明具体实施例为一种可变电抗器，在一具体实施例中，其包含以有差异的方式组构成可形成三指装置(3-fingered device)的3个NMOS晶体管。本揭示内容的具体实施例不需要交流耦合电容器(AC coupling capacitor)，或直流偏压电阻器(DC biasresistor)，这导致寄生二极管漏电减少，且节省每个装置的空间。
图1根据本揭示内容的数个具体实施例图示可变电抗器100。更特别的是，可变电抗器100在FDSOI制程中用作可切换差分电容器的为反井型(flipped well)NMOS。如以下所详述的，相较于习知可变电抗器，可变电抗器100的组构大幅改善精细分辨率效能(每一步阶约有22aF电容变化)，精细调控电容范围(每10位调控字(tuning word)约有23fF)，较低的寄生电容且对偏压有较低敏感性而可大幅减少相位噪声。根据可变电抗器100的一具体实施例，该装置包括由数个晶体管组成的序列。此晶体管序列可包括第一晶体管102、第二晶体管104及第三晶体管106。
仍参考图1，第一晶体管102与第二晶体管104是源极耦合至(source coupled to)直流电压源114(Vs)节点，该节点有约0.5伏特的直流偏压以确保第一晶体管102与第二晶体管104保持处于关闭状态。第一晶体管102也栅极耦合至(gate coupled to)提供约0.5伏特的电压116(Vp)的数字控制振荡器电感电容共振腔(digitally controlled oscillatorLC tank)，同时第二晶体管104栅极耦合至提供约0.5伏特的电压(Vn)的数字控制振荡器。第三晶体管106源极耦合至第一晶体管102的漏极；且漏极耦合至第二晶体管104的漏极。第三晶体管106的栅极接收可变电抗器的电压控制信号(Vc)110，它约有0至1.2伏特，允许第三晶体管在Vc 110约有1.2伏特时处于开启状态，以及在Vc 110约有0伏特时处于关闭状态。第一晶体管102、第二晶体管104及第三晶体管106的本体或背栅极电压(Vbb)112在本体制程(bulk process)绑定至接地，或在FDSOI制程绑定至选定电压。藉由改变Vbb 112，允许在给定范围中操作Vc 110及Vs 114的电压以控制第一晶体管102及第二晶体管104以确保在处于所欲关闭状态时的操作。
图2根据本揭示内容的数个具体实施例图示简化的可变电抗器结构200。可变电抗器结构200包括由3个晶体管装置组成的序列。此晶体管装置序列可包括第一晶体管202、第二晶体管204及第三晶体管206。在以可变电抗器结构200具体实施时，第一晶体管202及第二晶体管204的漏极是浮动的，且第三晶体管206用作开关。第一晶体管202与第二晶体管204共享电压在约0.5伏特的共享Vs节点208，致使装置用处于关闭状态的第一晶体管202及第二晶体管204操作。
图3根据本揭示内容的一具体实施例图标IC结构的简化的可变电抗器精细单元300模型。可变电抗器精细单元300包括由3个晶体管装置组成的序列。此晶体管装置序列可包括第一晶体管302、第二晶体管304及第三晶体管306。在以可变电抗器精细单元300具体实施时，当可变电抗器精细单元处于关闭状态时，意谓第一晶体管302及第二晶体管304的源极电压308设定在约0.5伏特(Vs)。第三晶体管306也关闭，因为控制电压310(Vc)设定在约0.0伏特。在此具体实施例中，第一晶体管302及第二晶体管304的漏极是浮动的，在第三晶体管306的下部形成沟道。第一晶体管302与第二晶体管304的栅极电容大约为Cgs(ov)+Cgb，在此Cgs(ov)为第一晶体管302与第二晶体管304的栅极至源极重迭电容，以及Cgb为栅极至本体的(或FDSOI技术的背栅极电压)。在此具体实施例中，差分可变电抗器电容由方程式Cv_off＝(Cgs(ov)+Cgb)/2给出。
进一步参考图3，当可变电抗器精细单元300处于开启状态时，第一晶体管302与第二晶体管304的源极电压308设定在约0.5伏特(Vs)，且因为控制信号电压310(Vc)大约设定在1.2伏特，所以第三晶体管306处于开启状态。在此具体实施例中，在处于开启状态时，在第三晶体管沟道的中心处形成虚拟接地312，且第一晶体管与第二晶体管的栅极电容变成Cgs(ov)+Cgd(ov)+Cgb。此具体实施例，在处于此开启状态时，差分可变电抗器电容由方程式Cv_on＝(Cgs(ov)+Cgd(ov)+Cgb)/2给出。栅极至源极重迭电容与栅极至漏极重迭电容有相同的数值用于全对称MOS制程。开启/关闭状态的整体可变电抗器电容差额大约为Cgs(ov)/2，且在此较佳具体实施例下；有取决于沟道宽度(W)、氧化物厚度(tox)、重迭长度、栅极高度和漏极结深度的Cgs(ov)。
图4图示简化的可变电抗器模型400。此简化的可变电抗器模型400图标在可变电抗器精细单元300(图3)处于关闭状态时会被组构的第一晶体管402与第二晶体管404。此具体实施例的差分可变电抗器电容由方程式Cv_off＝(Cgs(ov)+Cgb)/2给出。
图5图示简化的可变电抗器模型500。此简化的可变电抗器模型500图标在可变电抗器精细单元300(图3)处于开启状态时会被组构的第一晶体管502与第二晶体管504。当可变电抗器精细单元300处于开启状态时，第一晶体管302与第二晶体管304的源极电压308设定在约0.5伏特(Vs)，且因为控制信号电压310(Vc)大约设定在1.2伏特，所以第三晶体管306处于开启状态，。此具体实施例，在处于此开启状态时，在第三晶体管的沟道的中心(为求简洁未予图示)处形成虚拟接地510。此具体实施例在处于开启状态时，差分可变电抗器电容由方程式Cv_on＝(Cgs(ov)+Cgd(ov)+Cgb)/2给出。
图6根据本揭示内容的一具体实施例图标在IC结构内的可变电抗器精细单元实体设计横截面600。可变电抗器精细单元实体设计横截面600包括由3个晶体管装置组成的序列，且用作为切换式差分电容器，其取代使用于有此装置的工作电容的习知VCO技术的金属氧化物金属电容器。此晶体管装置序列可包括第一晶体管602、第二晶体管604及第三晶体管606。第一晶体管602与第二晶体管604源极耦合至直流电压源610节点。第一晶体管602也栅极耦合至提供电压612(Vp)的数字控制振荡器电感电容共振腔，同时第二晶体管604栅极耦合至提供电压616(Vn)的数字控制振荡器电感电容共振腔。第三晶体管606源极耦合至第一晶体管602的漏极；且漏极耦合至第二晶体管604的漏极。第三晶体管606的栅极接收可变电抗器的电压控制信号(Vc)620，允许第三晶体管取决于Vc 620的电压而被组构为开启状态或关闭状态。第一晶体管602、第二晶体管604及第三晶体管606的本体或背栅极电压(Vbb)618在本体制程绑定至接地，或在FDSOI制程绑定至选定电压。藉由改变Vbb 618，允许在给定范围中操作Vc 620及Vs 610电压以控制第一晶体管602及第二晶体管604，从而确保在处于所欲关闭状态时的操作。
图7根据本揭示内容的替代具体实施例图示可变电抗器装置的一般电容-电压的曲线图700。如曲线图700所示，电容的变化图标成在开关信号的电压(约1.2v)的过程中约有22aF。响应曲线图700中信号在开启/关闭状态拥有平坦宽广的频带，数字控制振荡器大体不受输入电压的任何直流偏压噪声影响。可用沟道的长度与宽度的变化组合来调整如曲线图700所示的一般电容特性。
图8根据本揭示内容的替代具体实施例图示可变电抗器装置的电容-电压的曲线图800。曲线图800图标在改变可变电抗器装置的沟道长度时使沟道宽度保持一致的推荐可变电抗器装置的具体实施例。曲线图800进一步图标电容变化对于沟道长度的变化组合保持不变，同时致能可调整的调控范围。
图9根据本揭示内容的替代具体实施例图示可变电抗器装置的电容-电压的曲线图900。曲线图900图标在改变可变电抗器装置的沟道宽度时使沟道长度保持一致的推荐可变电抗器装置的具体实施例。该精细单元实现约22aF电容步阶的精细分辨率，且步阶随着沟道宽度递减而渐小。较大宽度的效益是精细调控比(fine tuning ratio)的范围增加。
使用于本文的术语只为了描述特定示范具体实施例并非旨在限制用。如本文所使用的，单数形式“一(a)”、“一(an)”、及“该”可能旨在也包括复数形式，除非上下文另有明示。用语“包含(comprises)”、“包含(comprising)”、“包括(including)”、及“具有(having)”是包含用语，因此是指明存在所述特征、整数、步骤、操作、组件及/或组件，但是不排除存在或添加一或多个其他特征、整数、步骤、操作、组件、组件及/或由彼等组成的群组。描述于本文的方法步骤、程序、及操作不应视为一定需要以所述或所解说的特定顺序执行，除非明确说明为执行的顺序。也应了解，可采用额外或替代步骤。
为了图示及说明，已呈现本发明的各种方面。非旨在以所揭示的确切形式来穷尽或限制本发明，且许多修改及变体显然是有可能的。本技艺人士明白此类修改及变体包括在如随附权利要求书所界定的本发明范畴内。
为了图解说明已呈现本发明的各种具体实施例的描述，但是并非旨在穷尽或限定于所揭示的具体实施例。本领域技术人员明白仍有许多修改及变体而不脱离所述具体实施例的范畴及精神。使用于本文的术语经选定成可最好地解释具体实施例的原理、实际应用或优于在市场上可找到的技术的技术改善，或使得本领域技术人员能够了解揭示于本文的具体实施例。

Claims (18)

1.一种数字控制可变电抗器装置，包含：
本体nMOS场效应晶体管集合，其本体绑定至接地，该本体nMOS场效应晶体管集合具有：
第一晶体管，包括：
第一源极，耦合至直流电压源；以及
第一栅极，耦合至数字控制振荡器；
第二晶体管，包括：
第二源极，耦合至该直流电压源；以及
第二栅极，耦合至该数字控制振荡器；以及
第三晶体管，包括：
第三源极，耦合至该第一晶体管的第一漏极；以及
第三漏极，耦合至该第二晶体管的第二漏极，
其中，该第一晶体管的该第一栅极与该第二晶体管的该第二栅极耦合至该数字控制振荡器的电感电容共振腔的各自的正极及负极节点。
2.如权利要求1所述的装置，其中，该数字控制振荡器的电感电容共振腔有约0.5伏特的偏压。
3.如权利要求1所述的装置，其中，该直流电压源提供0.5伏特以使该第一晶体管及该第二晶体管处于关闭状态。
4.如权利要求1所述的装置，其中，该第三晶体管的第三栅极接收控制信号。
5.如权利要求4所述的装置，其中，该控制信号在0至1.2伏特的电压范围中。
6.如权利要求5所述的装置，其中：
响应该控制信号被设定在约0伏特，使该第三晶体管处于关闭状态；以及
响应该控制信号被设定在约1.2伏特，使该第三晶体管处于开启状态。
7.如权利要求1所述的装置，其中，通过背栅极电压的调整，该第一晶体管的该第一栅极与该第二晶体管的该第二栅极接收一可组构电压范围。
8.一种数字控制可变电抗器装置，包含：
完全耗尽型绝缘体上硅(FDSOI) nMOS场效应晶体管集合，栅极耦合至连接至Vbb电位电压的背栅极电压，该完全耗尽型绝缘体上硅(FDSOI) nMOS场效应晶体管具有：
第一晶体管，包括：
第一源极，耦合至直流电压源；以及
第一栅极，耦合至数字控制振荡器；
第二晶体管，包括：
第二源极，耦合至该直流电压源；以及
第二栅极，耦合至该数字控制振荡器；以及
第三晶体管，包括：
第三源极，耦合至该第一晶体管的第一漏极；以及
第三漏极，耦合至该第二晶体管的第二漏极，
其中，该第一晶体管的该第一栅极与该第二晶体管的该第二栅极耦合至该数字控制振荡器的电感电容共振腔的正极及负极节点。
9.如权利要求8所述的装置，其中，该数字控制振荡器的电感电容共振腔有约0.5伏特的偏压。
10.如权利要求8所述的装置，其中，该直流电压源接收0.5伏特以使该第一晶体管及该第二晶体管处于关闭状态。
11.如权利要求8所述的装置，其中，该第三晶体管的第三栅极接收控制信号。
12.如权利要求11所述的装置，其中，该控制信号是在0至1.2伏特的电压范围中。
13.如权利要求12所述的装置，其中：
响应该控制信号被设定在约0伏特，使该第三晶体管处于关闭状态；以及
响应该控制信号被设定在约1.2伏特，使该第三晶体管处于开启状态。
14.如权利要求8所述的装置，其中，通过该Vbb电位电压的调整，该可变电抗器装置拥有用于该第一晶体管的该第一栅极及该第二晶体管的该第二栅极的电压范围。
15.一种实现极精细频率调控分辨率的方法，包含：
施加偏压至数字控制振荡器电感电容(DCO LC)共振腔，该数字控制振荡器电感电容(DCO LC)共振腔栅极连接至第一NMOS晶体管装置的第一栅极与第二NMOS晶体管装置的第二栅极；
施加直流偏压至一节点，该节点连接至该第一NMOS晶体管装置的第一源极与该第二NMOS晶体管装置的第二源极；
产生由第三NMOS晶体管装置的第三栅极接收的控制信号；
设定该第一NMOS晶体管装置、该第二NMOS晶体管装置及该第三NMOS晶体管装置的背栅极电压至接地；以及
调整该背栅极电压以重新组构该直流偏压及该控制信号的调控范围。
16.如权利要求15所述的方法，其中，施加该偏压至该数字控制振荡器电感电容共振腔包括：
施加约0.5伏特的电压至该数字控制振荡器电感电容共振腔。
17.如权利要求15所述的方法，其中，该方法包括在该数字控制振荡器电感电容共振腔中的晶体管装置阵列。
18.如权利要求15所述的方法，其中，产生该控制信号包括：
产生范围在0至1.2伏特之间的控制信号：
其中，通过该范围，使该第一NMOS晶体管装置及该第二NMOS晶体管装置保持在关闭状态；
其中，响应施加0.0至0.6伏特至该控制信号，使该第三NMOS晶体管处于关闭状态；以及
其中，响应施加0.9至1.2伏特至该控制信号，使该第三NMOS晶体管处于开启状态。
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CN101753117A (zh) * 2008-12-16 2010-06-23 晨星软件研发(深圳)有限公司 环震荡器中的延迟单元及相关方法
CN104954011A (zh) * 2014-03-27 2015-09-30 上海斐讯数据通信技术有限公司 一种压控振荡器

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