CN109639256B - 背栅控制可变电抗器 - Google Patents

背栅控制可变电抗器 Download PDF

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CN109639256B
CN109639256B CN201810034723.1A CN201810034723A CN109639256B CN 109639256 B CN109639256 B CN 109639256B CN 201810034723 A CN201810034723 A CN 201810034723A CN 109639256 B CN109639256 B CN 109639256B
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张弛
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Lattice Core Usa Inc
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Abstract

本发明涉及背栅控制可变电抗器。本公开涉及半导体结构，更特别地，涉及背栅控制可变电抗器及其使用和制造方法。该可变电抗器包括：并联设置的多个晶体管；耦合到所述多个晶体管的背栅的电压控制节点；以及耦合到所述多个晶体管的源极和漏极的偏置电压节点。

Description

背栅控制可变电抗器
技术领域
本发明涉及半导体结构，更特别地，涉及一种背栅控制可变电抗器及其使用和制造方法。
背景技术
可变电抗器用在电压控制振荡器(VCO)中用于频率调谐，其中VCO频率由控制电压调谐。电压控制振荡器具有许多应用，诸如用于FM发射机和锁相环的频率调制。锁相环可以用于例如调谐蜂窝电话或其他无线设备的频率合成器。
基于二极管的可变电抗器以反向偏置状态操作，其中反向偏置的量控制耗尽区的厚度并由此控制可变电抗器的结电容。电容与施加电压的平方根成反比。常规的基于MOS的可变电抗器以积累模式或反转模式操作。栅电容是相对栅偏置的函数。也就是，可变电抗器显示作为控制电压(C-V曲线)的函数的电容。通过示例的方式，基于LC(电感器/电容器)库(tank)的VCO具有作为可变电抗器电容的函数的输出频率。
常规的可变电抗器表现出高增益、高噪声、高AC耦合和有限的控制电压范围。更具体地，常规的基于金属氧化物半导体电容器(MOSCAP)的可变电抗器使用Vgs电压作为控制电压，其具有陡的斜率的C-V曲线。电容值对控制电压电平敏感，其中VCO增益(Kv)高。另外，由于高增益，VCO相位噪声对控制电压噪声敏感。此外，为了偏置基于MOSCAP的可变电抗器，在MOSCAP器件的栅极上需要AC耦合电容器和DC耦合电阻器，这增加了设计复杂度、面积和寄生电容。电阻也贡献了噪声。最后，基于MOSCAP的可变电抗器具有受到栅极上的可靠性约束限制的小的控制电压范围。
发明内容
在本公开的一方面，一种可变电抗器包括：多个并联设置的晶体管；耦合到所述多个晶体管的背栅的电压控制节点；以及耦合到所述多个晶体管的源极和漏极的偏置电压节点。
在本公开的一方面，一种可变电抗器包括：直接耦合到一对晶体管的背栅以实现栅电容调谐的电压控制节点；以及直接耦合到所述晶体管的源极和漏极的偏置电压节点。所述晶体管通过在所述电压控制节点处施加的电压而被背栅控制。
在本公开的一方面，一种使用可变电抗器的方法包括应用所述可变电抗器的阈值电压对背栅偏置的依赖性以实现栅电容调谐。
附图说明
通过本公开的示例性实施例的非限制性实例并参考所述多个附图，在以下详细描述中描述本公开。
图1示出了根据本公开的方面的背栅控制可变电抗器。
图2示出了根据本公开的方面的直接耦合到背栅控制可变电抗器的VCO。
图3示出了根据本公开的方面的直接耦合到背栅控制可变电抗器的VCO。
图4示出了根据本公开的方面的包括背栅控制可变电抗器的模拟的C-V曲线。
图5示出了根据本公开的方面的背栅控制可变电抗器的频率调谐和Kv曲线。
具体实施方式
本公开涉及半导体结构，更特别地，涉及背栅控制可变电抗器及其使用和制造方法。更具体地，本公开提供了一种使用背栅作为电压控制(VCTRL)节点的可变电抗器。有利地，与常规可变电抗器相比，背栅控制可变电抗器具有低噪声、低增益、直接耦合到VCO的能力以及宽的控制电压范围。
在实施例中，本文描述的背栅控制可变电抗器使用阈值电压对背栅偏置的依赖性以实现栅电容调谐。另外，可变电抗器的前栅(晶体管)可以直接耦合到VCO的LC-库(没有耦合电阻器或耦合电容器)，其中VCO使用背栅控制可变电抗器。例如，背栅控制可变电抗器可以用于适用于5G 28GHz频带本地振荡器(LO)的产生的60GHz VCO。在操作中，VCO电感器中心抽头电压提供可变电抗器前栅DC偏置。另外，在操作中，可以通过偏置电压(VS)来调整可变电抗器C-V曲线。
图1示出了根据本公开的方面的背栅控制可变电抗器。在实施例中，背栅控制可变电抗器100包括并联设置的两个晶体管N0、N1，其中晶体管N0、N1的前栅分别直接耦合到LC库正(VP)节点和负(VM)节点。在实施例中，晶体管N0、N1是源极/漏极节点短接(电耦合)到节点VS的NMOS完全耗尽SOI(FDSOI)器件或PMOS全耗尽SOI(FDSOI)器件。在操作中，通过设置适当的VS电势，晶体管N0、N1被偏置在亚阈值区域中。
如图1进一步所示，晶体管N0、N1的背栅在VBB节点处被短接(例如，电耦合)在一起。如本领域技术人员应该理解，VBB节点是电压控制节点(例如，VCTRL)。以此方式，晶体管N0、N1通过施加在VBB节点处的电压被背栅控制。在实施例中，背栅控制可变电抗器100展现出由于背栅具有非常高的击穿电压而导致的宽的控制电压范围。例如，VBB电压可以是0V至3.0V或更高，而不受器件可靠性要求的限制。这是与具有约0V至0.8V的电压范围的常规可变电抗器相比较。
通过调整背栅偏置而改变晶体管N0、N1的阈值电压来实现背栅控制可变电抗器100的电容调谐，这产生可变电抗器C-VBB曲线。在本文描述的背栅控制可变电抗器100中，与常规的前栅电压控制的可变电抗器相比，电容对背栅电压VBB较不敏感。这进而允许背栅控制可变电抗器100呈现低增益和更高的范围(与常规的前栅偏置可变电抗器相比)。可变电抗器增益也可以通过使用不同的VS偏置进行调整。
仍然参考图1，晶体管N0、N1的前栅通过施加的DC电压在节点VP/VM处被DC偏置。依赖于VCO类型，例如，NMOS交叉耦合的VCO(图2)或CMOS交叉耦合的VCO(图3)，可变电抗器100的前栅可以被不同地偏置。例如，VDD/2应用于CMOS交叉耦合的VCO(其中PMOS的源极偏置在VDD，VP和VM大约为VDD/2)；而中心抽头(CTAP)电压被施加于NMOS或PMOS仅交叉耦合的VCO(VP＝VM＝VDD)。差分电容(VP到VM)大约是晶体管N0和N1的栅电容的一半。
因此，通过使用背栅控制可变电抗器100，现在可以提供低增益、低噪声、到VCO的直接耦合和宽的控制电压范围。例如，低增益是由于可变电抗器电容对背栅电压较不敏感。低噪声是由于低VCO增益导致电压线噪声受到抑制。因为不需要AC耦合电容器或DC耦合电阻器，可变电抗器可以直接耦合到VCO的LC库。这节省了相当大的面积、降低了寄生电容、扩展了调谐范围以及实现了低噪音。另外，由于背栅具有非常高的击穿电压，背栅控制可变电抗器展现出宽的控制电压范围。
图2示出了根据本发明的方面的直接耦合到背栅控制可变电抗器的VCO。在实施例中，对于更好的相位噪声，低增益可变电抗器，例如，背栅控制可变电抗器100，对毫米波VCO特别重要。另外，到背栅控制可变电抗器100的直接耦合对于毫米波VCO是特别重要的，以便降低寄生电容以实现非常高的频率和宽的调谐范围。在实施例中，背栅控制可变电抗器100可用于不同类型的VCO，例如，NMOS交叉耦合的VCO(图2)或CMOS交叉耦合的VCO(图3)。
更具体地并仍然参考图2，VCO 200直接耦合到背栅控制可变电抗器100，其中VDD是VCO 200的电源电压。在操作中，VDD用于偏置背栅控制可变电抗器100的前栅。更具体地，在偏置背栅控制可变电抗器100的前栅之前，通过电感器210提供供给VCO 200的电压VDD。因此，VCO电感器210(中心抽头)电压向背栅控制可变电抗器100的前栅提供DC偏置。如在此应该理解的，背栅控制可变电抗器100可以直接耦合到VCO 200，而不需要耦合电容器或耦合电阻器。背栅控制可变电抗器100的前栅也直接耦合到节点VP和VM。VCO 200进一步包括与节点VP和VM一致的缓冲器205。也就是，VP/VM是缓冲器输入205处的节点。
图3示出了根据本发明的方面的直接耦合到背栅控制可变电抗器100的CMOS交叉耦合VCO 300。在此实现中，VCO 300直接耦合到背栅控制可变电抗器100，其中VDD是VCO300的电源电压。在操作中，背栅控制可变电抗器100的前栅被偏置在大约VDD/2。
图4示出了根据本公开的方面的包括背栅控制可变电抗器100的模拟的C-V曲线。在图4中，y轴代表56GHz处的电容，以及x轴代表电压VBB。如图3所示，当VS固定在0.4V、VBB在0.8V到1.0V之间扫描时，电容变化1.5fF。此外，C-V斜率为7.5fF/V，注意增益由曲线斜率表示。这是与当VBB固定在0.9V以及VS在0.3V到0.5V之间扫描时具有8.5fF的电容变化和42.5fF/V的C-V斜率的常规MOS可变电抗器相比较。因此，假定将相同尺寸的晶体管用于两个可变电抗器，对于背栅控制可变电抗器100，VCO增益约为常规的MOS可变电抗器的1/5.7。
图4的曲线图进一步示出了VS可以设置到不同的操作点以为系统提供灵活性。另外，通过固定VBB和扫描VS，本文描述的背栅控制可变电抗器100也可以类似于常规MOS可变电抗器来起作用。
图5示出了根据本公开的方面的背栅控制可变电抗器的频率调谐和Kv(增益)曲线。更具体地，图4示出了关于57GHZ VCO的频率调谐和Kv曲线的测量结果。在该图中，y轴表示频率(GHz)和增益(Kv)，而x轴表示电压VBB。虚线表示根据本公开的方面的背栅控制可变电抗器的性能。例如，在0.8V与1.0V之间的电压下，背栅控制可变电抗器示出了由曲线的平坦部分表示的线性增益，例如，约680MHz/V的增益。
本公开的背栅控制可变电抗器可以使用多种不同的工具以多种方式来制造。一般而言，方法和工具被用于形成具有微米和纳米尺寸的结构。已从集成电路(IC)技术中采用了用于制造本公开的背栅控制可变电抗器的方法，即，技术。例如，该结构可以建立在晶片上，并且以通过光刻工艺被图案化的材料膜来实现。特别地，背栅控制可变电抗器的制造使用三个基本构建块：(i)将薄膜材料沉积在衬底上，(ii)通过光刻成像在膜的顶部施加图案化的掩模，以及(iii)选择性地将膜蚀刻到掩模。
如上所述的方法用在集成电路芯片的制造中。所得到的集成电路芯片可以由制造商以作为裸芯片的原始晶片形式(即，作为具有多个未封装芯片的单个晶片)或者以封装形式分发。在后一种情况下，芯片被安装在单芯片封装(诸如塑料载体中，其引线固定到母板或其他更高级别的载体)或多芯片封装(诸如陶瓷载体中，其具有表面互连和/或掩埋互连中的一者或两者)中。在任何情况下，芯片然后与其他芯片、分立电路元件和/或其他信号处理设备集成，作为(a)中间产品(诸如母板)或者(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其他低端应用，到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已为了示例的目的而给出，但并非旨在是穷举性的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的被选择以旨在最好地解释实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能理解本文公开的实施例。

Claims (19)

1.一种可变电抗器，包括：
并联设置的多个晶体管；
耦合到所述多个晶体管的背栅的电压控制节点；以及
耦合到所述多个晶体管的源极和漏极的偏置电压节点，
其中所述多个晶体管的前栅分别直接耦合到电压控制振荡器VCO的电感器/电容器LC库的LC库正(VP)节点和负(VM)节点。
2.根据权利要求1所述的可变电抗器，其中所述多个晶体管包括NMOS完全耗尽SOI(FDSOI)器件或PMOS完全耗尽SOI(FDSOI)器件。
3.根据权利要求2所述的可变电抗器，其中所述多个晶体管的源极/漏极节点通过所述偏置电压节点电耦合在一起。
4.根据权利要求3所述的可变电抗器，其中所述多个晶体管通过所述偏置电压节点被偏置在亚阈值区域。
5.根据权利要求1所述的可变电抗器，其中所述多个晶体管通过施加在所述电压控制节点处的电压被背栅控制。
6.根据权利要求1所述的可变电抗器，其中所述可变电抗器的电容调谐通过调整所述多个晶体管的背栅偏置而改变所述多个晶体管的阈值电压来实现。
7.根据权利要求1所述的可变电抗器，其中所述多个晶体管的所述前栅分别在施加的DC电压的所述LC库正(VP)节点和负(VM)节点处被DC偏置。
8.根据权利要求1所述的可变电抗器，其中VCO电感器中心抽头电压向所述多个晶体管的所述前栅提供DC偏置。
9.根据权利要求8所述的可变电抗器，其中所述VCO的增益通过由耦合到所述多个晶体管的所述源极和漏极的所述偏置电压节点施加的偏置电压来调整。
10.根据权利要求1所述的可变电抗器，其中通过到所述多个晶体管的所述源极和漏极的所述偏置电压节点调整C-V曲线。
11.根据权利要求1所述的可变电抗器，其中所述电压控制振荡器VCO的电压直接耦合到所述多个晶体管的所述背栅。
12.一种可变电抗器，包括：
直接耦合到一对晶体管的背栅以实现栅电容调谐的电压控制节点；以及
直接耦合到所述晶体管的源极和漏极的偏置电压节点，其通过所述偏置电压节点将所述晶体管偏置在亚阈值区域中，
其中所述晶体管通过在所述电压控制节点处施加的电压而被背栅控制，以及
其中所述一对晶体管的前栅分别直接耦合到电压控制振荡器VCO的电感器/电容器LC库的LC库正(VP)节点和负(VM)节点。
13.根据权利要求12所述的可变电抗器，其中所述晶体管的源极/漏极节点通过所述偏置电压节点电耦合在一起。
14.根据权利要求12所述的可变电抗器，其中所述可变电抗器的电容调谐通过调整所述晶体管的背栅偏置而改变所述晶体管的阈值电压来实现。
15.根据权利要求12所述的可变电抗器，其中所述晶体管的所述前栅通过施加的DC电压在所述LC库正(VP)节点和负(VM)节点处被偏置。
16.根据权利要求15所述的可变电抗器，其中所述电压控制振荡器VCO的电压直接耦合到所述晶体管的所述背栅，使得NMOS交叉耦合的VCO电感器中心抽头电压向所述可变电抗器的所述前栅提供DC偏置VDD。
17.根据权利要求15所述的可变电抗器，其中所述VCO的电压直接耦合到所述晶体管的所述背栅，使得CMOS交叉耦合的VCO电源电压向所述可变电抗器的所述前栅提供DC偏置VDD/2。
18.根据权利要求16所述的可变电抗器，其中所述VCO的增益通过由耦合到所述晶体管的所述源极和漏极的所述偏置电压节点施加的偏置电压来调整，以及C-V曲线通过直接耦合到所述晶体管的所述源极和漏极的所述偏置电压节点来调整。
19.一种使用可变电抗器的方法，包括：应用所述可变电抗器的阈值电压对背栅偏置的依赖性以实现栅电容调谐；以及将所述可变电抗器的多个晶体管的前栅分别直接耦合到电压控制振荡器VCO的电感器/电容器LC库的LC库正(VP)节点和负(VM)节点。
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