CN108155291A - A kind of bipolarity large capacity organic field effect tube memory and preparation method - Google Patents
A kind of bipolarity large capacity organic field effect tube memory and preparation method Download PDFInfo
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- CN108155291A CN108155291A CN201711437516.2A CN201711437516A CN108155291A CN 108155291 A CN108155291 A CN 108155291A CN 201711437516 A CN201711437516 A CN 201711437516A CN 108155291 A CN108155291 A CN 108155291A
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
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- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
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- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
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Abstract
The invention discloses a kind of bipolarity large capacity organic field effect tube memory and preparation methods, pass through a series of p-type of band engineering design and N-type organic semiconducting materials, a kind of structure similar to inorganic P N knots is constructed by solution spin coating proceeding, it solves the problems, such as that electron hole is buried in oblivion on same wafer, is stored so as to fulfill the bipolarity information of electron hole.Threshold voltage relatively low simultaneously realizes the stabilization of information storage for the following reduction power consumption when improving integrated level and fever.The present invention is directed to prepare a kind of mixing nano thin-film that site is captured with bipolarity by simple solution spin coating, the storage of large capacity bipolarity is realized.The preparation of film carries out advantageously reducing production cost in the environment of Cryogenic air and prepared by large area.
Description
Technical field
The invention belongs to Semiconductor Organic field-effect transistor memory technology fields, and in particular to be to be had based on p-type
Machine semi-conducting material and N-type organic semiconducting materials by simply adulterate a kind of floating gate type organic field effect tube memory and
Preparation method.
Background technology
The information of magnanimity calculates, storage, transmits and using the feature as 21 century information electronic technology development.In face of big
The arrival of data age, the data processing processing requirement exploitation large capacity of magnanimity, high density, high speed memory, and organic field
Effect transistor memory is compared to traditional inorganic semiconductor memory since it is concerned with natural advantage.Its
Middle organic semiconducting materials low production cost is easy to get, solution processable processing, can be integrated with flexible substrate, and organic effect
Transistorized memory be easy to logic circuit integrate, can the features such as single transistor is realized, nondestructive is read it is practical meet and
Next-generation flexible intelligent wearable electronic industrial expansion direction.
Organic field effect tube (OFET) is to be inserted into a layer charge accumulation layer in control gate insulation layer and semiconductor layer,
Type, ferroelectric type, electret type, floating gate type are currently divided into three categories according to operation principle and device architecture difference.Wherein ferroelectric type
OFET is to realize that information stores by regulating and controlling grid voltage to adjust the polarized state of ferroelectric material.Electret type OFET stores mould
Also there is dispute in formula and mechanism, academia is generally acknowledged that charge under the action of Interface electric field, is deposited charge by tunnel form
Storage is inside the interface or electret of semiconductor layer and electret layer, also or inside semiconductor.Floating gate type OFET pass through by
Metal, inorganic nano-particle or small molecule as charge-trapping center, by the capture and release of electric charge carrier being written and
Information storage is realized in erasing.But most of organic field effect tube memory is all unipolarity storage at present, can only be stored
Hole and can only store electronics.In order to obtain the memory capacity that bipolarity memory improves memory, we devise a system
Row organic small molecule material, by the electron energy band of the controlling changing molecule of the type and the position of substitution of substituent group, so as to obtain
A series of different organic semiconducting materials (p-type and N-type) can store hole but also deposit by simply adulterating final realize
The organic semiconductor memory of storing up electricity.
Organic micromolecule compound has structure determination, and composition is single, and chemical purity is high and structure is easy to the spy regulated and controled
Point, therefore the advantage for having many polymer incomparable in the research and application of material.In the present invention, exactly pass through
The substituent group of different electronic effects (electron and electrophilic) is introduced on an identical structural unit, reaches adjusting electronics
The purpose of energy band, the great advantage of this design are：Since p-type or N-type organic semiconducting materials derive from same class chemical combination
Object differs only in the type of substituent group and the position of substituent group., this control measures are for organic semiconducting materials modularization
It is extremely advantageous with procedure production.
The present invention provides one kind and regulates and controls electron energy band by substituent group, and then obtain different types of semi-conducting material (p-type
Or N-type), with reference to nonpolarity and Hydrophobic insulation polymer material polystyrene (PS) as matrix, prepare a kind of bipolarity
Floating gate type nonvolatile organic field effect tube memory.The memory of the preparation realizes the storage of large capacity bipolarity,
With higher storage data stability.Therefore, memory performance is effectively improved.
Invention content
In view of some technical problems existing for existing organic field effect tube memory, the present invention proposes one kind with polyphenyl
This nonpolar hydrophobic high-k insulative polymer material of ethylene adds in the organic molecule of p-type and N-type as matrix
Material is prepared for the floating gate layer of organic field effect tube memory by solution treatment and spin coating proceeding.Certain p-type with
Under N-type semiconductor material doping ratio, threshold voltage is successfully reduced, reduces power consumption, greatly improves storage performance.It is logical
Crossing this simple doping process realizes the storage of large capacity bipolarity.
The technical solution adopted by the present invention is as follows：
A kind of bipolarity large capacity organic field effect tube memory includes source-drain electrode 5, partly leads successively from top to bottom
Body layer 4, charge storage layer 3, gate insulation layer 2, substrate 1, wherein the charge storage layer 3 is exhausted by hydrophobicity high-k
Edge material polystyrene (PS) is as matrix, and p-type is with N-type semiconductor organic small molecule material as charge-trapping site floating gate layer
Composition；The lower part of the memory further includes the gate electrode being formed on substrate 1, and the memory is using bottom gate
The device architecture of top contact.
The substrate 1 is selected from：Highly doped silicon chip, sheet glass or plastics PET；The material that the gate insulation layer 2 uses
For silica, aluminium oxide, zirconium oxide, polystyrene or polyvinylpyrrolidone；The gate electrode be selected from highly doped silicon, aluminium,
Copper, silver, gold, titanium or tantalum；The FGS floating gate structure is small molecule nanometer floating boom；The material that the semiconductor layer 4 uses is simultaneously
Pentaphene, aphthacene, titan bronze, fluorination titan bronze, red lustrous and transparent alkene, anthracene or 3- hexyl thiophenes；5 material of source-drain electrode is
Ni metal or Au；It is p-type naphthalene cycle compound and N-type naphthalene nucleus that the floating gate layer charge-trapping site, which is organic small molecule material,
Object is closed, the matrix is that hydrophobicity high dielectric constant insulating material is polystyrene.
The floating gate layer charge-trapping site machine small molecule material molecular structure structure is as follows：
P-type organic semiconducting materials molecular structure：The structural unit centered on the naphthalene of 1,2,3,4- tetra- aryl substitution, in virtue
Electron donating group such as-OCH3 is introduced on base or naphthalene nucleus, 3 grade of-CH3 ,-C (CH3) is to put forward high molecular electronics capture ability, example
It is as follows：
N-type molecule organic semiconductor structure：The structural unit centered on the naphthalene of 1,2,3,4- tetra- aryl substitution, in aryl or
Electron withdrawing group such as-CF3 is introduced on naphthalene nucleus, to put forward high molecular hole capture ability, example is as follows by-F ,-Cl etc.：
Described by matrix p-type of polystyrene is to capture site mixing as electric charge capture layer with N-type semiconductor material
It is 1 to close optimum molar ratio example：4.5：4.5, the film thickness of the floating gate layer is 15-40nm.
A kind of preparation method of bipolarity large capacity organic field effect tube memory, includes the following steps：
a：Ease of solubility p-type and N-type small molecule material and hydrophobicity high dielectric of the configuration with excellent charge-trapping ability are normal
Number polymers polystyrene, is dissolved in toluene, three person's concentration is 3mg/ml, using optimal doping ratio matrix polyphenyl second
Alkene, P-type semiconductor, N-type semiconductor 1：4.5：Then 4.5 blending by 80KHz ultrasound 5-10min, stand 5-10min and allow it
It is sufficiently mixed uniformly；
The structure feature of p-type small molecule material described in step a is：Centered on the naphthalene of 1,2,3,4- tetra- aryl substitution
Structural unit introduces electron donating group such as-OCH3 ,-CH3 ,-C (CH3) 3 etc. on aryl or naphthalene nucleus.N-type described in step a
The structure feature of small molecule material is：The structural unit centered on the naphthalene of 1,2,3,4- tetra- aryl substitution, on aryl or naphthalene nucleus
Introduce electron withdrawing group such as-CF3 ,-F ,-Cl etc..
b:Suitable 1 material Silicon Wafer of substrate is selected as substrate, and formation gate electrode and first kind grid are exhausted on substrate
Edge layer, first kind gate insulation layer SiO2It is to be formed by thermal evaporation, thickness 100-300nm dries after cleaning up substrate
It is dry；
c：The clean substrate for drying postcooling is placed in UV ozone and handles 5min；
d：The blend solution that spin-coating step a above substrate in step c has been configured forms a layer charge accumulation layer 3,
The good sample of spin coating is then put into 60 DEG C of drying, thickness 20nm；
e：Dry sample vacuum evaporation semiconductor layer 4 after cooling and source-drain electrode 5 in step d.
The material preparation process of the memory accumulation layer is using a kind of non-polar hydrophobic high dielectric constant polymer
Material polystyrene forms a kind of P-N junction by the way that p-type is similar with N-type semiconductor doping, passes through solution treatment spin coating as matrix
Integral process realizes high quality, uniform film.
The step d spincoating conditions parameters are：3000rps, time 30s, plastics thickness control are spin-coated in 15nm
It is carried out in air and air humidity control is below 50%.
2 thickness of gate insulation layer is 50-300nm；The semiconductor layer 4 using thermal vacuum evaporation film-forming method, into
Film evaporation rate isVacuum degree control is in 5x10-4Pa is hereinafter, crystal oscillator controls thickness in 30nm-50nm；The source
5 evaporation rate of drain electrodeThickness is 40-80nm.
Advantageous effect
(1) OFET memories provided by the present invention, by regarding high dielectric constant polymer material polystyrene as base
Matter, p-type are doped with N-type semiconductor material and prepare a kind of nanometer floating boom similar to P-N junction；Realize large capacity bipolarity
Storage has been provided simultaneously with long maintenance characteristic and good tolerance.
(2) manufacture craft is simplified by tunnel layer-floating gate layer integrated structure, favorably prepares, reduce with large area
Cost advantages are promoted in large-scale commercial applications.
(3) p-type based on band engineering design is formed with N-type semiconductor material by simple doping by spin coating proceeding
Similar inorganic P-N junction avoids burying in oblivion on one piece of wafer electron hole, so as to and realize bipolarity and store.
(4) present invention forms a kind of structure similar to inorganic semiconductor P-N junction by simple solution treatment spin coating, keeps away
The construction process of inorganic semiconductor P-N complexity is exempted from.A kind of thinking is provided for construction organic semiconductor P-N junction.Pass through simultaneously
The doping of P/N types reduces threshold voltage, following as memory integrated level increase is conducive to good reduction power consumption and fever
The unstability of information storage brought.
(5) p-type used in and n type material are all 1,2,3,4- tetra- aryl substitution naphthalene derivatives.It has been more conducive to
The production of machine semi-conducting material modularization and procedure.
Description of the drawings
Fig. 1 is OFET memory device structures schematic diagram of the present invention；
Fig. 2 is that the transfer characteristic of three component floating gate type organic field effect tube memory tests prepared by embodiment 1 is bent
Line；
Fig. 3 is that the output characteristics of three component floating gate type organic field effect tube memory tests prepared by embodiment 1 is bent
Line；
The hole and electricity of Fig. 4,5 for three component floating gate type organic field effect tube memory tests of the preparation of embodiment 1
Sub- memory window indicatrix；
Fig. 6 is the spy that holds time of three component floating gate type organic field effect tube memory tests prepared by embodiment 1
Levy curve；
Fig. 7 is that cycle is wiped in the read-write of three component floating gate type organic field effect tube memory tests prepared by embodiment 1
Indicatrix；
In figure：1- substrates；2- gate insulation layers；3- charge storage layers；4- semiconductor layers；5- source-drain electrodes.
Specific embodiment
In order to become apparent from illustrating technical scheme of the present invention, the present invention is carried out below in conjunction with specific embodiments and the drawings
Detailed description, it is mentioned that attached drawing be only applicable in following embodiments.But protection scope of the present invention be not limited to it is following
Embodiment.
Embodiment 1
The organic field effect tube memory construction schematic diagram that the specific embodiment of the invention is related to is as shown in Figure 1, a kind of P
Type and OFET memory of the N-type semiconductor dopen Nano film as electric charge capture layer include substrate, are formed successively from top to bottom
In the gate electrode of the substrate, the gate insulation layer being covered on gate electrode, the three components doping for being spin-coated on gate insulation layer is organic
Nanometer floating gate layer, the semiconductor layer being formed on floating gate layer and the source and drain for being formed in semiconductor layer upper surface channel region both sides
Electrode.It is using the silicon of N-shaped heavy doping as grid in the technical solution of the embodiment of the present invention；Thermal evaporation 300nm is thick on it
SiO2As gate insulation layer；Electric charge capture layer by polystyrene (PS) as matrix, p-type semiconductor material 5- methoxyl groups 1,2,3,
(4- (trifluoromethyl) phenyl) naphthalenes (TBT-3) of 4- tetraphenyls naphthalene (5-MOT) N-type semiconductor material 1,2,3,4- tetra- using molar ratio as
1：4.5：4.5 are doped to be blended by solution mode and are spun on the gate insulation layer.Its thickness is 20nm.Vacuum evaporation
The pentacene (Pentance) of one layer of 50nm thickness is as semiconductor layer；Then in semiconductor layer conducting channel both sides evaporation metal copper
As source-drain electrode.
When actually preparing, why laboratory is maintained at 25 DEG C or so, and indoor humidity is controlled below 50%.
In the present embodiment as shown in Figure 1：Using the device architecture of bottom gate top contact, the SiO of thermal evaporation 300nm thickness2
As gate insulation layer, mixed solution is then spun on substrate postcooling vapor deposition one semiconductor layer (having no benzene) of annealing, most
One layer of electrode (Au) is deposited afterwards.
As shown in Fig. 2, the device prepared is tested for the property with semi-conductor test instrument in the present embodiment；It is calculated
Threshold voltage is -2.5V, mobility 0.08cm2/ V.s, on-off ratio ION/IOFF are 6.5x104。
The curve of output test that the present embodiment is illustrated in figure 3 device has good transistor field-effect.
Be in the present embodiment be as shown in Figure 4,5 hole and Electronic saving window test, hole memory window reach 70V,
Electronic saving window reaches 35V.Total memory window reaches 105V.
It is as shown in Figure 5,6 the maintenance characteristic of device and tolerance test in the present embodiment, 104On-off ratio maintains after s
103, show good information storage stability.
The specific preparation process of memory described in embodiment is as follows：
(1) by PS, 5-MOT (p-type), TBT-3 (N-type) and using molar ratio as 1：4.5：4.5 ratio blending, is dissolved in toluene
In.A concentration of 3mg/ml of solution；It is sufficiently mixed by the ultrasonication 5-10min of 80KHz the solution being configured
Uniformly.
(2) the N-shaped heavy doping silicon chip of surface growth 300nm thickness is respectively cleaned by ultrasonic successively with acetone, ethyl alcohol, deionized water
10min, supersonic frequency 100kHz, then the drying of substrate surface liquid is ensured into its clean surface with high pure nitrogen, then will
It is put into 120 DEG C of baking oven drying, time 30min.
(3) substrate dried in step (2) is placed on 5min in UV ozone machine.
(4) in air environment, control air humidity is 50% hereinafter, the solution that step (1) has been configured is spin-coated on step
Suddenly the substrate surface that (3) are handled well, spin coating use rotating speed 3000r/min, and spin-coating time 30s, plastics thickness control is on a 20nm left sides
The good substrate of spin coating is placed on 60 DEG C of baking close annealing 15min by the right side.
(5) substrate annealed is placed in vacuum vacuum evaporation system, is evacuated to 6 × 10-5Pa is hereinafter, in the condition
Under withEvaporation rate be deposited one layer of 50nm thickness pentacene as semiconductor layer.
(6) the organic semiconductor layer surface of substrate cooled down in step (5) is subjected to patterned process plus mask plate, protected
Vacuum degree is held 6 × 10-5Pa, withRate one layer of copper is deposited as source-drain electrode, control thickness in 40-60nm；It covers
The channel width of diaphragm plate is 2000 μm, and length is 100 μm.
The present invention is adulterated altogether using using high dielectric constant polymer polystyrene as matrix by p-type and N-type semiconductor
The mode of mixed spin-coating film forms one kind and is similar to inorganic metal-oxide-semiconductor class P-N junction nanometer floating boom organic field effect tube memory,
The storage of large capacity bipolarity is realized, by simple spin coating proceeding, realizes high density storage, multistage storage.It is smaller simultaneously
Threshold voltage is conducive to the unstable of the information storage that reduction power consumption and heating tape when future chips improve integrated level come.Effectively
Small molecule material is promoted to be applied to the research of storage, the business promotion simultaneously for organic field effect tube memory has
Significance.
Above-described embodiment is only the preferred embodiment of the present invention, it should be pointed out that：For the ordinary skill of the art
For personnel, without departing from the principle of the present invention, several improvement and equivalent replacement can also be made, these are to the present invention
Claim be improved with the technical solution after equivalent replacement, each fall within protection scope of the present invention.
Claims (8)
1. a kind of bipolarity large capacity organic field effect tube memory, it is characterised in that：Using the device of bottom gate top contact
Structure includes source-drain electrode (5), semiconductor layer (4), charge storage layer (3), gate insulation layer (2), substrate successively from top to bottom
(1), as site is captured, then the charge storage layer (3) is by polystyrene as matrix p-type and N-type semiconductor material
It is steamed by solvent and the one type inorganic semiconductor P-N junction of construction that occurs to be separated；Lower part, which further includes, to be formed on substrate (1)
Gate electrode.
2. transistorized memory according to claim 1, it is characterised in that：The substrate (1) is selected from：Highly doped silicon
Piece, sheet glass or plastics PET；The material that the gate insulation layer (2) uses is silica, aluminium oxide, zirconium oxide, polyphenyl second
Alkene or polyvinylpyrrolidone；The gate electrode is selected from highly doped silicon, aluminium, copper, silver, gold, titanium or tantalum；The FGS floating gate structure is P
Type and floating boom of the N-type organic semiconducting materials as capture site；The material that the semiconductor layer (4) uses for pentacene,
Aphthacene, titan bronze, fluorination titan bronze, red lustrous and transparent alkene, anthracene or 3- hexyl thiophenes；Described source-drain electrode (5) material is gold
Belong to Cu or Au；The p-type is organic molecule naphthalene cycle compound with N-type organic semiconducting materials；The matrix is non-pole
Property hydrophobicity high-k compound polystyrene.
3. transistorized memory according to claim 1, it is characterised in that：The structure of the p-type and N-type semiconductor material
Formula is as follows：
P-type organic semiconducting materials molecular structure is as follows：
N-type organic semiconducting materials molecular structure is as follows：
4. transistorized memory according to claim 1, it is characterised in that：P-type in the floating boom of the charge storage layer (3)
Optimal doping molar ratio with N-type semiconductor capture site is 1：1, the film thickness is 20-50nm.
5. the preparation method of transistorized memory as claimed in claim 1, which is characterized in that include the following steps：
a：Ease of solubility p-type and N-type organic semiconducting materials and hydrophobicity high dielectric of the configuration with excellent charge-trapping ability are normal
Number polymers polystyrene is dissolved in the toluene solvant without water removal.Optimal concentration is 3mg/ml, will adulterate 10% polyphenyl second
Alkene is blended as matrix and then with p-type and N-type semiconductor organic compound, by 80KHz ultrasound 5-10min, stands 5-
10min allows it to be sufficiently mixed uniformly；
b：Selected substrate is justified for crystal silicon, and formation gate electrode and first kind gate insulation layer (2), first kind grid are exhausted on substrate
Edge layer (2) SiO2It is to be formed by thermal evaporation, thickness 100-300nm, the process for first cleaning up substrate is acetone, second
120 DEG C of baking oven drying 30min postcoolings are placed on after each ultrasound 15min of alcohol, deionized water；
c：The clean substrate for drying postcooling is placed in UV ozone and handles 5min；
d：The blend solution that spin-coating step a above substrate in step c has been configured forms a layer charge accumulation layer (3), with
Afterwards by the good sample of spin coating be put into 60 DEG C drying 15min after natural cooling, thickness 20nm；
e：Dry sample vacuum evaporation semiconductor layer (4) after cooling and source-drain electrode (5) in step d.
6. preparation method as claimed in claim 5, which is characterized in that in step d, the material preparation of memory accumulation layer (3)
Process is to pass through p-type and N-type semiconductor as matrix using non-polar hydrophobic high dielectric constant polymer material polystyrene
Doping is similar to form a kind of P-N junction, is realized by solution treatment floating boom-tunnel layer integration spin coating proceeding.
7. preparation method as claimed in claim 5, which is characterized in that in the step d, spincoating conditions parameter is：
3000rps, time 30s, plastics thickness control 15nm, spin coating carry out in air and air humidity control 50% with
Under.
8. preparation method as claimed in claim 5, which is characterized in that first kind gate insulation layer (2) thickness is 50-
300nm；Using thermal vacuum evaporation film-forming method, the evaporation rate that forms a film is the semiconductor layer 4Vacuum degree control
In 5x10-4Pa is hereinafter, crystal oscillator controls thickness in 30nm-50nm；5 evaporation rate of source-drain electrodeThickness is 40-
80nm。
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| CN109037449B (en) * | 2018-06-25 | 2022-07-26 | 南京邮电大学 | Organic field effect transistor memory and preparation method thereof |
| CN110620177A (en) * | 2019-09-26 | 2019-12-27 | 苏州金宏气体股份有限公司 | Preparation process of organic field effect transistor with carbonyl sulfide as dopant |
| CN110620177B (en) * | 2019-09-26 | 2023-06-23 | 金宏气体股份有限公司 | Preparation process of organic field effect transistor with carbonyl sulfide as dopant |
| CN110964052A (en) * | 2019-12-23 | 2020-04-07 | 苏州和颂生化科技有限公司 | Storage property of organic functional material containing terminal aldehyde group |
| CN110964052B (en) * | 2019-12-23 | 2022-08-05 | 南京和颂材料科技有限公司 | Storage property of organic functional material containing terminal aldehyde group |
| CN113793901A (en) * | 2021-09-16 | 2021-12-14 | 南京大学 | Pentacene organic field effect transistor based on polymer doped N-type organic semiconductor |
| CN113793901B (en) * | 2021-09-16 | 2023-11-07 | 南京大学 | Pentacene organic field effect transistor based on polymer doped N-type organic semiconductor |
| CN114479460A (en) * | 2022-03-21 | 2022-05-13 | 深圳先进电子材料国际创新研究院 | Double-layer polymer composite material and preparation method thereof |
| CN114479460B (en) * | 2022-03-21 | 2024-01-23 | 深圳先进电子材料国际创新研究院 | Double-layer polymer composite material and preparation method thereof |
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Application publication date: 20180612 |