CN108154861A - A kind of top rake voltage generation circuit and liquid crystal display device - Google Patents
A kind of top rake voltage generation circuit and liquid crystal display device Download PDFInfo
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- CN108154861A CN108154861A CN201810070519.5A CN201810070519A CN108154861A CN 108154861 A CN108154861 A CN 108154861A CN 201810070519 A CN201810070519 A CN 201810070519A CN 108154861 A CN108154861 A CN 108154861A
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- switch element
- top rake
- voltage
- switching element
- generation circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
Abstract
The present invention provides a kind of top rake voltage generation circuit, including first switching element, first resistor, second switch element, second resistance, third switch element, 3rd resistor, the 4th switch element and the first capacitance；First control terminal of first switching element receives the first clock signal, and the first path terminal of first switching element, by the first capacity earth, the first path terminal of first switching element is received with reference to high voltage；Wherein, when first switching element is closed, third switch element and the 4th switch element are opened, and the first capacitance is discharged by 3rd resistor so that the voltage value of top rake voltage at this time is less than the voltage value with reference to high voltage.The present invention also provides a kind of liquid crystal display devices, the top rake voltage generation circuit and liquid crystal display device of the present invention, by the voltage value of the top rake voltage of the state of control switch element control output, occur light and dark so as to eliminate between adjacent column sub-pixel, improve display quality.
Description
Technical field
The present invention relates to technical field of liquid crystal display more particularly to a kind of top rake voltage generation circuit, liquid crystal display devices.
Background technology
With the rapid development of display technology, there is liquid crystal display (Liquid Crystal Display, LCD) skill
Art, and its various field that are widely used, such as mobile phone, computer and other various equipment for having display demand, instruments.
By taking thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal display device as an example, including liquid crystal display
Panel and driving circuit, wherein, liquid crystal display panel include array substrate, the color membrane substrates being oppositely arranged with array substrate and
Liquid crystal between array substrate and color membrane substrates is provided with distribution area in array substrate, is used to receiving driving circuit defeated
The drive signal gone out is provided with common electrode area, and close by sealant between color membrane substrates and array substrate on color membrane substrates
Sealing liquid is brilliant.Distribution area in array substrate includes a plurality of gate line and multiple data lines, and adjacent two gate lines with it is adjacent
Two data lines intersect to form a pixel unit, each pixel unit includes at least one TFT.Each pixel respectively by according to
Three sub-pixels of R (red), G (green), B (blue) of secondary arrangement are formed.Driving circuit includes：Gate drivers and source electrode drive
Dynamic device.The basic functional principle of liquid crystal display panel and driving circuit is：Gate drivers are driven by sending out grid to gate line
Dynamic signal sequentially opens the TFT of every a line, then by source electrode driver by data line simultaneously by the pixel unit of a full line
Respectively required voltage is charged to, to change the state of liquid crystal, so as to show different grayscale.
Fig. 1 is the structure diagram of the double grid line style pel array of existing 2 point-polarity inversion mode.Fig. 2 is existing
The structure diagram of 2 point-polarity inversion mode of double grid line style pel array.Fig. 3 a are double grid line style pel array as shown in Figure 2
Driving principle figure.Fig. 3 b are on the first data line D1 and the first data line D2 of double grid line style pel array as shown in Figure 2
Voltage oscillogram.Illustrate existing double grid line style pel array by taking double grid line style pel array as shown in Figure 2 as an example below
Type of drive.Fig. 3 a and Fig. 3 b are please also refer to, due on data line such as the first data line D1
The positive-negative polarity transformation (such as when being transformed to negative polarity by positive polarity or be transformed to positive polarity by negative polarity) of data-signal, the
The data-signal loaded on one data line D1 will appear signal delay phenomenon, so as to cause corresponding sub-pixel undercharge, make
It obtains the brightness of light that corresponding sub-pixel is sent out and is less than the brightness for the light that adjacent sub-pixel is sent out (for example, first row
The brightness for the light that sub-pixel is sent out is less than the brightness of light that secondary series sub-pixel is sent out), therefore, existing double grid line style pixel
The type of drive of array, which exists, to be caused left and right adjacent subpixels charging different due to data-signal postpones and showing for septal line occurs
As.
Invention content
In view of problem above, the present invention provides a kind of top rake voltage generation circuit and liquid crystal display device, can solve existing
Double grid line style pel array type of drive exist cause left and right adjacent subpixels charging difference due to data-signal postpone and
There is picture and show the technical issues of light and dark.
A kind of top rake voltage generation circuit provided by the invention is connected with the input terminal of gate drivers, is cut with output
Angle voltage to the gate drivers, the top rake voltage generation circuit includes first switching element, first resistor, second switch
Element, second resistance, third switch element, 3rd resistor, the 4th switch element and the first capacitance；The first switching element
First control terminal receives the first clock signal, the first path terminal of the first switching element and the input of the gate drivers
End is connected, and the first path terminal of the first switching element is by first capacity earth, the first switching element
Alternate path end is received with reference to high voltage；Second control terminal of the second switch element receives DC voltage, and described second opens
The third path end for closing element refers to high voltage by the way that first resistor reception is described；The third control of the third switch element
End processed receives second clock signal, and the fifth passage end of the third switch element is opened by the second resistance and described second
The third path end for closing element is connected, the 6th path terminal ground connection of the third switch element；The of 4th switch element
Four control terminals are connected with the fourth passage end of the second switch element, the 7th path terminal of the 4th switch element with it is described
First path terminal of first switching element is connected, and the 8th path terminal of the 4th switch element is connect by the 3rd resistor
Ground；Wherein, the voltage value of the DC voltage is more than the voltage value with reference to high voltage, and the first switching element is closed
When, the third switch element and the 4th switch element are opened, and first capacitance is discharged by the 3rd resistor, made
The voltage value for obtaining the top rake voltage at this time is less than the voltage value with reference to high voltage.
In the present embodiment, the first switching element and the 4th switch element are PMOS tube, and described second
Switch element and the third switch element are NMOS tube.
In the present embodiment, the gate drivers are used to export gate drive signal to pair of 1+2 dot inversion modes
Grid line type pel array, when the first switching element is closed, the gate drivers export n-th grade of gate drive signal, with
So that the pixel unit of line n charges, the time that the first switching element is closed is less than or equal to the pixel list of line n
The time of member charging, n is odd number.
In the present embodiment, the gate drivers are used to export gate drive signal to pair of 1+2 dot inversion modes
Grid line type pel array, when the first switching element is closed, the gate drivers export n-th grade of gate drive signal, with
So that the pixel unit of Nth row charges, N is integer；
Wherein, voltage value of the second clock signal when the pixel unit of odd-numbered line is charged is more than in even number line
Voltage value of pixel unit when being charged so that voltage of the top rake voltage when the pixel unit of odd-numbered line is charged
Value is less than the voltage value when the pixel unit of even number line is charged.
In the present embodiment, the gate drivers are used to export gate drive signal to the double grid of 2 dot inversion modes
Line style pel array, when the first switching element is closed, the gate drivers export n-th grade of gate drive signal, so that
The pixel unit for obtaining the (n+1)th row charges, and the time that the first switching element is closed is less than or equal to the pixel of the (n+1)th row
The time of unit charging, n is odd number.
In another embodiment, the top rake voltage generation circuit further includes the 5th switch element, the 5th switch
5th control terminal of element receives third clock signal, the 9th path terminal and the third switch member of the 5th switch element
The fifth passage end of part is connected, the tenth path terminal ground connection of the 5th switch element.
In the present embodiment, the first switching element and the 4th switch element are PMOS tube, and described second
Switch element, the third switch element and the 5th switch element are NMOS tube.
The present invention also provides a kind of liquid crystal display device, the liquid crystal display device includes above-mentioned top rake voltage and generates electricity
Road.
In the present embodiment, the liquid crystal display device further includes gate drivers, and the gate drivers are for defeated
Go out gate drive signal.
The top rake voltage generation circuit and liquid crystal display device of the present invention of the present invention, passes through the state of control switch element
The voltage value of the top rake voltage of output is controlled, so as to which gate drivers be controlled to export the wherein one sub- picture into adjacent column sub-pixel
The voltage value of the gate drive signal of element, to adjust the charging current of the wherein row sub-pixel in adjacent column sub-pixel, so as to
The bright fringes occurred between adjacent column sub-pixel is eliminated, improves display quality.
Description of the drawings
Fig. 1 is the structure diagram of the double grid line style pel array of existing 2 point-polarity inversion mode.
Fig. 2 is the structure diagram of existing 2 point-polarity inversion mode of double grid line style pel array.
Fig. 3 a are the driving principle figure of double grid line style pel array as shown in Figure 2.
Fig. 3 b are the voltage on the first data line D1 and the first data line D2 of double grid line style pel array as shown in Figure 2
Oscillogram.
Fig. 4 is the electrical block diagram of the top rake voltage generation circuit of first embodiment of the invention.
Fig. 5 is the circuit waveform schematic diagram of the top rake voltage generation circuit as shown in Figure 4 of one embodiment of the invention.
Fig. 6 is the enlarged diagram of top rake voltage as shown in Figure 5.
Fig. 7 is the electrical block diagram of the top rake voltage generation circuit of second embodiment of the invention.
Fig. 8 is the circuit waveform schematic diagram of the top rake voltage generation circuit as shown in Figure 7 of one embodiment of the invention.
Fig. 9 is the enlarged diagram of top rake voltage as shown in Figure 8.
Specific embodiment
The technological means and effect taken further to illustrate the present invention to reach predetermined goal of the invention, below in conjunction with
Attached drawing and preferred embodiment, to propose according to the present invention top rake voltage generation circuit, liquid crystal display device its specific embodiment party
Formula, method, step, structure, feature and effect, detailed description are as follows.
For the present invention aforementioned and other technology contents, feature and effect, in following cooperation with reference to the preferable reality of schema
Applying in the detailed description of example to be clearly presented.By the explanation of specific embodiment, when can be predetermined to reach to the present invention
The technological means and effect that purpose is taken be able to more deeply and it is specific understand, however institute's accompanying drawings be only to provide with reference to
Purposes of discussion is not intended to limit the present invention.
Grid top rake voltage generation circuit, liquid crystal display device and implementation of the specific case used herein to the present invention
Mode is expounded, and the explanation of embodiment of above is merely used to help understand the method and its core concept of the present invention；Together
When, for those of ordinary skill in the art, thought according to the present invention has in specific embodiments and applications
Change part, to sum up, the content of the present specification should not be construed as limiting the invention.
Fig. 4 is the electrical block diagram of the top rake voltage generation circuit of first embodiment of the invention.Fig. 5 is the present invention one
The circuit waveform schematic diagram of the top rake voltage generation circuit as shown in Figure 4 of embodiment.Fig. 6 is top rake voltage as shown in Figure 5
Enlarged diagram.It please also refer to Fig. 4, Fig. 5 and Fig. 6, the input terminal of top rake voltage generation circuit 10 and gate drivers 20
It is connected, to export top rake voltage Vgh to gate drivers 20.
In the present embodiment, top rake voltage generation circuit 10 is opened including first switching element M1, first resistor R1, second
Close element M2, second resistance R2, third switch element M3,3rd resistor R3, the 4th switch element M4 and the first capacitance C1.
Specifically, the first control terminal of first switching element M1 receives the first clock signal V1, first switching element M1's
First path terminal is connected with the input terminal of gate drivers 20, and the first path terminal of first switching element M1 passes through the first capacitance
C1 is grounded, and the alternate path end of first switching element M1 is received with reference to high voltage VGH.The second control terminal of second switch element M2
DC voltage V2 is received, the third path end of second switch element M2 is received by first resistor R1 with reference to high voltage VGH.Third
The third control terminal of switch element M3 receives second clock signal V3, and the fifth passage end of third switch element M3 passes through the second electricity
Resistance R2 is connected with the third path end of second switch element M2, the 6th path terminal ground connection of third switch element M3.4th switch
The 4th control terminal of element M4 is connected with the fourth passage end of second switch element M2, the 7th path terminal of the 4th switch element M4
It is connected with the first path terminal of first switching element M1, the 8th path terminal of the 4th switch element M4 is connect by 3rd resistor R3
Ground.Wherein, the voltage value of DC voltage V2 is more than the voltage value with reference to high voltage VGH.
In the present embodiment, first switching element M1 and the 4th switch element M4 is PMOS tube, second switch element
M2 and third switch element M3 is NMOS tube.Specifically, the first control terminal of first switching element M1, second switch element M2
The second control terminal, the third control terminal of third switch element M3 and the 4th control terminal of the 4th switch element M4 be grid,
The first path terminal of first switching element M1, the third path end of second switch element M2, third switch element M3 it is the 5th logical
Terminal and the 8th path terminal of the 4th switch element M4 are drain electrode, and the alternate path end of first switching element M1, second are opened
The 7th path terminal for closing the fourth passage end of element M2, the 6th path terminal of third switch element M3 and the 4th switch element M4 is equal
For source electrode.
In other embodiments, such as first switching element M1, second switch element M2 and the 4th switch element M4
Can be NMOS tube, third switch element M3 is PMOS tube, but the present invention is not limited thereto.In addition, first switching element
At least one in M1, second switch element M2, third switch element M3, the 4th switch element M4 may be other classes
The transistor of type such as triode etc..
It is below PMOS tube with first switching element M1 and the 4th switch element M4, second switch element M2 is opened with third
It is the operation principle that NMOS tube illustrates the top rake voltage generation circuit of the present embodiment to close element M3：
In the starting stage, the first clock signal V1 is low level, therefore first switching element M1 is opened (that is, the
The first path terminal of one switch element M1 is connected with the alternate path end of first switching element M1).Due to the electricity of DC voltage V2
Pressure value is more than the voltage value with reference to high voltage VGH, and therefore, second switch element M2 is in opening state always.Further, since this
It is low level to locate second clock signal V3, and therefore, third switch element M3 is closed (that is, the of third switch element M3
Five path terminals and the 6th path terminal of third switch element M3 are not turned on).Therefore it is opened with reference to high voltage VGH by the first of conducting
It closes element M1 to charge to the first capacitance C1, at this point, the voltage value for the top rake voltage Vgh that top rake voltage generation circuit 10 exports
It is approximately equal to the value with reference to high voltage VGH.
In the top rake stage, the first clock signal V1 becomes high level from low level, therefore first switching element M1 is closed, and
Since second clock signal V3 from low level becomes high level, third switch element M3 is opened, so that the 4th switch
Element M4 is also opened, and the first capacitance C1 is discharged by the 4th switch element M4 and 3rd resistor R3 of conducting, at this time top rake voltage
The top rake voltage Vgh that generation circuit 10 exports is less than the value with reference to high voltage VGH, and the electricity by controlling second clock signal V3
Pressure value can control the electric current for flowing through second resistance R2, therefore can control the voltage of the 4th control terminal of the 4th switch element M4
Size, so as to control the voltage value of the top rake voltage Vgh of output, such as shown in figure 5, second clock signal V3 voltage value
During for the first voltage value V31, the voltage value of top rake voltage Vgh is Vgh1, is the second electricity in the voltage value of second clock signal V3
During pressure value V32, the voltage value of top rake voltage Vgh is Vgh2, wherein, V32 ＞ V31, Vgh2 ＜ Vgh1 ＜ VGH.Therefore, it is of the invention
When first switching element M1 is closed, third switch element M3 and the 4th switch element M4 are opened, and the first capacitance C1 passes through third
Resistance R3 discharges so that the voltage value of top rake voltage Vgh at this time is less than the voltage value with reference to high voltage VGH.
In the present embodiment, gate drivers 20 are used to export gate drive signal to the double grid of 1+2 dot inversion modes
Line style pel array, and during first switching element M1 closings, gate drivers 20 export the gate drive signal of line n, so that
The pixel unit for obtaining line n charges, and n is odd number.Specifically, when gate drivers 20 are used to export gate drive signal extremely
During the double grid line style pel array of 1+2 dot inversion modes, since the data-signal loaded on every data line becomes in positive-negative polarity
It will appear signal delay phenomenon when changing, so big per the brightness of the corresponding sub-pixel of odd-numbered line gate line corresponding on data line
In the brightness of the corresponding sub-pixel of even number line gate line, therefore, when first switching element M1 is closed, due to that can cause the first electricity
Hold C1 to discharge by 3rd resistor R3, so that the voltage value of top rake voltage Vgh at this time is less than the electricity with reference to high voltage VGH
Pressure value realizes top rake, so that the voltage value of the gate drive signal of the corresponding odd-numbered line gate line output of every data line
Less than the voltage value of the gate drive signal of even number line gate line output, therefore so that per corresponding odd-numbered line on data line
The charging current of the corresponding sub-pixel of gate line is less than the charging current of the corresponding sub-pixel of even number line gate line, and then can eliminate
The septal line occurred between adjacent column sub-pixel improves display quality.
In the present embodiment, gate drivers 20 are used to export gate drive signal to the double grid of 1+2 dot inversion modes
During line style pel array, the time t of top rake voltage Vgh top rakes can be equal to the time of line n pixel unit charging, can also be small
In the time of line n pixel unit charging, n is odd number.
In the present embodiment, gate drivers 20 are used to export gate drive signal to the double grid of 1+2 dot inversion modes
During line style pel array, can the gate drive signal of odd-numbered line only be exported so that the picture of odd-numbered line in gate drivers 20
When plain unit is charged, just so that the first capacitance C1 is discharged by 3rd resistor R3, so that top rake voltage Vgh at this time
Voltage value be less than with reference to high voltage VGH voltage value i.e. realize top rake.
In other embodiments, gate drivers 20 are used to export gate drive signal to pair of 1+2 dot inversion modes
During grid line type pel array, the gate drive signal of odd-numbered line and the grid of output even number line can also be exported in gate drivers 20
Pole drive signal, during so that the pixel unit of odd-numbered line and the pixel unit of even number line being charged, so that first switch member
Part M1 is closed, so that the first capacitance C1 carries out top rake by 3rd resistor R3 electric discharges to top rake voltage Vgh, and is passed through
Voltage value of the voltage value of second clock signal V3 when the pixel unit of odd-numbered line is charged is controlled to be more than in even number line
Voltage value when pixel unit is charged, so that electricity of the top rake voltage Vgh when the pixel unit of odd-numbered line is charged
Pressure value is less than the voltage value when the pixel unit of even number line is charged.Specifically, such as shown in figure 5, pass through control the
Voltage value of the voltage value of two clock signal V3 when the pixel unit of odd-numbered line is charged is V32, in the pixel of even number line
Voltage value when unit is charged is V31 so that exports the gate drive signal of odd-numbered line in gate drivers 20 with to strange
The voltage value of top rake voltage Vgh is adjusted to Vgh2 when several rows of pixel unit is charged, and is exported in gate drivers 20
When the gate drive signal of even number line is charged with the pixel unit of several rows of antithesis, the voltage value of top rake voltage Vgh is adjusted
For Vgh1, wherein, V32 ＞ V31, Vgh2 ＜ Vgh1 ＜ VGH, so that corresponding odd-numbered line gate line pair on per data line
The charging current for the sub-pixel answered is less than the charging current of the corresponding sub-pixel of even number line gate line, and then can eliminate adjacent column
The septal line occurred between pixel improves display quality.Wherein, the time for time, that is, top rake that first switching element M1 is closed can be with
But it is not limited to be equal with the time of the pixel unit of odd-numbered line and the charging of the pixel unit of even number line, might be less that odd-numbered line
Pixel unit charging time and/or even number line pixel unit charging time.
In the present embodiment, gate drivers 20 are used to export gate drive signal to the double grid line of 2 dot inversion modes
During type pel array, when first switching element M1 is closed, gate drivers 20 export the gate drive signal of even number line, so that
The pixel unit of (n+1)th row charges, and the time that first switching element M1 is closed is less than or equal to the pixel unit of the (n+1)th row
The time of charging, n are odd number, eliminate the principle of the septal line occurred between adjacent column sub-pixel and pair of 1+2 dot inversion modes
The principle of grid line type pel array is similar, and details are not described herein.
In other embodiments, gate drivers 20 are used to export gate drive signal to the double grid of 2 dot inversion modes
During line style pel array, the gate drive signal of odd-numbered line and the grid of output even number line can also be exported in gate drivers 20
Drive signal, during so that the pixel unit of odd-numbered line and the pixel unit of even number line being charged, so that first switching element
M1 is closed, so that the first capacitance C1 is discharged by 3rd resistor R3, and by controlling the voltage value of second clock signal V3
Voltage value when the pixel unit of even number line is charged is more than the voltage value when the pixel unit of odd-numbered line is charged,
So that voltage values of the top rake voltage Vgh when the pixel unit of even number line is charged be less than odd-numbered line pixel unit into
Voltage value during row charging, so that the charging current per the corresponding sub-pixel of even number line gate line corresponding on data line
The charging current of sub-pixel corresponding less than odd-numbered line gate line, and then the septal line occurred between adjacent column sub-pixel can be eliminated,
Improve display quality.
Fig. 7 is the electrical block diagram of the top rake voltage generation circuit of second embodiment of the invention.Fig. 8 is the present invention one
The circuit waveform schematic diagram of the top rake voltage generation circuit as shown in Figure 7 of embodiment.Fig. 9 is top rake voltage as shown in Figure 8
Enlarged diagram.The structure of the top rake voltage generation circuit 11 of the present embodiment and the top rake voltage generation circuit of first embodiment
Essentially identical, the difference lies in top rake voltage generation circuit further includes the 5th switch element M5.The of 5th switch element M5
Five control terminals receive third clock signal V4, and the 9th path terminal of the 5th switch element M5 is logical with the 5th of third switch element M3 the
Terminal is connected, the tenth path terminal ground connection of the 5th switch element M5.
In the present embodiment, the 5th switch element M5 can be NMOS tube, but the present invention is not limited thereto.
It is below PMOS tube with first switching element M1 and the 4th switch element M4, second switch element M2, third are opened
It is NMOS tube to close element M3, the 5th switch element M5, illustrates the operation principle of the top rake voltage generation circuit of the present embodiment：
In the starting stage, the first clock signal V1 is low level, therefore first switching element M1 is opened (that is, the
The first logical short end of one switch element M1 is connected with the alternate path end of first switching element M1).Due to the electricity of DC voltage V2
Pressure value is more than the voltage value with reference to high voltage VGH, and therefore, second switch element M2 is in opening state always.Further, since this
It is low level to locate second clock signal V3 and second clock signal V4, therefore, third switch element M3, the 4th switch element M4
It is turned off.Therefore charged with reference to high voltage VGH by the first switching element M1 of conducting to the first capacitance C1, at this point, top rake
The voltage value for the top rake voltage Vgh that voltage generation circuit 10 exports is approximately equal to the value with reference to high voltage VGH.
In the top rake stage, the first clock signal V1 becomes high level from low level, therefore first switching element M1 is closed, and
When second clock signal V3 becomes high level from low level and voltage value is Vgh, and third switch element M3 is opened, so that
4th switch element M4 is also opened, and the first capacitance C1 is discharged by the 4th switch element M4 and 3rd resistor R3 of conducting, at this time
The top rake voltage Vgh that top rake voltage generation circuit 10 exports is less than the value with reference to high voltage VGH, and by the way that second clock is controlled to believe
The voltage value of number V3 can control the electric current for flowing through second resistance R2, therefore the 4th of the 4th switch element M4 can be controlled to control
The voltage swing at end, so as to control the voltage value of the top rake voltage Vgh of output, such as shown in figure 8, control second clock signal
Voltage value when V3 is high level is Vgh1 so as to control the voltage value of the top rake voltage Vgh of output；As third clock signal V4
When becoming high level from low level, the 5th switch element M5 is opened, so that the 4th switch element M4 is also opened, the first capacitance
C1 is discharged by the 4th switch element M4 and 3rd resistor R3 of conducting, the top rake electricity that top rake voltage generation circuit 10 exports at this time
Vgh is pressed to be less than the value with reference to high voltage VGH, and the second electricity is flowed through by controlling the voltage value of third clock signal V4 that can control
The electric current of R2 is hindered, therefore the voltage swing of the 4th control terminal of the 4th switch element M4 can be controlled, so as to control cutting for output
The voltage value of angle voltage Vgh, such as shown in figure 8, voltage value when control third clock signal V4 is high level is more than second
Voltage value when clock signal V3 is high level so that the voltage value of top rake voltage Vgh exported at this time is Vgh2, wherein,
Vgh2 ＜ Vgh1.
Since the present embodiment can be by controlling the voltage value control of second clock signal V3 and third clock signal V4 respectively
Make the voltage value of the top rake voltage Vgh of output, so that the top rake voltage generation circuit of the present embodiment exports a variety of top rake electricity
Pressure adapts to the double grid line style pel array of a variety of such as 2 dot inversion modes or 1+2 dot inversion modes, to eliminate adjacent column
The septal line occurred between pixel, flexibility are high.
The present invention also provides a kind of liquid crystal display devices using above-mentioned top rake voltage generation circuit.
The top rake voltage generation circuit and liquid crystal display device of invention are exported by the state control of control switch element
The voltage value of top rake voltage is adjacent so as to eliminate to adjust the charging current of the wherein row sub-pixel in adjacent column sub-pixel
The septal line occurred between row sub-pixel improves display quality.
Claims (9)
- A kind of 1. top rake voltage generation circuit, which is characterized in that the input of the top rake voltage generation circuit and gate drivers End is connected, and to export top rake voltage to the gate drivers, the top rake voltage generation circuit includes first switching element, the One resistance, second switch element, second resistance, third switch element, 3rd resistor, the 4th switch element and the first capacitance；First control terminal of the first switching element receives the first clock signal, the first path terminal of the first switching element It is connected with the input terminal of the gate drivers, and the first path terminal of the first switching element is connect by first capacitance Ground, the alternate path end of the first switching element are received with reference to high voltage；Second control terminal of the second switch element receives DC voltage, and the third path end of the second switch element passes through The first resistor receives described with reference to high voltage；The third control terminal of the third switch element receives second clock signal, the fifth passage end of the third switch element It is connected by the second resistance with the third path end of the second switch element, the 6th access of the third switch element End ground connection；4th control terminal of the 4th switch element is connected with the fourth passage end of the second switch element, and the described 4th opens The 7th path terminal for closing element is connected with the first path terminal of the first switching element, and the 8th of the 4th switch element is logical Terminal is grounded by the 3rd resistor；Wherein, the voltage value of the DC voltage is more than the voltage value with reference to high voltage, and the first switching element is closed When, the third switch element and the 4th switch element are opened, and first capacitance is discharged by the 3rd resistor, made The voltage value for obtaining the top rake voltage at this time is less than the voltage value with reference to high voltage.
- 2. top rake voltage generation circuit as described in claim 1, which is characterized in that the first switching element and the described 4th Switch element is PMOS tube, and the second switch element and the third switch element are NMOS tube.
- 3. top rake voltage generation circuit as described in claim 1, which is characterized in that the gate drivers are used to export grid Drive signal to 1+2 dot inversion modes double grid line style pel array, when the first switching element is closed, the gate driving Device exports n-th grade of gate drive signal, so that the pixel unit of line n charges, what the first switching element was closed Time is less than or equal to the time that the pixel unit of line n charges, and n is odd number.
- 4. top rake voltage generation circuit as described in claim 1, which is characterized in that the gate drivers are used to export grid Drive signal to 1+2 dot inversion modes double grid line style pel array, when the first switching element is closed, the gate driving Device exports N grades of gate drive signals, so that the pixel unit of Nth row charges, N is integer；Wherein, voltage value of the second clock signal when the pixel unit of odd-numbered line is charged is more than the picture in even number line Voltage value when plain unit is charged, so that voltage of the top rake voltage when the pixel unit of odd-numbered line is charged Value is less than the voltage value when the pixel unit of even number line is charged.
- 5. top rake voltage generation circuit as described in claim 1, which is characterized in that the gate drivers are used to export grid Drive signal to 2 dot inversion modes double grid line style pel array, when the first switching element is closed, the gate drivers N-th grade of gate drive signal is exported, so that the pixel unit of the (n+1)th row charges, what the first switching element was closed Time is less than or equal to the time that the pixel unit of the (n+1)th row charges, and n is even number.
- 6. top rake voltage generation circuit as described in claim 1, which is characterized in that the top rake voltage generation circuit further includes 5th switch element, the 5th control terminal of the 5th switch element receive third clock signal, the 5th switch element 9th path terminal is connected with the fifth passage end of the third switch element, the tenth access termination of the 5th switch element Ground.
- 7. top rake voltage generation circuit as described in claim 1, which is characterized in that the first switching element and the described 4th Switch element is PMOS tube, and the second switch element, the third switch element and the 5th switch element are NMOS tube.
- 8. a kind of liquid crystal display device, which is characterized in that the liquid crystal display device includes such as claim 1-7 any one The top rake voltage generation circuit.
- 9. liquid crystal display device as claimed in claim 8, which is characterized in that the liquid crystal display device further includes gate driving Device, the gate drivers are used to export gate drive signal.
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| CN108154861B (en) | 2020-10-30 |
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