CN108153485B - Method and system for multi-device cooperative access to SRAM - Google Patents

Abstract

The invention provides a method and a system for cooperatively accessing an SRAM by multiple devices, which belong to the technical field of integrated circuits. When a plurality of devices need to access the SRAM, one of the devices is taken as a master device, the other devices are taken as slave devices, the slave devices acquire the current SRAM state through interaction information between the slave devices and the master device, SRAM read-write signals sent by the slave devices are controlled by the master device, and the master device determines which device performs read-write operation on the SRAM according to the current SRAM state and the priority of each device. The method provides a practical and effective method for a system with multiple devices accessing the SRAM with higher real-time performance, the two-time handshake mechanism is simple to realize, the reliable and effective operation of reading and writing the SRAM can be ensured, and the method has no special requirements on the reading and writing time, the reading and writing period and the like of the SRAM and has stronger universality.

Description

Method and system for multi-device cooperative access to SRAM

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a reliable method for accessing an SRAM (static random access memory) by multiple devices in a coordinated mode.

Background

Data storage, which is a critical part of digital circuitry, plays an important role in data caching. The common SRAM in data storage becomes the mainstream memory at present due to its advantages of no need of refresh circuit, simple read-write interface timing sequence, and the like, and is widely applied to embedded systems. In a digital circuit system, a plurality of devices often need to access the same SRAM, and since the SRAM can be accessed by only one device at the same time, a method for realizing that the plurality of devices access the SRAM alternately is needed. The traditional method is usually realized by software time sharing access or hardware time sharing access. Most of the existing software time-sharing access methods cannot ensure the real-time performance of reading and writing the SRAM; the hardware time-sharing access method is usually to design and select a circuit, so that the area and the cost of the circuit are increased, and the market competitiveness of the product is reduced. In order to save cost and ensure the reliability of products, a reliable method for cooperatively accessing the SRAM by multiple devices is provided. The method has simple hardware and small software overhead, and practices prove that the method is effective and reliable in SRAM access.

Disclosure of Invention

The purpose of the invention is as follows: the method is based on the software coordination idea, does not increase hardware overhead, and reliably realizes the multi-device cooperative access to the SRAM.

In order to achieve the above purposes, the technical scheme adopted by the invention is as follows: when a plurality of devices need to access the SRAM, one of the devices is taken as a master device, the other devices are taken as slave devices, the slave devices acquire the current SRAM state through interaction information between the slave devices and the master device, SRAM read-write signals sent by the slave devices are controlled by the master device, and the master device determines which device performs read-write operation on the SRAM according to the current SRAM state.

A method for multiple devices to cooperatively access an SRAM, the method comprising:

s1, when multiple devices need to access SRAM, one of the devices is taken as a main device, and the other devices are taken as auxiliary devices;

s2, directly connecting the master device with the SRAM, connecting the slave device with the master device, and realizing the access of the slave device to the SRAM by the transfer of the master device;

s3, the main device is responsible for monitoring and recording the current state of the SRAM, when a plurality of devices access the SRAM at the same time, the main device determines which device accesses the SRAM according to the current state and the priority of each device;

s4, when the higher priority device accesses SRAM, no matter what state the current SRAM is in, it doesn't wait to give SRAM operation right to the device with highest priority;

s5, when the low priority device accesses the SRAM, firstly judging the current state of the SRAM to determine whether the current read or write can be started, after the read or write of the SRAM, judging whether the current read or write is successful, wherein the successful sign is to judge whether other devices perform read or write operation on the SRAM during the current operation; if the judgment result is that the reading or writing fails, the reading or writing needs to be carried out again until the success is achieved;

a system for multiple devices to cooperatively access SRAM, comprising: MCU, FPGA, SRAM; the FPGA is used as a master device, and the MCU is used as a slave device; the FPGA is directly connected with the SRAM, the MCU is connected with the FPGA, and the operation of the MCU on the SRAM is realized by the transfer of the FPGA;

(1) the FPGA controls two flags: one is the current state of the SRAM, and the other is the reading and writing mark of the SRAM; the current state of the SRAM is defaulted to be an idle state, when equipment reads or writes the SRAM, the FPGA needs to set the current state of the SRAM to be a read state or a write state, and after the read or write operation is completed, the current state of the SRAM is restored to be the idle state; the reading and writing mark is defaulted to be in an idle state, when equipment reads or writes the SRAM, the FPGA needs to set the reading and writing mark to be in a reading and writing state, and when the FPGA finishes one-time reading or writing operation of the SRAM and reads the reading and writing mark, the reading and writing mark is restored to be in the idle state;

(2) the priority of the MCU for accessing the SRAM is higher than that of the FPGA;

before reading or writing the SRAM by the FPGA with lower priority, the FPGA needs to judge the current state of the SRAM, if the current state of the SRAM is an idle state, the FPGA can read or write the SRAM, after reading or writing the SRAM, a reading or writing mark register needs to be inquired to judge whether the reading or writing is successful, if the reading or writing mark register is in a reading or writing state, the reading or writing operation is proved to be failed, and if the reading or writing mark register is in an idle state, the reading or writing operation is proved to be successful; if the judgment result is that the reading or writing fails, the reading or writing needs to be carried out again until the success is achieved; when the MCU with higher priority reads or writes the SRAM, the FPGA connects the SRAM with the MCU without waiting control, thereby ensuring that the MCU accesses the SRAM in real time.

A system for multiple devices to cooperatively access SRAM, comprising: MCU, FPGA, SRAM; the FPGA is used as a master device, and the MCU is used as a slave device; the FPGA is directly connected with the SRAM, the MCU is connected with the FPGA, and the operation of the MCU on the SRAM is realized by the transfer of the FPGA;

(1) the FPGA controls two flags: one is the current state of the SRAM, and the other is the reading and writing mark of the SRAM; the current state of the SRAM is defaulted to be an idle state, when equipment reads or writes the SRAM, the FPGA needs to set the current state of the SRAM to be a read state or a write state, and after the read or write operation is completed, the current state of the SRAM is restored to be the idle state; the reading and writing mark is defaulted to be in an idle state, when equipment reads or writes the SRAM, the FPGA needs to set the reading and writing mark to be in a reading and writing state, and when the FPGA finishes one-time reading or writing operation of the SRAM and reads the reading and writing mark, the reading and writing mark is restored to be in the idle state;

(2) the priority of the FPGA accessing the SRAM is higher than that of the MCU; when the MCU with lower priority reads or writes the SRAM, the MCU judges the current state of the SRAM first, if the current state of the SRAM is an idle state, the MCU reads or writes the SRAM, queries a read-write mark after reading or writing the SRAM to judge whether the reading or writing is successful, if the read-write mark is the read-write state, the reading or writing operation is proved to be failed, and if the read-write mark is the idle state, the reading or writing operation is proved to be successful; if the judgment result is that the reading or writing fails, the reading or writing needs to be carried out again until the success is achieved; when the FPGA with higher priority reads or writes the SRAM, the FPGA does not wait for reading or writing.

Preferably, the system for accessing the SRAM in cooperation with multiple devices is characterized by further comprising an RS422 interface circuit, a data transmission interface circuit, and an upper computer provided with a data acquisition device; the SRAM is connected with the input/output port of the FPGA; the MCU is provided with an external EPI interface, the EPI interface is connected with other input and output ports of the FPGA, and the EPI interface can be configured to access the FPGA and the SRAM in a time-sharing mode; the RS422 interface circuit receives the serial port command of the upper computer and transmits the serial port command to the FPGA; the data transmission interface circuit realizes the transmission of SRAM data; the upper computer is used for sending serial port commands and collecting and analyzing SRAM data; the FPGA can receive serial port commands and control the EPI interface to access the FPGA and the SRAM in a time-sharing manner.

Preferably, the system for accessing the SRAM in cooperation with multiple devices is characterized by comprising: the FPGA can realize the SRAM read-write control function, the data sending function and the SRAM state control function.

Preferably, the system for multiple devices to access the SRAM in cooperation is characterized in that the MCU is TI, and the system for multiple devices to access the SRAM in cooperation is characterized in that the MCU has an external EPI interface and can implement an 8, 16, or 32-bit parallel bus interface.

A system for multiple devices to cooperatively access SRAM, comprising: MCU, FPGA, SRAM; the FPGA is used as a master device, and the MCU is used as a slave device; the FPGA is directly connected with the SRAM, the MCU is connected with the FPGA, and the operation of the MCU on the SRAM is realized by the transfer of the FPGA; the priority of the FPGA accessing the SRAM is higher than that of the MCU; the specific access method is as follows:

(1) read SRAM command: the upper computer sends an SRAM reading command, and the FPGA receives and analyzes the command through the serial port;

(2) reading SRAM data: after receiving the SRAM reading command, the FPGA generates an SRAM reading signal, an SRAM chip selection signal and an SRAM writing prohibition enabling signal without waiting, and sends data read out from the SRAM to an upper computer;

(3) SRAM state control: the FPGA controls two registers to mark the state of the SRAM: the current state register of the SRAM and the read-write marking register of the SRAM are respectively used for being read by the MCU; the default state of the current state register is an idle state, when SRAM reading operation is started, the current state register is set to be a read state, the current state register is restored to be the idle state after the reading operation is finished, when the SRAM writing operation is started, the current state register is set to be a write state, the current state register is restored to be the idle state after the writing operation is finished, the read-write marking register is defaulted to be the idle state, and when the SRAM reading operation is started, the read-write marking register is set to be a read-write state;

(4) writing SRAM data: the FPGA controls interaction between an EPI interface of the MCU and the FPGA, before writing the SRAM, the MCU firstly inquires a current state register of the SRAM, when the SRAM is in an idle state, the MCU initiates SRAM writing operation through the EPI interface, the FPGA judges the current state of the SRAM, and if the current state is in the idle state, the FPGA sends the following signals to the SRAM: writing SRAM signals, SRAM chip selection signals and SRAM data signals by the MCU, or else, not sending the signals by the FPGA; after the MCU completes the SRAM writing operation, the MCU queries the SRAM reading and writing mark register, if the reading and writing mark register is in a reading and writing state, the reading and writing SRAM command is received during the SRAM writing period, the SRAM writing is forced to be interrupted, the SRAM writing operation fails, at the moment, the MCU sends a command to set the SRAM reading and writing mark register to be in an idle state, the FPGA sets the reading and writing mark register to be in an idle state after receiving the command, and meanwhile, the MCU writes the data into the SRAM again until the writing is successful.

Compared with the prior art, the method has the beneficial effects that:

(1) the reliability is strong, based on the idea of software coordination, the reliable reading and writing of the SRAM are ensured by adopting a two-time handshake mechanism, the hardware overhead is reduced, the cost is saved, and the reliability of the system is improved;

(2) the method has good universality, has no special requirements on the specific time of reading and writing the SRAM, the reading and writing period and the like, and has strong adaptability;

(3) the real-time performance is high, and equipment with high priority can access the SRAM without waiting.

Drawings

FIG. 1 is a multi-device cooperative access SRAM system configuration of the present invention.

Fig. 2 is a system data flow diagram in the second embodiment of the present invention.

FIG. 3 is a flow chart of SRAM read/write according to a second embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

When a plurality of devices need to access the SRAM, one of the devices is taken as a master device, the other devices are taken as slave devices, the slave devices acquire the current SRAM state through interaction information between the slave devices and the master device, SRAM read-write signals sent by the slave devices are controlled by the master device, and the master device determines which device performs read-write operation on the SRAM according to the current SRAM state and the priority of each device.

A reliable system for multiple device cooperative access to SRAM, comprising the following definitions:

(1) when a system with multiple devices accessing SRAM in a coordinated mode is designed, the main device is directly connected with the SRAM, the slave device is connected with the main device, and the access of the slave device to the SRAM is finally realized through the transfer of the main device.

(2) The main equipment is responsible for monitoring and recording the current state of the SRAM; when a plurality of devices access the SRAM simultaneously, the main device determines which device accesses the SRAM according to the current state and the priority of each device;

(3) when the equipment with higher priority accesses the SRAM, no matter what state the current SRAM is in, the SRAM operation right is handed to the equipment with the highest priority;

(4) the read/write operation of the SRAM by the lower priority device may be interrupted by the higher priority device, so a mechanism needs to be established to ensure reliable read/write of the SRAM. The method is realized by adopting a two-time handshake mechanism, when low-priority equipment needs to inquire the current state of an SRAM before reading/writing the SRAM to determine whether the reading/writing can be started (if the current state of the SRAM is in an idle state, the reading/writing operation can be started, otherwise, the reading/writing operation cannot be started), whether the reading/writing of the reading/writing (inquiring a reading/writing mark register) is successful needs to be judged after the SRAM is read/written, a mark of whether the reading/writing is successful is to judge whether other equipment successfully acquires the control right of the SRAM and carries out the reading/writing operation during the current operation period (if the reading/writing mark register is in a reading/writing state, the reading/writing operation is proved to be failed, and if the reading/writing mark register is in an idle state, the reading/writing operation is proved to be successful). And if the judgment result is that the reading/writing fails, the reading/writing needs to be carried out again until the success is achieved.

The first embodiment is as follows: the invention relates to a multi-device cooperative access SRAM system, which specifically comprises: MCU, FPGA, SRAM. Both the MCU and the FPGA need to access the SRAM, and in the embodiment, the priority of the MCU to access the SRAM is higher than that of the FPGA. The FPGA is directly connected with the SRAM, the MCU is connected with the FPGA, and the operation of the MCU on the SRAM is realized by the transfer of the FPGA. The specific steps of the MCU and the FPGA cooperatively accessing the SRAM are as follows:

(3) the FPGA is responsible for managing two registers, one is an SRAM current state register, and the other is a read/write flag register. The SRAM current state register is in an idle state by default, when equipment reads/writes the SRAM, the FPGA needs to set the SRAM current state register in a read state or a write state, and after the read/write operation is completed, the SRAM current state register is restored to the idle state. The read/write marking register defaults to an idle state, when equipment reads/writes the SRAM, the FPGA needs to set the read/write marking register to be in a read state or a write state, and when the FPGA completes one-time read/write SRAM operation and reads the read/write marking register, the read/write marking register is restored to the idle state.

(4) Before reading or writing the SRAM by the FPGA with lower priority, the FPGA needs to judge the current state of the SRAM, if the current state of the SRAM is an idle state, the FPGA can read or write the SRAM, after reading or writing the SRAM, a reading or writing mark register needs to be inquired to judge whether the reading or writing is successful, if the reading or writing mark register is in a reading or writing state, the reading or writing operation is proved to be failed, and if the reading or writing mark register is in an idle state, the reading or writing operation is proved to be successful. And if the judgment result is that the reading/writing fails, the reading or the writing needs to be carried out again until the success is achieved.

(5) When the MCU with higher priority reads/writes the SRAM, the FPGA needs to connect the SRAM with the MCU without waiting, and the MCU can access the SRAM in real time.

In a second embodiment, the present invention provides a multi-device cooperative access SRAM system, which specifically includes: MCU, FPGA, SRAM. The FPGA is used as a master device, and the MCU is used as a slave device; both the MCU and the FPGA need to access the SRAM, and in the embodiment, the priority of the FPGA to access the SRAM is higher than that of the MCU. The FPGA is directly connected with the SRAM, the MCU is connected with the FPGA, and the operation of the MCU on the SRAM is realized by the transfer of the FPGA. The specific steps of the MCU and the FPGA cooperatively accessing the SRAM are as follows:

(3) the FPGA controls two flags: one is the current state of the SRAM, and the other is the reading and writing mark of the SRAM; the current state of the SRAM is defaulted to be an idle state, when equipment reads or writes the SRAM, the FPGA needs to set the current state of the SRAM to be a read state or a write state, and after the read or write operation is completed, the current state of the SRAM is restored to be the idle state; the reading and writing mark is defaulted to be in an idle state, when equipment reads or writes the SRAM, the FPGA needs to set the reading and writing mark to be in a reading state or a writing state, and when the FPGA finishes one-time reading or writing operation of the SRAM and reads the reading and writing mark, the reading and writing mark is restored to be in the idle state;

(2) when the priority of the FPGA for accessing the SRAM is higher than that of the MCU; when the MCU with lower priority reads or writes the SRAM, the MCU judges the current state of the SRAM first, if the current state of the SRAM is an idle state, the MCU reads or writes the SRAM, queries a read-write mark after reading or writing the SRAM to judge whether the reading or writing is successful, if the read-write mark is the read-write state, the reading or writing operation is proved to be failed, and if the read-write mark is the idle state, the reading or writing operation is proved to be successful; if the judgment result is that the reading or writing fails, the reading or writing needs to be carried out again until the success is achieved;

(3) when the FPGA with higher priority reads or writes the SRAM, the FPGA does not wait for reading or writing;

in short, when the priority of the master device is lower than that of the slave device, the slave device initiates a read or write operation on the SRAM, and then the master device connects the slave device with the SRAM.

Example three: as shown in fig. 1, a system for reliable multi-device cooperative access to an SRAM according to the present invention includes: the system comprises an SRAM read-write device consisting of an MCU, an FPGA and an SRAM, an RS422 interface circuit, a data transmitting interface circuit and an upper computer provided with a data acquisition device. In the SRAM read-write device, both the MCU and the FPGA need to access the SRAM, the FPGA is directly connected with the SRAM, the MCU is connected with the FPGA, and the MCU is used for realizing the operation of the SRAM through the switching of the FPGA. The MCU needs to write data into the SRAM, the priority of the FPGA for accessing the SRAM is higher than that of the MCU in the embodiment, and the FPGA needs not to wait for reading the data in the SRAM after receiving the SRAM reading command.

In the SRAM read-write device, MCU is realized by TM4C1294 of TI company, the processor is provided with an external interface (EPI) which can realize 8/16/32 bit parallel bus interface, the EPI interface is connected with FPGA IO, the EPI interface has a plurality of working modes, and FPGA and SRAM can be accessed in time-sharing mode by configuring corresponding modes through software;

the FPGA is used as a main device and needs to realize a serial port command receiving function, an SRAM read-write control function, a data sending function, an SRAM state control function and an EPI interface control function, the FPGA selects XC6SLX45 which is a Spartan6 series chip of Xilinx company, and the FPGA can provide enough hardware resources such as logic gate number, IO pins, RAM and the like for users to use;

the SRAM selects CY7C1061, the capacity of which is 2MB and the data width of which is 16bits from CYPRESS company;

the RS422 interface circuit realizes the receiving of the upper computer serial port command;

the data transmission interface circuit realizes the transmission of SRAM data;

the upper computer is used for sending serial port commands and collecting and analyzing SRAM data.

As shown in fig. 2, a reliable method for accessing an SRAM cooperatively by multiple devices includes a data flow diagram including four data paths, where each data path data flow is as follows:

(5) the upper computer sends an SRAM reading command, the FPGA receives and analyzes the command through the serial port command receiving module, and then the read command is transmitted to the SRAM read-write control module;

(6) the SRAM read-write control module does not wait for generating an SRAM read signal/RD, an SRAM chip selection signal/CS, an SRAM byte enable signal/BLE and/BHE and an SRAM address signal ADDR after the FPGA receives an SRAM read command, simultaneously forbids an SRAM write enable signal/WE, connects the signals to the SRAM, and sends data read from the SRAM to an upper computer data acquisition device through a data sending module;

(7) an SRAM state control access, which generates two register FLAG SRAM states through an SRAM state control module for MCU reading, wherein the two register FLAG SRAM states are respectively an SRAM current state register SRAM _ STA and an SRAM READ-write FLAG register READ _ FLAG, the default state of the current state register SRAM _ STA is an idle state, when SRAM reading operation is started, the current state register SRAM _ STA is set to be a READ state, when the SRAM reading operation is ended, the current state register SRAM _ STA is restored to be the idle state, when SRAM writing operation is started, the current state register SRAM _ STA is set to be a write state, when the SRAM writing operation is ended, the current state register SRAM _ STA is restored to be the idle state, the READ FLAG register READ _ FLAG is defaulted to be an invalid state, and when the SRAM reading operation is started, the READ FLAG register READ _ FLAG is set to be an effective state (READ state or write state);

(8) the MCU inquires a READ/write FLAG register READ _ FLAG after completing the write operation once, if the READ _ FLAG is in a READ state, the MCU indicates that a READ SRAM command is received during the writing of the SRAM, the write SRAM is forced to be interrupted, the write SRAM operation fails, and at the moment, the MCU sends a command to set the READ/write FLAG register READ _ FLAG of the SRAM to be in an idle state, after receiving the command, the FPGA sets the READ _ FLAG to be in an idle state, and meanwhile, the MCU rewrites the data into the SRAM until the writing is successful.

In summary, a reliable method for accessing an SRAM cooperatively by multiple devices is provided, and a flow is shown in fig. 3. The SRAM reading operation does not need to be executed, namely the ongoing SRAM writing operation is possibly interrupted, and the invention ensures that the MCU can reliably complete the SRAM writing operation through a two-time handshake mechanism between the MCU and the FPGA. Before the MCU writes the SRAM, a current state register of the SRAM needs to be inquired firstly to ensure that the current state of the SRAM is in an idle state, so that the first handshake is completed, after the SRAM writing operation is completed once, the SRAM reading mark register needs to be judged again to confirm whether the SRAM writing operation is successful, if the SRAM writing operation is unsuccessful, a command needs to be sent to set the SRAM reading mark register to be invalid, the SRAM is rewritten, and so that the second handshake is completed. The two-way handshake mechanism ensures that the MCU can reliably write the SRAM without the FPGA waiting for reading the SRAM.

The reliable method for the multi-device collaborative access to the SRAM is simple to implement, the software and hardware expenses are low, a practical and effective method is provided for a system with high real-time performance and multi-device access to the SRAM, the two-time handshake mechanism is simple to implement, the reliable and effective operation of reading and writing the SRAM can be ensured, and the method has no special requirements on the reading and writing time, the reading and writing period and the like of the SRAM and has strong universality.

Claims (1)

1. A system for multiple devices to cooperatively access SRAM, comprising: MCU, FPGA, SRAM; the FPGA is used as a master device, and the MCU is used as a slave device; the FPGA is directly connected with the SRAM, the MCU is connected with the FPGA, and the operation of the MCU on the SRAM is realized by the transfer of the FPGA; the priority of the FPGA accessing the SRAM is higher than that of the MCU; the specific access method is as follows:

(1) read SRAM command: the upper computer sends an SRAM reading command, and the FPGA receives and analyzes the command through the serial port;

(2) reading SRAM data: after receiving the SRAM reading command, the FPGA generates an SRAM reading signal, an SRAM chip selection signal and an SRAM writing prohibition enabling signal without waiting, and sends data read out from the SRAM to an upper computer;

(3) SRAM state control: the FPGA controls two registers to mark the state of the SRAM: the current state register of the SRAM and the read-write marking register of the SRAM are respectively used for being read by the MCU; the default state of the current state register is an idle state, when SRAM reading operation is started, the current state register is set to be a read state, the current state register is restored to be the idle state after the reading operation is finished, when the SRAM writing operation is started, the current state register is set to be a write state, the current state register is restored to be the idle state after the writing operation is finished, the read-write marking register is defaulted to be the idle state, and when the SRAM reading operation is started, the read-write marking register is set to be a read-write state;

(4) writing SRAM data: the FPGA controls interaction between an EPI interface of the MCU and the FPGA, before writing the SRAM, the MCU firstly inquires a current state register of the SRAM, when the SRAM is in an idle state, the MCU initiates SRAM writing operation through the EPI interface, the FPGA judges the current state of the SRAM, and if the current state is in the idle state, the FPGA sends the following signals to the SRAM: writing SRAM signals, SRAM chip selection signals and SRAM data signals by the MCU, or else, not sending the signals by the FPGA; after the MCU completes the SRAM writing operation, the MCU queries the SRAM reading and writing mark register, if the reading and writing mark register is in a reading and writing state, the reading and writing SRAM command is received during the SRAM writing period, the SRAM writing is forced to be interrupted, the SRAM writing operation fails, at the moment, the MCU sends a command to set the SRAM reading and writing mark register to be in an idle state, the FPGA sets the reading and writing mark register to be in an idle state after receiving the command, and meanwhile, the MCU writes the data into the SRAM again until the writing is successful.

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