CN103995675A - Method and device for controlling hard disk read-write equipment - Google Patents
Method and device for controlling hard disk read-write equipment Download PDFInfo
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Abstract
The invention discloses a method and device for controlling hard disk read-write equipment. The method and device are used for accurately writing data into and reading data from a hard disk without host interference and control. The method for controlling the hard disk read-write equipment comprises the steps that connection initializing control is carried out on the hard disk read-write equipment, the hard disk read-write equipment is controlled to carry out data transmission at rising edge and falling edge of gating pulse signals sent to a dynamic random memory controller, whether the data transmission is completed is judged to obtain a judgment result, and when the judgment result is that the data transmission is completed, initializing stopping control is carried out on the hard disk read-write equipment. By means of the control method, the hard disk read-write equipment can be small in size, high in flexibility and speed, and capable of being independently applied to video systems, audio systems and other systems where storage of a large number of data is needed, safe data storage at high speed is achieved.
Description
Technical field
The present invention relates to computer memory technical field, more specifically, relate to a kind of control method and device of disk read-write device.
Background technology
Hard-disk interface is the link of transmission command and data between main frame and hard disk, and the quality of interface will directly affect the performance of hard disk.IDE (ATA) hard-disk interface has compatible strong, and data transmission is stable, and lower-price characteristic is widely used in image, Audio and Video is processed and information household appliances etc. need to be stored in the equipment of mass data.Generally, by hardware circuit, form software control and the intervention that main frame side's ata interface controller needs main frame, but this storage organization by host computer control is complicated, weight is large, underaction, not good to the adaptability of environment, can not meet low cost, embedded and personalized data storage requirement.
Therefore, in prior art, exist and cannot effectively save processor and memory source, improve the problem of data rate memory.
Summary of the invention
The present invention discloses a kind of control method and device of disk read-write device, for what solve that prior art exists, cannot effectively save processor and memory source, improves the problem of data rate memory.
For achieving the above object, according to a first aspect of the invention, provide a kind of control method of disk read-write device, and adopt following technical scheme:
The control method of disk read-write device, comprising: disk read-write device is connected to initialization and control; Controlling described disk read-write device is sending to rising edge and the negative edge of the strobe signal of dynamic randon access controller all to carry out data transmission; Judge that whether described data transmission completes, and obtains a judged result; And, described disk read-write device is interrupted to initialization and control while judgment result is that described data transmission completes described.
Further, describedly disk read-write device is connected to initialization control and to comprise: receive hard disk end and send direct memory access request; According to described access request, control described disk read-write device and in the first Preset Time, make the response that direct memory signal is set high; The STOP signal of controlling described disk read-write device in the second Preset Time sets to 0 and HDMARDY signal puts 1; Send an announcement information to described hard disk end, described announcement information is used for notifying described hard disk end to prepare to receive data; Produce after the saltus step of strobe signal described in first obtaining described hard disk end, by first group of data transmission to data bus.
Further, describedly described disk read-write device is interrupted to initialization control and to comprise: control described hard disk end and make described direct memory access request invalid; Control that described disk read-write device sets high described STOP signal in the 3rd default duration, described HDMARDY signal resets; In the described the 4th default duration after described hard disk end is received the saltus step of described STOP signal, set high described strobe signal; Control described disk read-write device and produce DMACK-hopping edge, CRC check is imported into described data bus simultaneously.
Further, the described disk read-write device of described control comprises sending to the rising edge of strobe signal of dynamic randon access controller and negative edge all to carry out data transmission: trigger the idle condition st_idle of setting program, enter described read states st_readstl when receiving read/write command; By setting address wire, read the status register of described hard disk end, check whether described hard disk end meets described idle condition st_idle; When described hard disk end meets described idle condition st_idle, by write device/head register is selected will access means 1 or equipment 0; To feature register, write 03h and start to set transmission mode, high 5 of sector number register writes 01000, represents selected described senior direct memory access mode pattern, and low 3 write 010, represent to select pattern 2, the most backward command register writes set feature order; This need to transmit the shared sector number of data described sector number register-stored, represents to transmit the data of 256 sectors when being 0; Sector number register, cylinder number be low/and most-significant byte register and equipment/head register write address, initial sector physical address or the logical address of this hard disk operation; Judge the state of described data transmission, if read operation, the rising and falling edges in described strobe signal receives data; If write operation, is required at preset timed intervals to produce HSTROBE waveform by described disk read-write device, and imports data into data bus in hopping edge.
According to another aspect of the present invention, provide a kind of control device of disk read-write device, and adopt following technical scheme:
The control device of disk read-write device, comprising: the first control module, for disk read-write device being connected to initialization, control; The second control module, is sending to rising edge and the negative edge of the strobe signal of dynamic machine access controller all to carry out data transmission for controlling described disk read-write device; The first judge module, for judging that whether described data transmission completes, and obtains a judged result; And the 3rd control module, for, described disk read-write device being interrupted to initialization and controls while judgment result is that described data transmission completes described.
Further, described the first control module comprises: receiver module, sends direct memory access request for receiving hard disk end; Respond module makes for control described disk read-write device according to described access request the response that direct memory signal is set high in the first Preset Time; First controls submodule, and for controlling in the second Preset Time, the STOP signal of described disk read-write device sets to 0 and HDMARDY signal puts 1; Sending module, for sending an announcement information to described hard disk end, described announcement information is used for notifying described hard disk end to prepare to receive data; Transport module, for producing after the saltus step of strobe signal described in first obtaining described hard disk end, by first group of data transmission to data bus.
Further, described the 3rd control module comprises: the first submodule, makes described direct memory access request invalid for controlling described hard disk end; The second submodule, for controlling, described disk read-write device sets high described STOP signal in the 3rd default duration, described HDMARDY signal resets; Set high module, for setting high described strobe signal in the described the 4th default duration after described hard disk end is received the saltus step of described STOP signal; The 3rd submodule, produces DMACK-hopping edge for controlling described disk read-write device, CRC check is imported into described data bus simultaneously.
Further, described the second control module comprises: trigger module for triggering the idle condition st_idle of setting program, enters described read states st_readstl when receiving read/write command; Check module, for read the status register of described hard disk end by setting address wire, check whether described hard disk end meets described idle condition st_idle; Writing module, for when described hard disk end meets described idle condition st_idle, by write device/head register is selected will access means 1 or equipment 0; Setting module, starts to set transmission mode for write 03h to feature register, and high 5 of sector number register writes 01000, represent selected described senior direct memory access mode pattern, low 3 write 010, represent to select pattern 2, and the most backward command register writes set feature order; Memory module, for described sector number register-stored, this need to transmit the shared sector number of data, represents to transmit the data of 256 sectors when being 0; Sector number register, cylinder number be low/and most-significant byte register and equipment/head register write address, initial sector physical address or the logical address of this hard disk operation; And second judge module, for judging the state of described data transmission, if read operation, the rising and falling edges in described strobe signal receives data; If write operation, is required at preset timed intervals to produce HSTROBE waveform by described disk read-write device, and imports data into data bus in hopping edge.
The present invention has realized in the upper design of FPGA (field programmable gate array) UltraDMA (senior direct memory access) read-write controller that a kind of off is intervened, have that volume is little, dirigibility is high, fireballing advantage, can be used for realizing mass data storage, there is better practicality.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, forms the application's a part, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 represents the control method schematic diagram of the disk read-write device described in the embodiment of the present invention;
Fig. 2 represents the senior direct memory access hard disk of the disk read-write device end data input initialization process sequential logic figure described in the embodiment of the present invention;
Fig. 3 represents the constitutional diagram of the senior direct memory access data transmission procedure of disk read-write device described in the embodiment of the present invention;
Fig. 4 represents that the senior direct memory access hard disk of the disk read-write device end start-stop described in the embodiment of the present invention connects sequential logic figure;
Fig. 5 represents the data input initialization stage schematic diagram that the disk read-write device described in the embodiment of the present invention captures with Chipscope software;
Fig. 6 represents the data transmission procedure schematic diagram that the disk read-write device described in the embodiment of the present invention captures with Chipscope software;
Fig. 7 represents the data input termination phase schematic diagram that the disk read-write device described in the embodiment of the present invention captures with Chipscope software;
Fig. 8 represents the data output initial phase schematic diagram that the disk read-write device described in the embodiment of the present invention captures with Chipscope software;
Fig. 9 represents the data output termination stage schematic diagram that the disk read-write device described in the embodiment of the present invention captures with Chipscope software;
Figure 10 represents that the disk read-write device described in the embodiment of the present invention takies FPGA resource situation;
Figure 11 represents the control device general frame of the disk read-write device described in the embodiment of the present invention;
Figure 12 represents the control device interface definition figure of the disk read-write device described in the embodiment of the present invention;
Figure 13 represents the control device structural drawing of the disk read-write device described in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, embodiments of the invention are elaborated, but the multitude of different ways that the present invention can be defined by the claims and cover is implemented.
Fig. 1 represents the control method schematic diagram of the disk read-write device described in the embodiment of the present invention.
Shown in Figure 1, the control method of disk read-write device comprises:
S101: disk read-write device is connected to initialization and control;
S103: control described disk read-write device and sending to rising edge and the negative edge of the strobe signal of dynamic randon access controller all to carry out data transmission;
S105: judge that whether described data transmission completes, and obtains a judged result;
S107: while judgment result is that described data transmission completes, described disk read-write device is interrupted to initialization and control described.
In step S101, senior direct memory access hard disk end data input initialization process sequential logic figure shown in Figure 2.First by hard disk end, send direct memory access request, main frame is made the response that direct memory signal is set high after receiving request in the first Preset Time, the STOP signal of simultaneously controlling described disk read-write device in the second Preset Time sets to 0 and HDMARDY signal puts 1, notice hard disk and host end has performed the preparation that receives data, after this, hard disk end produces the saltus step of first strobe signal, and by first group of data transmission to data bus, complete and connect initialization and control.As system verification, Fig. 5 is the data input initialization stage schematic diagram that all Chipscope software captures, first hard disk end sends direct memory access request (dmarq=1) as shown, controller end makes DMACK effectively (Low level effective) as response, then STOP resets, hdmardy is effective, represents that master controller is ready to receive data.Hard disk end starts to produce first strobe signal saltus step after receiving signal, spreads out of first group of 16 bit data simultaneously, and so far initialization finishes.The data output initial phase schematic diagram of Fig. 8 for capturing with Chipscope software, after hard disk and controller " are shaken hands " and are completed, by controller, produce first HSTROBE (writing) saltus step, first data (0000h) are imported into data bus, after this data are transmitted in order simultaneously.
In step S103, the constitutional diagram of senior direct memory access data transmission procedure shown in Figure 3, describes each state of data transmission procedure in detail, comprising:
S301: idle condition st_idle;
In this step, first setting program triggers this state, enters st_readstl state when receiving read/write command, otherwise keeps.
S302: read states register st_readstl;
In this step, by setting address wire (CS & DA=" 10111 "), read disk state register, check and whether meet BSY=0 & DRQ=0 (hard disk is idle), meet and enter NextState, otherwise continue access until the hard disk free time.
S303: equipment selection mode st_selectdev;
In this step, by write device/head register (CS & DA=" 10110 "), selecting will access means 1 or equipment 0.
S304: read states register st_readst2;
In this step, read disk state, the free time enters NextState, otherwise keeps.
S305: interface features st_setfeature is set;
In this step, after selected equipment, to feature register, write 03h and start to set transmission mode: high 5 of sector number register writes 01000, represent selected senior direct memory access pattern, low 3 write 010, represent to select pattern 2, the most backward command register writes set feature order (EFh), and end is set.
S306: read states register st_readst3.
S307: write order parameter s t_weparameter;
In this step, this need to transmit the shared sector number of data sector number register-stored, represents to transmit the data of 256 sectors when being 0; Sector number register, cylinder number be low/and most-significant byte register and equipment/head register write the address, initial sector (physical address or logical address) of this hard disk operation.
S308: write order st_wec;
In this step, during read operation, write order C8h (Read DMA), during write operation, write order CAh (Write DMA).
S309: senior direct memory access initialization st_initiate;
In this step, enter and first wait for that DMARQ signal puts one after this state, then senior direct memory access controller starts to set STOP (read/write), DMACK (read/write), HDMARDY (reading) and HSTROBE (writing) by Fig. 1 sequential, until receive or export first group of data after enter data transmission state.
S310: data transmission state st_transdata;
In this step, if read operation, the rising and falling edges at DSTROBE receives data; If write operation, is pressed time requirement (Cycle=54ns) the generation HSTROBE waveform of mode2, and in hopping edge, data is imported into data bus (ddi (15:0)) by senior direct memory access controller.
S311: stop connecting and send CRC check value st_crc;
In this step, when a sector data transfers (not opening interruption) or during all data transmission complete (opening interruption), crc value controller being calculated in the hopping edge of DMACK writes hard disk.
S312: read states register st_readst4;
In this step, if BSY=0 & is DRQ=0, get back to st_idle state, finish once transmission; If BSY=1 & is DRQ=0, keep; If BSY=0 & DRQ=1 & DMARQ=1 (not opening interruption), enters st_initiate, continue data transmission.
S313: error condition St_err enters this state when wrong generation.
As system verification, Fig. 6 is the data transmission procedure schematic diagram that disk read-write device captures with Chipscope software, from hard disk reading data course.Hard disk master boot record sector is read in this time read operation, and in this sector, the value of " guiding designator " should be 0x80, and the value of initial magnetic head and initial sector is generally 0x01.In Fig. 6,0180 (anti-byte shows: high address is front, and low address is rear) was " the guiding designator " and the initial magnetic head that read, and ensuing 0001 is initial sector, and reading result conforms to theory.
In step S107, senior direct memory access hard disk end start-stop shown in Figure 4 connects sequential logic figure.First hard disk end makes direct memory access request invalid, host side detects direct memory access request and in the 3rd default duration, sets high STOP signal, reset HDMARDY signal after invalid, hard disk end receives in the default duration of the 4th after the saltus step of STOP signal and sets high described strobe signal, shows after this not have data etc. to be transmitted.Host side produces DMACK-hopping edge afterwards, CRC check is imported into described data bus simultaneously, and hard disk receives that check results and the proof test value of oneself compare, and with this, judges and whether transmits mistake, completes whole senior direct memory access control procedure.As system verification, Fig. 7 is the data input termination phase schematic diagram that disk read-write device captures with Chipscope software.Wherein reading last two byte datas is AA55, and " boot section mark ", identical with actual conditions; In figure, last F445 is CRC check value, when the saltus step of DMACK arrives, returns to hard disk, by hard disk, is judged whether correctly.Controller will be read data and deposit reception buffer zone in, and waiting for CPU reads.Fig. 9 is the data output termination stage schematic diagram that disk read-write device captures with Chipscope software.Hard disk first make ddmardy (Low level effective) and dmarq invalid, master controller end produces stop signal, and in the end last two byte datas (00FFh) are transmitted in a HSTROBE (writing) hopping edge.After user data transmission is complete, in DMACK hopping edge, CRC check value (8985h) is passed to hard disk.
Figure 10 is that in system verification process, disk read-write device takies FPGA resource situation.From figure, also can find out, adopt technique scheme, whole process is carried out under without CPU environment, the read/write of controller has been controlled by enable signal separately, volume is little, dirigibility is high, speed is fast, can be applied independently in video, audio frequency etc. needs in the system of mass data storage, the storage of the high-speed secure of complete paired data.
As shown in figure 11, the controller of design comprises senior direct memory access read-write control module, receives buffer module and send buffer module the control device general frame of disk read-write device.It is the main modular of design that its middle-and-high-ranking direct memory access read-write is controlled, and for realizing the whole flow process with senior direct memory access mode access hard disk, comprises the transmission to the access of hard disk register and user data; Receive/send buffer module and realize the buffer memory to user data, during design, adopt two-port RAM to realize.
Interface connects design as shown in figure 12 particularly, and this figure is the encapsulation of the RTL top layer after ISE10.1 is comprehensive figure by VHDL code, and right-side signal is by controller, to be outputed to the control signal of hard disk, and left-side signal is the signal of the senior direct memory access controller of input.Design adopts the Virtex-II development board of Xilinx to realize, owing to there is no ide interface on development board, therefore hard disk is accessed to J5 expansion mouthful through self-designed adapter.J5 can provide 37 bidirectional interfaces, a ground wire and two direct current supply lines.During connection, 7 ground wires of IDE are connected with J5 ground wire, all the other 32 self-defined accesses of signal wire.LVTTL (level standard) mode that the level that defines each signal wire all adopts FPGA to provide while driving.
Figure 13 represents the control device structural drawing of the disk read-write device described in the embodiment of the present invention.
Shown in Figure 13, the control device of disk read-write device comprises: the first control module 1301, for disk read-write device being connected to initialization, control; The second control module 1303, is sending to rising edge and the negative edge of the strobe signal of dynamic randon access controller all to carry out data transmission for controlling described disk read-write device; The first judge module 1305, for judging that whether described data transmission completes, and obtains a judged result; The 3rd control module 1307, for, interrupting initialization to described disk read-write device and control while judgment result is that described data transmission completes described.
Further, the first control module comprises: receiver module (not shown), sends direct memory access request for receiving hard disk end; Respond module (not shown) makes for control described disk read-write device according to described access request the response that direct memory signal is set high in the first Preset Time; First controls submodule (not shown), and for controlling in the second Preset Time, the STOP signal of described disk read-write device sets to 0 and HDMARDY signal puts 1; Sending module (not shown), for sending an announcement information to described hard disk end, described announcement information is used for notifying described hard disk end to prepare to receive data; Transport module (not shown), for producing after the saltus step of strobe signal described in first obtaining described hard disk end, by first group of data transmission to data bus.
Further, the second control module comprises: trigger module (not shown) for triggering the idle condition st_idle of setting program, enters described read states st_readstl when receiving read/write command; Check module (not shown), for read the status register of described hard disk end by setting address wire, check whether described hard disk end meets described idle condition st_idle; Writing module (not shown), for when described hard disk end meets described idle condition st_idle, by write device/head register is selected will access means 1 or equipment 0; Setting module (not shown), for writing 03h to feature register, start to set transmission mode, high 5 of sector number register writes 01000, represent selected described senior direct memory access mode pattern, low 3 write 010, represent to select pattern 2, the most backward command register writes set feature order; Memory module (not shown), for described sector number register-stored, this need to transmit the shared sector number of data, represents to transmit the data of 256 sectors when being 0; Sector number register, cylinder number be low/and most-significant byte register and equipment/head register write address, initial sector physical address or the logical address of this hard disk operation; The second judge module (not shown), for judging the state of described data transmission, if read operation, the rising and falling edges in described strobe signal receives data; If write operation, is required at preset timed intervals to produce HSTROBE waveform by described disk read-write device, and imports data into data bus in hopping edge.
Further, the 3rd control module comprises: the first submodule (not shown), makes described direct memory access request invalid for controlling described hard disk end; The second submodule (not shown), for controlling, described disk read-write device sets high described STOP signal in the 3rd default duration, described HDMARDY signal resets; Set high module (not shown), for setting high described strobe signal in the described the 4th default duration after described hard disk end is received the saltus step of described STOP signal; The 3rd submodule (not shown), produces DMACK-hopping edge for controlling described disk read-write device, CRC check is imported into described data bus simultaneously.
Adopt technique scheme, with FPGA, realize the UltraDMA read-write controller that meets ATA standard, can the read-write operation of complete independently to hard disk.If controller is changed a little, as coordinated corresponding document system, as FAT32 or EXT, will can be used for, in embedded device, realizing mass data storage, make system there is better practicality.
Claims (8)
1. a control method for disk read-write device, is characterized in that, comprising:
Disk read-write device is connected to initialization to be controlled;
Controlling described disk read-write device is sending to rising edge and the negative edge of the strobe signal of dynamic randon access controller all to carry out data transmission;
Judge that whether described data transmission completes, and obtains a judged result;
Described, while judgment result is that described data transmission completes, described disk read-write device interrupted to initialization and control.
2. control method as claimed in claim 1, is characterized in that, describedly disk read-write device is connected to initialization controls and to comprise:
Receive hard disk end and send direct memory access request;
According to described access request, control described disk read-write device and in the first Preset Time, make the response that direct memory signal is set high;
The STOP signal of controlling described disk read-write device in the second Preset Time sets to 0 and HDMARDY signal puts 1;
Send an announcement information to described hard disk end, described announcement information is used for notifying described hard disk end to prepare to receive data;
Produce after the saltus step of strobe signal described in first obtaining described hard disk end, by first group of data transmission to data bus.
3. control method as claimed in claim 1, is characterized in that, describedly described disk read-write device is interrupted to initialization controls and to comprise:
Controlling described hard disk end makes described direct memory access request invalid;
Control that described disk read-write device sets high described STOP signal in the 3rd default duration, described HDMARDY signal resets;
In the described the 4th default duration after described hard disk end is received the saltus step of described STOP signal, set high described strobe signal;
Control described disk read-write device and produce DMACK-hopping edge, CRC check is imported into described data bus simultaneously.
4. control method as claimed in claim 1, is characterized in that, the described disk read-write device of described control comprises sending to the rising edge of strobe signal of dynamic randon access controller and negative edge all to carry out data transmission:
The idle condition st_idle that triggers setting program enters described read states st_readstl when receiving read/write command;
By setting address wire, read the status register of described hard disk end, check whether described hard disk end meets described idle condition st_idle;
When described hard disk end meets described idle condition st_idle, by write device/head register is selected will access means 1 or equipment 0;
To feature register, write 03h and start to set transmission mode, high 5 of sector number register writes 01000, represents selected described senior direct memory access mode pattern, and low 3 write 010, represent to select pattern 2, the most backward command register writes set feature order;
This need to transmit the shared sector number of data described sector number register-stored, represents to transmit the data of 256 sectors when being 0; Sector number register, cylinder number be low/and most-significant byte register and equipment/head register write address, initial sector physical address or the logical address of this hard disk operation;
Judge the state of described data transmission, if read operation, the rising and falling edges in described strobe signal receives data; If write operation, is required at preset timed intervals to produce HSTROBE waveform by described disk read-write device, and imports data into data bus in hopping edge.
5. a control device for disk read-write device, is characterized in that, comprising:
The first control module, controls for disk read-write device being connected to initialization;
The second control module, is sending to rising edge and the negative edge of the strobe signal of dynamic randon access controller all to carry out data transmission for controlling described disk read-write device;
The first judge module, for judging that whether described data transmission completes, and obtains a judged result;
The 3rd control module, for, interrupting initialization to described disk read-write device and control while judgment result is that described data transmission completes described.
6. control device as claimed in claim 5, is characterized in that, described the first control module comprises:
Receiver module, sends direct memory access request for receiving hard disk end;
Respond module makes for control described disk read-write device according to described access request the response that direct memory signal is set high in the first Preset Time;
First controls submodule, and for controlling in the second Preset Time, the STOP signal of described disk read-write device sets to 0 and HDMARDY signal puts 1;
Sending module, for sending an announcement information to described hard disk end, described announcement information is used for notifying described hard disk end to prepare to receive data;
Transport module, for producing after the saltus step of strobe signal described in first obtaining described hard disk end, by first group of data transmission to data bus.
7. control device as claimed in claim 5, is characterized in that, described the 3rd control module comprises:
The first submodule, makes described direct memory access request invalid for controlling described hard disk end;
The second submodule, for controlling, described disk read-write device sets high described STOP signal in the 3rd default duration, described HDMARDY signal resets;
Set high module, for setting high described strobe signal in the described the 4th default duration after described hard disk end is received the saltus step of described STOP signal;
The 3rd submodule, produces DMACK-hopping edge for controlling described disk read-write device, CRC check is imported into described data bus simultaneously.
8. control device as claimed in claim 5, is characterized in that, described the second control module comprises:
Trigger module for triggering the idle condition st_idle of setting program, enters described read states st_readstl when receiving read/write command;
Check module, for read the status register of described hard disk end by setting address wire, check whether described hard disk end meets described idle condition st_idle;
Writing module, for when described hard disk end meets described idle condition st_idle, by write device/head register is selected will access means 1 or equipment 0;
Setting module, starts to set transmission mode for write 03h to feature register, and high 5 of sector number register writes 01000, represent selected described senior direct memory access mode pattern, low 3 write 010, represent to select pattern 2, and the most backward command register writes set feature order;
Memory module, for described sector number register-stored, this need to transmit the shared sector number of data, represents to transmit the data of 256 sectors when being 0; Sector number register, cylinder number be low/and most-significant byte register and equipment/head register write address, initial sector physical address or the logical address of this hard disk operation;
The second judge module, for judging the state of described data transmission, if read operation, the rising and falling edges in described strobe signal receives data; If write operation, is required at preset timed intervals to produce HSTROBE waveform by described disk read-write device, and imports data into data bus in hopping edge.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108733479A (en) * | 2017-04-24 | 2018-11-02 | 上海宝存信息科技有限公司 | Unload the method for solid state disk card and the device using this method |
| CN108153485A (en) * | 2017-11-20 | 2018-06-12 | 天津津航技术物理研究所 | A kind of more equipment collaborations access the method and system of SRAM |
| CN108153485B (en) * | 2017-11-20 | 2021-06-22 | 天津津航技术物理研究所 | Method and system for multi-device cooperative access to SRAM |
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