CN108109915B - Radio frequency triode and manufacturing method thereof - Google Patents
Radio frequency triode and manufacturing method thereof Download PDFInfo
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- CN108109915B CN108109915B CN201711396254.XA CN201711396254A CN108109915B CN 108109915 B CN108109915 B CN 108109915B CN 201711396254 A CN201711396254 A CN 201711396254A CN 108109915 B CN108109915 B CN 108109915B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 108
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 54
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 54
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 21
- 238000002513 implantation Methods 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Cold Cathode And The Manufacture (AREA)
Abstract
The invention relates to a radio frequency triode and a manufacturing method thereof. The radio frequency triode obtained by the manufacturing method comprises a silicon substrate, an N-type epitaxial layer formed on the silicon substrate, two first P-type high-doped regions formed on the surface of the N-type epitaxial layer, a P-type low-doped region formed between the two P-type high-doped regions, field oxide layers which are formed on the N-type epitaxial layer on two sides of the P-type high-doped region and provided with sharp corners, an N-type region formed on the surface of the P-type low-doped region, first polysilicon and silicon dioxide layers sequentially formed above the field oxide layers and the P-type high-doped region, a side wall formed on the P-type high-doped region and adjacent to the P-type low-doped region, a silicon nitride layer and another silicon dioxide layer formed on the top and the side wall of the first polysilicon and the silicon dioxide, and second polysilicon formed on the N-type region.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor manufacturing processes, in particular to a radio frequency triode and a manufacturing method thereof.
[ background of the invention ]
When the conventional radio frequency triode is formed with a P-type high doping region and a P-type low doping region, the concentration of the P-type low doping region is seriously influenced because the lateral diffusion of the P-type high doping region influences the P-type low doping region. The P-type low doped region is very critical to the amplification factor of the device operation. Conventionally, the width of the P-type low-doped region is ensured to be large enough, so that the N + region in the P-type low-doped region is far away from the P-type high-doped region. However, this causes the size of the device to become large, which increases the area of the individual device and increases the manufacturing cost.
Specifically, when the radio frequency triode is manufactured by the existing manufacturing process, after silicon dioxide and polysilicon are etched, a lightly doped P-type low doped region is injected, and then heat treatment is performed, so that concentrated P-type impurities in the polysilicon are diffused into an N-N type epitaxial layer to form a P-type high doped region. Because the P-type impurities in the polysilicon are very concentrated, the diffused P-type high-doping region can be diffused in the transverse direction to influence the P-type low-doping region, so that the amplification factor of the device operation can be influenced, the device performance is influenced, and the device reliability is reduced.
[ summary of the invention ]
The invention provides a novel radio frequency triode and a manufacturing method thereof, aiming at the problems of the manufacturing process flow and the device structure of the existing radio frequency triode, solving at least one technical problem and not increasing excessive manufacturing cost.
A manufacturing method of a radio frequency triode comprises the following steps:
providing a silicon substrate, and forming an N-type epitaxial layer on the silicon substrate;
sequentially forming a first silicon dioxide layer and a first silicon nitride layer on the N-type epitaxial layer;
photoetching and etching the first silicon nitride layer, and removing partial nitride layers at two ends to form an opening region;
growing field oxide layers on the opening region and a part of silicon dioxide layer adjacent to the opening region, so that a field oxide layer with a sharp angle is formed between two ends of the first silicon nitride layer and the N-type epitaxial layer, wherein the sharp angle of the field oxide layer corresponds to the first silicon dioxide layer of the other part, and the N-type epitaxial layer comprises a corner adjacent to the field oxide layer;
removing the first silicon nitride layer and the first silicon dioxide layer;
sequentially forming a first polysilicon layer and a second silicon dioxide layer on the surface of the N-type epitaxial layer, and performing first P-type ion implantation on the first polysilicon layer;
photoetching and etching the second silicon dioxide layer and the first polysilicon to form a groove which penetrates through the second silicon dioxide layer and the first polysilicon and extends into the N-type epitaxial layer;
performing heat treatment and second P-type ion implantation to enable P-type ions in the first polycrystalline silicon to diffuse towards the N-type epitaxial layer, so that a P-type high-doped region is formed on the surface of the N-type epitaxial layer below the first polycrystalline silicon and a P-type low-doped region is formed on the surface of the N-type epitaxial layer below the groove;
forming a second silicon nitride layer and a third silicon dioxide layer on the P-type low-doped region at the groove and the first polycrystalline silicon in sequence;
etching the third silicon dioxide layer so as to remove part of the third silicon dioxide layer above the second silicon nitride layer on the groove, wherein the side wall of the groove and the third silicon dioxide layer outside the groove are reserved;
removing part of the second silicon nitride layer at the bottom of the groove to expose part of the P-type low-doped region;
and forming second polysilicon on the P-type low-doped region, and performing heat treatment on the second polysilicon to diffuse N-type impurities of the second polysilicon to the surface of the P-type low-doped region, so as to form an N-type region on the surface of the P-type low-doped region.
In one embodiment, the growth temperature of the field oxide layer is in the range of 700 to 1200 degrees celsius, and the growth thickness is in the range of 0.4 to 2 um.
In one embodiment, the step of removing the first silicon nitride layer and the first silicon dioxide layer comprises: firstly, removing the first silicon nitride layer by adopting hot concentrated phosphoric acid; and removing the first silicon dioxide layer by adopting hydrofluoric acid solution.
In one embodiment, the first polysilicon is formed at a temperature in a range of 400 degrees celsius to 900 degrees celsius and at a thickness in a range of 0.1um to 0.5 um; the thickness of the second silicon dioxide layer is in the range of 0.02um to 0.1 um.
In one embodiment, the second silicon dioxide layer has a thickness in the range of 0.02um to 0.1 um.
In one embodiment, in the first P-type ion implantation, the implanted ions include B or BF2, the implantation dose is in a range from 14 to 16 powers per square centimeter 1, and the implantation energy is in a range from 50KEV to 200 KEV.
In one embodiment, in the second P-type ion implantation, the implanted ions include B or BF2, the implantation dose is in a range from 12 to 14 powers per square centimeter 1, and the implantation energy is in a range from 20 to 200 KEV.
In one embodiment, the second polysilicon is formed at a temperature in a range of 400 degrees celsius to 1000 degrees celsius and a thickness in a range of 0.02um to 2 um; and in the step of N-type ion implantation of the second polysilicon, the implanted ions comprise phosphorus or arsenic, the implantation dosage is in the range of 15 powers of 1 per square centimeter to 16 powers of 5 per square centimeter, and the implantation energy is in the range of 20KEV to 200 KEV.
In one embodiment, the depth of the trench in the N-type epitaxial layer is in the range of 0.2um to 0.5 um.
A radio frequency triode comprises a silicon substrate, an N-type epitaxial layer formed on the silicon substrate, two first P-type high-doped regions formed on the surface of the N-type epitaxial layer, a P-type low-doped region formed between the two P-type high-doped regions, field oxide layers which are formed on the N-type epitaxial layer on two sides of the P-type high-doped region and are provided with sharp corners, an N-type region formed on the surface of the P-type low-doped region, first polysilicon and silicon dioxide layers sequentially formed above the field oxide layers and the P-type high-doped region, a side wall formed on the P-type high-doped region and adjacent to the P-type low-doped region, a silicon nitride layer and another silicon dioxide layer on the top and the side wall of the first polysilicon and the silicon dioxide, and second polysilicon formed on the N-type region.
Compared with the prior art, in the radio frequency triode and the manufacturing method thereof, when the first polycrystalline silicon is etched, the silicon substrate is also etched to form grooves, so that the lateral diffusion of the P-type high-doping area cannot influence the P-type low-doping area, the problem that the diffusion influences the performance of the device is avoided, and the reliability of the device is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive efforts.
Fig. 1 is a flow chart of a method for manufacturing a radio frequency transistor according to the present invention.
Fig. 2-13 are schematic structural diagrams of steps of a method for manufacturing the rf transistor shown in fig. 1.
Description of the main elements
P-type low doped region: p-type low doped region
P-type highly doped region: p-type highly doped region
An N-type region: n + region
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 13, fig. 1 is a flowchart illustrating a method for fabricating a radio frequency transistor according to the present invention, and fig. 2 to 13 are schematic structural diagrams illustrating steps of the method for fabricating the radio frequency transistor illustrated in fig. 1. The manufacturing method of the radio frequency triode comprises the following steps.
In step S1, referring to fig. 2, a silicon substrate is provided, and an N-type epitaxial layer is formed on the silicon substrate. The N-type epitaxial layer is an N-type epitaxial layer. The silicon substrate is an N-type substrate.
In step S2, referring to fig. 3, a first silicon dioxide layer and a first silicon nitride layer are sequentially formed on the N-type epitaxial layer.
In step S3, referring to fig. 4, the first silicon nitride layer is subjected to photolithography and etching to remove portions of the nitride layer at two ends, thereby forming an opening region.
Step S4, please refer to fig. 5, in which field oxide layers are grown on the open region and a portion of the silicon dioxide layer adjacent to the open region, so that a field oxide layer having a sharp corner is formed between two ends of the first silicon nitride layer and the N-type epitaxial layer, the sharp corner of the field oxide layer corresponds to another portion of the first silicon dioxide layer, and the N-type epitaxial layer includes a corner adjacent to the field oxide layer. Wherein, the growth temperature of field oxide is in the scope of 700 degrees centigrade to 1200 degrees centigrade, and growth thickness is in the scope of 0.4um to 2 um.
In step S5, please refer to fig. 6, the first silicon nitride layer and the first silicon dioxide layer are removed. The step S5 includes: firstly, removing the first silicon nitride layer by adopting hot concentrated phosphoric acid; and removing the silicon dioxide layer by adopting a hydrofluoric acid solution.
In step S6, referring to fig. 7, a first polysilicon layer and a second silicon dioxide layer are sequentially formed on the surface of the N-type epitaxial layer, and a first P-type ion implantation is performed on the first polysilicon layer. The forming temperature of the first polysilicon is within the range of 400-900 ℃, and the thickness of the first polysilicon is within the range of 0.1-0.5 um; the thickness of the second silicon dioxide layer is in the range of 0.02um to 0.1 um. The thickness of the second silicon dioxide layer is in the range of 0.02um to 0.1 um. In the first P-type ion implantation, the implanted ions comprise B or BF2, the implantation dosage is in the range of 14 powers per square centimeter 1 to 16 powers per square centimeter 1, and the implantation energy is in the range of 50KEV to 200 KEV.
In step S7, referring to fig. 8, the second silicon dioxide layer and the first polysilicon are etched by photolithography, so as to form a trench penetrating through the second silicon dioxide layer and the first polysilicon and extending into the N-type epitaxial layer. The depth of the trench in the N-type epitaxial layer is in the range of 0.2um to 0.5 um.
In step S8, referring to fig. 9, a heat treatment and a second P-type ion implantation are performed to diffuse the P-type ions in the first polysilicon toward the N-type epitaxial layer, so as to form a P-type highly doped region on the surface of the N-type epitaxial layer under the first polysilicon and a P-type lowly doped region on the surface of the N-type epitaxial layer under the trench. In the second P-type ion implantation, the implanted ions comprise B or BF2, the implantation dosage is in a range from 12 powers per square centimeter 1 to 14 powers per square centimeter 1, and the implantation energy is in a range from 20KEV to 200 KEV. As can be seen, a transition region is formed between the P-type highly doped region and the P-type lowly doped region.
In step S9, referring to fig. 10, a second silicon nitride layer and a third silicon dioxide layer are sequentially formed on the P-type low-doped region at the trench and on the first polysilicon.
In step S10, please refer to fig. 11, the third silicon dioxide layer is etched, so that a portion of the third silicon dioxide layer above the second silicon nitride layer on the trench is removed, and the trench sidewall and the third silicon dioxide layer outside the trench are retained.
In step S11, please refer to fig. 12, a portion of the second silicon nitride layer at the bottom of the trench is removed, so that a portion of the P-type low-doped region is exposed.
In step S12, referring to fig. 13, a second polysilicon is formed on the P-type low-doped region, and the second polysilicon is subjected to a thermal process to diffuse N-type impurities of the second polysilicon to the surface of the P-type low-doped region, so as to form an N-type region on the surface of the P-type low-doped region. The forming temperature of the second polysilicon is within the range of 400 ℃ to 1000 ℃, and the thickness of the second polysilicon is within the range of 0.02um to 2 um; and in the step of N-type ion implantation of the second polysilicon, the implanted ions comprise phosphorus or arsenic, the implantation dosage is in the range of 15 powers of 1 per square centimeter to 16 powers of 5 per square centimeter, and the implantation energy is in the range of 20KEV to 200 KEV. The N-type region is an N-type highly doped region.
As shown in fig. 13, the radio frequency triode includes a silicon substrate, an N-type epitaxial layer formed on the silicon substrate, two first P-type highly doped regions formed on the surface of the N-type epitaxial layer, a P-type lowly doped region formed between the two P-type highly doped regions, a field oxide layer formed on the N-type epitaxial layer on both sides of the P-type highly doped region and having a sharp corner, an N-type region formed on the surface of the P-type lowly doped region, a first polysilicon and a silicon dioxide layer sequentially formed on the field oxide layer and the P-type highly doped region, a sidewall formed on the P-type highly doped region adjacent to the P-type lowly doped region, a silicon nitride layer and another silicon dioxide layer on the top and sidewall of the first polysilicon and the silicon dioxide, and a second polysilicon formed on the N-type region. And a transition region is formed between the P-type high doping region and the P-type low doping region.
Compared with the prior art, in the radio frequency triode and the manufacturing method thereof, when the first polycrystalline silicon is etched, the silicon substrate is also etched to form grooves, so that the lateral diffusion of the P-type high-doping area cannot influence the P-type low-doping area, the problem that the diffusion influences the performance of the device is avoided, and the reliability of the device is improved.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (9)
1. A manufacturing method of a radio frequency triode is characterized by comprising the following steps:
providing a silicon substrate, and forming an N-type epitaxial layer on the silicon substrate;
sequentially forming a first silicon dioxide layer and a first silicon nitride layer on the N-type epitaxial layer;
photoetching and etching the first silicon nitride layer, and removing partial nitride layers at two ends to form an opening region;
growing field oxide layers on the opening region and a part of silicon dioxide layer adjacent to the opening region, so that a field oxide layer with a sharp angle is formed between two ends of the first silicon nitride layer and the N-type epitaxial layer, wherein the sharp angle of the field oxide layer corresponds to the first silicon dioxide layer of the other part, and the N-type epitaxial layer comprises a corner adjacent to the field oxide layer;
removing the first silicon nitride layer and the first silicon dioxide layer;
sequentially forming a first polysilicon layer and a second silicon dioxide layer on the surface of the N-type epitaxial layer, and performing first P-type ion implantation on the first polysilicon layer;
photoetching and etching the second silicon dioxide layer and the first polysilicon to form a groove which penetrates through the second silicon dioxide layer and the first polysilicon and extends into the N-type epitaxial layer;
performing heat treatment and second P-type ion implantation to enable P-type ions in the first polycrystalline silicon to diffuse towards the N-type epitaxial layer, so that a P-type high-doped region is formed on the surface of the N-type epitaxial layer below the first polycrystalline silicon and a P-type low-doped region is formed on the surface of the N-type epitaxial layer below the groove;
forming a second silicon nitride layer and a third silicon dioxide layer on the P-type low-doped region at the groove and the first polycrystalline silicon in sequence;
etching the third silicon dioxide layer so as to remove part of the third silicon dioxide layer above the second silicon nitride layer on the groove, wherein the side wall of the groove and the third silicon dioxide layer outside the groove are reserved;
removing part of the second silicon nitride layer at the bottom of the groove to expose part of the P-type low-doped region;
and forming second polysilicon on the P-type low-doped region, and performing heat treatment on the second polysilicon to diffuse N-type impurities of the second polysilicon to the surface of the P-type low-doped region, so as to form an N-type region on the surface of the P-type low-doped region.
2. The method of claim 1, wherein the method comprises: the growth temperature of the field oxide layer is within the range of 700-1200 ℃, and the growth thickness is 0.4μmTo 2μmWithin the range of (1).
3. The method of claim 1, wherein the method comprises: the step of removing the first silicon nitride layer and the first silicon dioxide layer comprises: firstly, removing the first silicon nitride layer by adopting hot concentrated phosphoric acid; and removing the first silicon dioxide layer by adopting hydrofluoric acid solution.
4. The method of claim 1, wherein the method comprises: the forming temperature of the first polysilicon is within the range of 400-900 ℃, and the thickness of the first polysilicon is 0.1 DEG Cμm-0.5μmBetween the ranges of (1); the thickness of the second silicon dioxide layer is 0.02μmTo 0.1μmWithin the range of (1).
5. The method of claim 1, wherein the method comprises: the thickness of the second silicon dioxide layer is 0.02μmTo 0.1μmWithin the range of (1).
6. The method of claim 1, wherein the method comprises: in the first P-type ion implantation, the implanted ions comprise B or BF2, the implantation dosage is in the range of 14 powers per square centimeter 1 to 16 powers per square centimeter 1, and the implantation energy is in the range of 50KEV to 200 KEV.
7. The method of claim 1, wherein the method comprises: in the second P-type ion implantation, the implanted ions comprise B or BF2, the implantation dosage is in a range from 12 powers per square centimeter 1 to 14 powers per square centimeter 1, and the implantation energy is in a range from 20KEV to 200 KEV.
8. The method of claim 1, wherein the method comprises: the second polysilicon has a forming temperature of 400-1000 deg.C and a thickness of 0.02μmTo 2μmWithin the range of (1); and in the step of N-type ion implantation of the second polysilicon, the implanted ions comprise phosphorus or arsenic, the implantation dosage is in the range of 15 powers of 1 per square centimeter to 16 powers of 5 per square centimeter, and the implantation energy is in the range of 20KEV to 200 KEV.
9. The method of claim 1, wherein the method comprises: the depth of the groove in the N-type epitaxial layer is 0.2μmTo 0.5μmWithin the range of (1).
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Effective date of registration: 20200511 Address after: 1706-1, building a, phase I, Tianan Innovation Technology Plaza, No.29, Tairan 4th Road, Tianan community, Shatou street, Futian District, Shenzhen City, Guangdong Province Applicant after: SHENZHEN FIRST SEMICONDUCTOR Co.,Ltd. Address before: 518000 Guangdong city of Shenzhen province Baoan District Fuyong Street Peace community Junfeng Industrial Zone A3 building the first floor Applicant before: SHENZHEN JINGTE SMART MANUFACTURING TECHNOLOGY Co.,Ltd. |
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