CN108089955A - A kind of PCIE signal measurement jig and test method based on OCuLink interfaces - Google Patents
A kind of PCIE signal measurement jig and test method based on OCuLink interfaces Download PDFInfo
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- CN108089955A CN108089955A CN201711243801.0A CN201711243801A CN108089955A CN 108089955 A CN108089955 A CN 108089955A CN 201711243801 A CN201711243801 A CN 201711243801A CN 108089955 A CN108089955 A CN 108089955A
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- oculink
- interfaces
- measurement jig
- signal
- pcie
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing Of Electrical Connectors (AREA)
Abstract
The PCIE signal measurement jig and test method of the present application OCuLink interfaces, it is that OCuLink male connectors and SMP female interfaces are reserved on measurement jig, OCuLink male connectors are for the connection of measurement jig and tested interface, and SMP females are for connection of the measurement jig by SMP cables and oscillograph.By the measurement jig and test method can easily carry out OCuLink interfaces PCIE signal test, operation flexibly, conveniently, and can eliminate with probe directly put measuring tape come test error, improve measuring accuracy.
Description
Technical field
The present invention relates to server testing fields, and in particular to a kind of PCIE signal test based on OCuLink interfaces is controlled
Tool and test method.
Background technology
With the continuous improvement of server board density, the size of component package is less and less on board.OCuLink makees
More and more extensive use is obtained for the connector of a kind of high density, small size.Oculink connectors are high-speed datas of new generation
Signal connector is widely used in the fields such as server, interchanger, storage device and work station, is used for transmission 24G SAS data
Signal.The signal pins density of OCuLink interfaces is higher and is all wrapped, and the PCIE (Peripheral of OCuLink interfaces
Component Interface Express buses and interface standard) signal be high speed signal, it is necessary to carry out signal integrity survey
Examination.
For the PCIE signal integrity test of OCuLink interfaces, if can only not use and pop one's head at a high speed by measurement jig
A survey is directly carried out on OCuLink interfaces, still, is surveyed if put with probe directly on OCuLink interfaces, such operation
Can be potentially encountered can not normally touch signal pins or the unstable situation of contact, so as to cause can not normally, accurately into
Row test, testing efficiency and measuring accuracy can not ensure.
For this problem, the present application is a kind of based on the PCIE signal measurement jig of OCuLink interfaces and test side
Method.
The content of the invention
The problem to be solved in the present invention be carry out OCuLink interfaces PCIE signal integrity test when, if with spy
Head directly point, which is surveyed can be potentially encountered, can not normally touch signal pins or the unstable situation of contact, so as to cause can not be just
Often, the problem of accurately being tested.
As shown in Figure 1, test philosophy of the invention is to lead to the PCIE clock signals and data-signal of OCuLink interfaces
It crosses SMP females to extract, other any devices need not be added on signal transmission path, to ensure to draw the authenticity of signal.
The purposes of signal testing gauge in the present invention is for testing, therefore first has to ensure biography of the signal on gauge
It is defeated signal to be had an impact.In order to achieve this, it needs from plate, trace width, cable run distance, resistance requirements etc.
Stringent emulation is carried out, and then makes rational wiring rule.
The wiring rule formulated according to signal simulation requirement carries out Layout wires designs, after the completion of Layout wires designs
It re-packs.
The tests such as impedance, Loss verification is carried out after the completion of re-packing, it is ensured that gauge meets design requirement.
The connection of tested interface and measurement jig is carried out shown in 2 with reference to the accompanying drawings.
The connection of measurement jig and oscillograph is carried out shown in 3 with reference to the accompanying drawings, test can be carried out after the completion of connection.
Specifically, a kind of PCIE signal measurement jig based on OCuLink interfaces is claimed in the application, and feature exists
In the signal testing gauge specifically includes：OCuLink male connectors and SMP female interfaces, wherein, OCuLink male connectors are controlled for testing
The connection of tool and tested interface, SMP females are used for connection of the measurement jig by SMP cables and oscillograph.
PCIE signal measurement jig based on OCuLink interfaces as described above is further characterized in that, which controls
Tool is made of an OCuLink male connector, 5 pairs of PCB traces and 5 pairs of SMP females.
PCIE signal measurement jig based on OCuLink interfaces as described above, is further characterized in that, PCB trace is used for
Signal is led into SMP female interfaces.
PCIE signal measurement jig based on OCuLink interfaces as described above, is further characterized in that, in 5 pairs of PCB traces
One group be difference PCIE reference clock signals, remaining four groups be difference PCIE data-signals.
Specifically, the application also asks a kind of PCIE signal test method based on OCuLink interfaces, which is characterized in that
The test method carries out signal testing using PCIE signal measurement jig as described in claim 1, and specific testing procedure is：
By the connection of tested interface and measurement jig described in claim 1；
Measurement jig described in claim 1 with oscillograph is attached, is tested after the completion of connection.
PCIE signal test method based on OCuLink interfaces as described above is further characterized in that, which controls
Tool is made of an OCuLink male connector, 5 pairs of PCB traces and 5 pairs of SMP females.
PCIE signal test method based on OCuLink interfaces as described above, is further characterized in that, PCB trace is used for
Signal is led into SMP female interfaces.
PCIE signal test method based on OCuLink interfaces as described above, is further characterized in that, in 5 pairs of PCB traces
One group be difference PCIE reference clock signals, remaining four groups be difference PCIE data-signals.
PCIE signal test method based on OCuLink interfaces as described above, is further characterized in that, PCIE signal test
When need simultaneously test clock signal and data-signal.
Description of the drawings
Fig. 1, measurement jig schematic diagram
Fig. 2, measurement jig and tested interface connection diagram
Fig. 3, measurement jig pass through SMP cables and oscillograph connection diagram
Specific embodiment
Clearly to illustrate the realization situation of test method of the present invention, below in conjunction with the accompanying drawings 1, attached drawing 2, attached drawing 3 illustrate
Realize step.It is specific as follows：
OCuLink male connectors and SMP female interfaces are reserved on measurement jig, OCuLink male connectors are used for measurement jig and quilt
The connection of interface is surveyed, SMP females are used for connection of the measurement jig by SMP cables and oscillograph.
As shown in Figure 1, gauge is made of an OCuLink male connector, 5 pairs of PCB traces and 5 pairs of SMP females.OCuLink
Male connector is used for the connection of measurement jig and tested interface；PCB trace is used to signal leading to SMP female interfaces；SMP females are used for
With the connection of SMP cables.
In attached drawing 1, CLK+, CLK- are the PCIE reference clock signals of one group of difference；
TX0+, TX0-, TX1+, TX1-, TX2+, TX2-, TX3+, TX3- are the PCIE data-signals of four groups of difference；It can be with
It is connected by SMP cables with oscillograph, so as to easily carry out PCIE signal integrity test.
Attached drawing 2 is measurement jig and tested interface connection diagram.
Attached drawing 3 is measurement jig and oscillograph connection diagram.
It should be noted that：Needed when PCIE signal is tested simultaneously test clock signal (CLK) and data-signal (TX0,
TX1, TX2 or TX3), the present embodiment is exemplified by testing TX2.
It should be evident that illustrated above is only the specific embodiment of the present invention, for the common skill in this field
For art personnel, without creative efforts, other technical solutions can also be obtained according to above-described embodiment,
And the equivalent variations made in the scope of protection of the invention should all be fallen within the scope of protection of the present invention, and belong to the present invention
The scope of protection.
In conclusion the PCIE signal measurement jig and test method of the present application OCuLink interfaces, are controlled in test
OCuLink male connectors and SMP female interfaces are reserved on tool, OCuLink male connectors are for the connection of measurement jig and tested interface, SMP
Female is used for connection of the measurement jig by SMP cables and oscillograph.It can be convenient by the measurement jig and test method
The PCIE signal test of OCuLink interfaces is carried out, the gauge and test method can realize the company by SMP cables and oscillograph
Connect, operation flexibly, conveniently, and can eliminate with probe directly put measuring tape come test error, improve measuring accuracy and survey
Try efficiency.
Claims (9)
1. a kind of PCIE signal measurement jig based on OCuLink interfaces, which is characterized in that the signal testing gauge specifically wraps
It includes：OCuLink male connectors and SMP female interfaces, wherein, OCuLink male connectors are for the connection of measurement jig and tested interface, SMP
Female is used for connection of the measurement jig by SMP cables and oscillograph.
2. the PCIE signal measurement jig based on OCuLink interfaces as described in claim 1, is further characterized in that, the signal
Measurement jig is made of an OCuLink male connector, 5 pairs of PCB traces and 5 pairs of SMP females.
3. the PCIE signal measurement jig based on OCuLink interfaces as claimed in claim 2, is further characterized in that, PCB trace
For signal to be led to SMP female interfaces.
4. the PCIE signal measurement jig based on OCuLink interfaces as claimed in claim 3, is further characterized in that, 5 couples of PCB
Have in cabling one group be difference PCIE reference clock signals, remaining four groups be difference PCIE data-signals.
5. a kind of PCIE signal test method based on OCuLink interfaces, which is characterized in that the test method uses right such as will
The PCIE signal measurement jig described in 1 is asked to carry out signal testing, specific testing procedure is：
By the connection of tested interface and measurement jig described in claim 1；
Measurement jig described in claim 1 with oscillograph is attached, is tested after the completion of connection.
6. the PCIE signal test method based on OCuLink interfaces as claimed in claim 5, is further characterized in that, the signal
Measurement jig is made of an OCuLink male connector, 5 pairs of PCB traces and 5 pairs of SMP females.
7. the PCIE signal test method based on OCuLink interfaces as claimed in claim 6, is further characterized in that, PCB trace
For signal to be led to SMP female interfaces.
8. the PCIE signal test method based on OCuLink interfaces as claimed in claim 7, is further characterized in that, 5 couples of PCB
Have in cabling one group be difference PCIE reference clock signals, remaining four groups be difference PCIE data-signals.
9. the PCIE signal test method based on OCuLink interfaces as claimed in claim 8, is further characterized in that, PCIE letters
Number test when need simultaneously test clock signal and data-signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711243801.0A CN108089955A (en) | 2017-11-30 | 2017-11-30 | A kind of PCIE signal measurement jig and test method based on OCuLink interfaces |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711243801.0A CN108089955A (en) | 2017-11-30 | 2017-11-30 | A kind of PCIE signal measurement jig and test method based on OCuLink interfaces |
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| CN108089955A true CN108089955A (en) | 2018-05-29 |
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| CN201711243801.0A Pending CN108089955A (en) | 2017-11-30 | 2017-11-30 | A kind of PCIE signal measurement jig and test method based on OCuLink interfaces |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109375002A (en) * | 2018-09-21 | 2019-02-22 | 郑州云海信息技术有限公司 | A kind of M.2 interface signal test equipment |
| CN109884552A (en) * | 2019-03-20 | 2019-06-14 | 浪潮商用机器有限公司 | Power supply test method and system |
| CN111579825A (en) * | 2020-05-28 | 2020-08-25 | 浪潮电子信息产业股份有限公司 | PCIE signal test fixture and test cable auxiliary supporting tool thereof |
| CN112380103A (en) * | 2020-11-11 | 2021-02-19 | 深圳市广和通无线股份有限公司 | System log acquisition device, system, method and storage medium |
| CN113281583A (en) * | 2021-04-21 | 2021-08-20 | 深圳市精泰达科技有限公司 | PCIe test fixture and PCIe test method |
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| CN109375002A (en) * | 2018-09-21 | 2019-02-22 | 郑州云海信息技术有限公司 | A kind of M.2 interface signal test equipment |
| CN109884552A (en) * | 2019-03-20 | 2019-06-14 | 浪潮商用机器有限公司 | Power supply test method and system |
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| CN113281583A (en) * | 2021-04-21 | 2021-08-20 | 深圳市精泰达科技有限公司 | PCIe test fixture and PCIe test method |
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Application publication date: 20180529 |
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