CN108039318B - Method for manufacturing semiconductor chip capable of resisting illumination interference - Google Patents
Method for manufacturing semiconductor chip capable of resisting illumination interference Download PDFInfo
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- CN108039318B CN108039318B CN201711401434.2A CN201711401434A CN108039318B CN 108039318 B CN108039318 B CN 108039318B CN 201711401434 A CN201711401434 A CN 201711401434A CN 108039318 B CN108039318 B CN 108039318B
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Abstract
The invention provides a manufacturing method of a semiconductor chip capable of resisting illumination interference, which comprises the following steps: forming a composite dielectric layer on the surface of a silicon substrate, wherein the composite dielectric layer comprises a first dielectric layer and a second dielectric layer with different etching selection ratios; forming photoresist on the surface of the composite dielectric layer, and removing the photoresist in the metal wiring area through photoetching; performing first etching treatment on the first dielectric layer of the composite dielectric layer by using the photoresist to remove the first dielectric layer of the metal wiring area; performing second etching treatment on the second dielectric layer to remove the first dielectric layer in the metal wiring area and enable the composite dielectric layer to form a T-shaped step; and growing a metal layer by using the T-shaped step, wherein the metal layer which is positioned on the T-shaped step and directly covers the silicon substrate is used as a metal routing, and the metal layer which covers the surface of the T-shaped step is used as a light shielding layer.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor chip manufacturing, in particular to a manufacturing method of a semiconductor chip capable of resisting illumination interference.
[ background of the invention ]
Some semiconductor chips are applied to the occasions irradiated by light, and the irradiation of the light to the chips causes the abnormality of the operation of the chips. The LED lamp is characterized in that a plurality of LED chips and the LED driving control chips are packaged in transparent epoxy resin together, the driving control chips of the LED lamp are not packaged by opaque resin, the leakage current of the driving control chips is increased in the illumination environment, so that the function of part of the control chips is abnormal, and the abnormal work of the LED lamp is shown due to the increase of the leakage current.
In order to solve this problem, there is currently a method of: the passivation layer is etched by growing a layer of metal, such as aluminum (Al), on the surface of the passivation layer, and then lithographically etching the layer of metal. The light is shielded by means of the light-impermeable metal layer on the surface of the passivation layer. In order to reduce the risk of short circuit between the metal wire of the bonding pad area wire bonding and the light-shielding metal on the surface layer of the passivation layer, an etching area smaller than the light-shielding metal layer needs to be arranged in the etching area of the passivation layer.
Although this approach can solve the influence of light irradiation on the chip, there are some obvious drawbacks: for the metal on the surface of the passivation layer, in order to make the etched window of the passivation layer smaller than that of the shading metal layer, separate steps of photoetching, etching and photoresist removal are required, and the process is complex; in addition, the manufacturing cost is higher due to the addition of metal on the surface of the passivation layer and a series of processes.
In view of the above, it is desirable to provide a method for fabricating a semiconductor chip with resistance to light interference, so as to solve the above-mentioned problems in the prior art.
[ summary of the invention ]
One of the objectives of the present invention is to provide a method for fabricating a semiconductor chip that is resistant to light interference.
The invention provides a manufacturing method of a semiconductor chip capable of resisting illumination interference, which comprises the following steps: forming a composite dielectric layer on the surface of a silicon substrate, wherein the composite dielectric layer comprises a first dielectric layer and a second dielectric layer with different etching selection ratios; forming photoresist on the surface of the composite dielectric layer, and removing the photoresist in the metal wiring area through photoetching; performing first etching treatment on the first dielectric layer of the composite dielectric layer by using the photoresist to remove the first dielectric layer of the metal wiring area; performing second etching treatment on the second dielectric layer to remove the first dielectric layer in the metal wiring area and enable the composite dielectric layer to form a T-shaped step; and growing a metal layer by using the T-shaped step, wherein the metal layer which is positioned on the T-shaped step and directly covers the silicon substrate is used as a metal routing, and the metal layer which covers the surface of the T-shaped step is used as a light shielding layer.
As an improvement of the method for manufacturing a semiconductor chip resistant to light interference provided in the present invention, in a preferred embodiment, the silicon substrate is a silicon substrate of a device on which a chip has been formed.
As an improvement of the manufacturing method of the semiconductor chip with anti-light interference provided by the present invention, in a preferred embodiment, the first dielectric layer is a silicon dioxide layer, and the second dielectric layer is a silicon nitride layer, and the silicon nitride layer and the silicon dioxide layer are sequentially formed on the surface of the silicon substrate.
As an improvement of the manufacturing method of the semiconductor chip with anti-light interference provided by the present invention, in a preferred embodiment, the first dielectric layer is a silicon nitride layer, and the second dielectric layer is a silicon dioxide layer, and the silicon dioxide layer and the silicon nitride layer are sequentially formed on the surface of the silicon substrate.
As an improvement of the manufacturing method of the anti-light interference semiconductor chip provided by the present invention, in a preferred embodiment, the first etching is performed on the first dielectric layer by wet etching or dry etching.
As an improvement of the manufacturing method of the anti-illumination-interference semiconductor chip provided by the present invention, in a preferred embodiment, the second etching is performed on the second dielectric layer by wet etching or isotropic dry etching.
As an improvement of the manufacturing method of the semiconductor chip with anti-light interference provided by the present invention, in a preferred embodiment, the lateral etching amount of the second dielectric layer in the second etching process is greater than the lateral etching amount of the first dielectric layer.
As an improvement of the method for manufacturing a semiconductor chip resistant to light interference provided in the present invention, in a preferred embodiment, the method further includes: and removing the photoresist on the surface of the T-shaped step before the metal layer grows.
As an improvement of the method for manufacturing a semiconductor chip with resistance to light interference provided by the present invention, in a preferred embodiment, the metal layer is an aluminum layer, an aluminum-silicon-copper alloy layer, or other non-light-transmissive metal layer.
As an improvement of the manufacturing method of the semiconductor chip with anti-light interference provided by the present invention, in a preferred embodiment, the metal layer is formed on the surface of the T-shaped step and the surface of the metal routing area of the silicon substrate by a sputtering process.
Compared with the prior art, the manufacturing method of the anti-illumination-interference semiconductor chip mainly utilizes the difference of transverse corrosion amount of the composite dielectric layer during etching to form the T-shaped step, then the metal layer is grown, the shading metal layer area and the metal wiring layer area are automatically separated by utilizing the T-shaped step, and the metal layer on the surface of the T-shaped step can be used as the shading metal layer of the semiconductor chip.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained by those skilled in the art without inventive efforts based on these drawings:
FIG. 1 is a schematic flow chart illustrating a method for fabricating a semiconductor chip with anti-light interference according to an embodiment of the present invention;
fig. 2 to 7 are schematic diagrams of the steps of the method for manufacturing the semiconductor chip of fig. 1.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a method for manufacturing a semiconductor chip with light interference resistance, which aims to solve a series of problems caused by the fact that a bare metal layer is adopted to shield the surface of the semiconductor chip in the light interference environment in the prior art.
Please refer to fig. 1, which is a flowchart illustrating a method for fabricating a semiconductor chip with anti-illumination interference according to an embodiment of the present invention. Specifically, the method for manufacturing the semiconductor chip resistant to illumination interference mainly comprises the following steps:
step S1, forming a composite dielectric layer on the surface of the silicon substrate, wherein the composite dielectric layer comprises a first dielectric layer and a second dielectric layer with different etching selection ratios;
specifically, referring to fig. 2, the silicon substrate may be a silicon substrate of a device in which a chip has been formed, that is, the silicon substrate has been fabricated with an internal circuit of the chip; in this embodiment, the composite dielectric layer may include two film layers with different etching selectivity ratios, such as a first dielectric layer and a second dielectric layer. The first dielectric layer and the second dielectric layer may be formed by chemical vapor deposition, for example, the second dielectric layer is formed on the surface of the silicon substrate first, and then the first dielectric layer is formed on the surface of the second dielectric layer.
As shown in fig. 2, the first dielectric layer may be a silicon dioxide layer, and the second dielectric layer may be a silicon nitride layer, and the silicon nitride layer and the silicon dioxide layer are sequentially formed on the surface of the silicon substrate. Alternatively, the materials of the first dielectric layer and the second dielectric layer may be reversed, that is, the second dielectric layer on the surface of the silicon substrate may be a silicon dioxide layer, and the first dielectric layer on the surface of the second dielectric layer may be a silicon nitride layer.
In other alternative embodiments, the first dielectric layer and the second dielectric layer may be film layers made of other materials, but they need to have different etching selection ratios when performing dry etching or wet etching. That is, when one of the first dielectric layer and the second dielectric layer is etched, the other film layer is not substantially affected.
Step S2, forming photoresist on the surface of the composite dielectric layer, and removing the photoresist in the metal wiring area through photoetching;
specifically, referring to fig. 3, in step S2, a layer of photoresist is coated on the surface of the first dielectric layer, and then the photoresist is subjected to a photolithography process by using a photolithography technique to remove the photoresist in the pre-designed metal routing area, so that the composite dielectric layer in the metal routing area is exposed.
Step S3, carrying out first etching treatment on the first dielectric layer of the composite dielectric layer by using the photoresist;
specifically, referring to fig. 4, after the photoresist in the metal trace area is removed, a first etching process may be performed on the first dielectric layer through the photoresist, where the first etching process may adopt wet etching or dry etching, and in a specific embodiment, the first dielectric layer etching does not have a special requirement on the lateral etching amount, so that after the etching, the first dielectric layer in the metal trace area is removed. It should be understood that, in the process of the first etching treatment, because the first dielectric layer and the second dielectric layer have different etching selection ratios, the second dielectric layer below the first dielectric layer is not affected in the process of etching the first dielectric layer in the metal trace area. As shown in fig. 4, the silicon dioxide layer is etched away, but the underlying silicon nitride layer remains intact throughout the film.
Step 4, performing a second etching process on a second dielectric layer below the first dielectric layer by using the photoresist to form a T-shaped step on the composite dielectric layer;
specifically, referring to fig. 5, the second dielectric layer may be subjected to the second etching process by wet etching or isotropic dry etching; because the first dielectric layer and the second dielectric layer have different etching selection ratios, when the second dielectric layer is subjected to wet etching or isotropic dry etching, the transverse etching amount of the second dielectric layer in the second etching process is larger than that of the first dielectric layer, so that the size of the second dielectric layer reserved in the non-metal routing area is smaller than that of the first dielectric layer above the second dielectric layer, and a T-shaped step is formed in the composite dielectric layer. As shown in fig. 5, the size of the nitride layer is smaller than the size of the silicon dioxide layer above the nitride layer, so that the silicon dioxide layer and the silicon nitride layer form a cross-sectional T-shaped step structure, i.e. the T-shaped step as described above. Because the second dielectric layer of the metal routing area of the silicon substrate is removed, the metal routing area is exposed, and metal can be directly grown in a subsequent process to form a metal routing layer.
Step S5, removing the photoresist on the surface of the T-shaped step;
specifically, referring to fig. 6, after the T-shaped step is formed, the photoresist on the surface of the T-shaped step may be removed by a photoresist stripping process, so that the first dielectric layer of the T-shaped step is exposed.
Step S6, growing a metal layer by using the T-shaped step, wherein the metal layer which is directly positioned on the T-shaped step and covers the silicon substrate is used as a metal routing, and the metal layer which covers the surface of the T-shaped step is used as a light shielding layer;
specifically, referring to fig. 7, after the photoresist on the surface of the T-shaped step is removed, a metal layer may be formed on the surface of the silicon substrate (i.e., the surface of the metal routing area) between the surface of the T-shaped step and the T-shaped step by sputtering or other metal growth processes. The metal layer may be specifically an aluminum layer, an aluminum-silicon-copper alloy layer or other non-light-transmitting metal layers. The metal layer on the surface of the silicon substrate can be used as a metal wire of the semiconductor chip, and the metal layer on the surface of the T-shaped step can be used as a light shielding layer. The light shielding layer can shield surrounding optical signals so as to prevent the semiconductor chip from being applied to a light environment, and the optical signals can influence the internal circuit of the semiconductor chip to generate optical current or cause the problems of electric leakage and the like.
Compared with the prior art, the manufacturing method of the anti-illumination-interference semiconductor chip mainly utilizes the difference of transverse corrosion amount of the composite dielectric layer during etching to form the T-shaped step, then the metal layer is grown, the shading metal layer area and the metal wiring layer area are automatically separated by utilizing the T-shaped step, and the metal layer on the surface of the T-shaped step can be used as the shading metal layer of the semiconductor chip.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (4)
1. A method for manufacturing a semiconductor chip resistant to illumination interference is characterized by comprising the following steps:
forming a composite dielectric layer on the surface of a silicon substrate, wherein the composite dielectric layer comprises a first dielectric layer and a second dielectric layer with different etching selection ratios;
forming photoresist on the surface of the composite dielectric layer, and removing the photoresist in the metal wiring area through photoetching; performing first etching treatment on the first dielectric layer of the composite dielectric layer by using the photoresist to remove the first dielectric layer of the metal wiring area;
performing second etching treatment on the second dielectric layer to remove the first dielectric layer in the metal wiring area and enable the composite dielectric layer to form a T-shaped step;
growing a metal layer by utilizing the T-shaped step, wherein the metal layer which is positioned on the T-shaped step and directly covers the silicon substrate is used as a metal routing, and the metal layer which covers the surface of the T-shaped step is used as a light shielding layer; the transverse etching amount of the second dielectric layer in the second etching process is larger than that of the first dielectric layer; removing the photoresist on the surface of the T-shaped step before the metal layer grows; the metal layer is an aluminum layer, an aluminum-silicon-copper alloy layer or other non-light-transmitting metal layers;
the first dielectric layer is a silicon dioxide layer, the second dielectric layer is a silicon nitride layer, and the silicon nitride layer and the silicon dioxide layer are sequentially formed on the surface of the silicon substrate;
the metal layer is formed on the surface of the T-shaped step and the surface of the metal routing area of the silicon substrate by adopting a sputtering process.
2. The method of claim 1, wherein the silicon substrate is a silicon substrate of a device that has been formed into a chip.
3. The method according to claim 1, wherein the first etching is performed on the first dielectric layer by wet etching or dry etching.
4. The method of claim 1, wherein the second etching is performed on the second dielectric layer by wet etching or isotropic dry etching.
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| CN108039318B true CN108039318B (en) | 2020-10-16 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4729967A (en) * | 1987-04-09 | 1988-03-08 | Gte Laboratories Incorporated | Method of fabricating a junction field effect transistor |
| CN101231948A (en) * | 2008-03-31 | 2008-07-30 | 天津工业大学 | Method for stripping electrode |
| CN103187323A (en) * | 2011-12-28 | 2013-07-03 | 北大方正集团有限公司 | Semiconductor chip and thickening manufacture method of pressure welding block metal layer of semiconductor chip |
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- 2017-12-21 CN CN201711401434.2A patent/CN108039318B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4729967A (en) * | 1987-04-09 | 1988-03-08 | Gte Laboratories Incorporated | Method of fabricating a junction field effect transistor |
| CN101231948A (en) * | 2008-03-31 | 2008-07-30 | 天津工业大学 | Method for stripping electrode |
| CN103187323A (en) * | 2011-12-28 | 2013-07-03 | 北大方正集团有限公司 | Semiconductor chip and thickening manufacture method of pressure welding block metal layer of semiconductor chip |
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