CN108038260B - HKMG CMP process model test structure and modeling method - Google Patents
HKMG CMP process model test structure and modeling method Download PDFInfo
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- CN108038260B CN108038260B CN201711102832.4A CN201711102832A CN108038260B CN 108038260 B CN108038260 B CN 108038260B CN 201711102832 A CN201711102832 A CN 201711102832A CN 108038260 B CN108038260 B CN 108038260B
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Abstract
The invention discloses a HKMG CMP process model test structure, which comprises a final test pattern array formed by arranging final test pattern units; the final test pattern unit comprises a grid test pattern array and a measuring substrate pattern array; the grid test pattern array is formed by arranging HKMG test patterns corresponding to various HKMG formed on various front-mounted topography surfaces; the measurement substrate pattern array is formed by arranging thickness measurement substrate patterns for measuring the HKMG thickness, the interlayer film thickness and the polysilicon thickness formed on the surfaces of various pre-topographies. The invention also discloses a modeling method of the HKMG CMP process model. The method can ensure the accuracy of the HKMG CMP process model and reduce the modeling period.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a Chemical Mechanical Polishing (CMP) process model test structure of a high dielectric constant grid (HKMG) and a modeling method of the HKMG CMP process model.
Background
As the semiconductor technology node moves into 45 nm and below, semiconductor fabrication plants have introduced high dielectric constant metal gate (HKMG) technology, which includes multiple chemical mechanical polishing processes, in order to improve transistor performance. With the introduction of chemical mechanical polishing processes, manufacturability checking associated therewith becomes indispensable.
The establishment of the model of the chemical mechanical polishing process is one of the most important loops in the manufacturability inspection of the chemical mechanical polishing process. As shown in fig. 1, it is a flow chart of the existing CMP process model establishment, and the flow includes the following steps:
designing a Test Pattern (Test Pattern) of a chemical mechanical polishing process model;
manufacturing a chemical mechanical polishing process model test photomask;
testing wafer processing by using the chemical mechanical polishing process model;
collecting test data of a chemical mechanical polishing process model;
calibrating a chemical mechanical polishing process model;
and (5) verifying a chemical mechanical polishing process model.
That is, through the design of the test pattern, the photomask corresponding to the test pattern is manufactured, the wafer is processed according to the photomask, various test patterns are formed in the wafer processing, corresponding data are collected in each step of the wafer processing or after each step is completed, the model is calibrated according to the collected data, and finally the model is verified. And the verified chemical mechanical grinding process model is used for performing manufacturable detection on the product layout before the product flow of the customer, so that the layout weak part related to the chemical mechanical grinding process in the product layout of the customer can be found in time. The detection result is fed back to the customer for correction, and the product yield can be greatly improved.
In the CMP process modeling, the design of the test pattern plays a crucial role in ensuring the accuracy and precision of the model.
Disclosure of Invention
The invention aims to provide a HKMG CMP process model test structure which can ensure the manufacturability detection accuracy of the HKMG CMP process. The invention also provides a modeling method of the HKMG CMP process model.
In order to solve the technical problem, the HKMG CMP process model test structure provided by the invention comprises a final test pattern array formed by arranging final test pattern units; the final test pattern unit comprises a grid test pattern array and a measuring substrate pattern array.
The grid test pattern array is formed by arranging HKMG test patterns corresponding to various HKMG formed on various front-mounted topography surfaces;
the substrate pattern array is formed by arranging thickness measurement substrate patterns for measuring the HKMG thickness, the interlayer film thickness and the polysilicon thickness formed on the surfaces of various pre-topographies.
In a further refinement, the pre-topographic surface comprises: the surface of the silicon substrate is formed on the surface of the shallow trench isolation medium in the silicon substrate.
Categories of HKMG include: HKMG for P-type transistors and HKMG for N-type transistors.
In a further improvement, the HKMG test pattern includes 9 patterns, which are respectively:
the first HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of P-type transistors simultaneously formed on the surface of a continuous silicon-based substrate.
The second HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of N-type transistors simultaneously formed on the surface of a continuous silicon-based substrate.
The third HKMG test pattern is a test pattern formed by alternately arranging HKMG of a plurality of N-type transistors and HKMG of P-type transistors simultaneously formed on the surface of a continuous silicon-based substrate.
A fourth HKMG test pattern is formed by arranging HKMG of a plurality of P-type transistors formed on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region;
the fifth HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of N-type transistors formed on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region.
The sixth HKMG test pattern is a test pattern formed by alternately arranging HKMG of a plurality of N-type transistors and HKMG of P-type transistors formed on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region.
The seventh HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium.
The eighth HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of N-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium.
The ninth HKMG test pattern is a test pattern formed by alternately arranging HKMGs of a plurality of N-type transistors and HKMGs of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium.
In a further improvement, the HKMG of the corresponding N-type transistor and the HKMG of the corresponding P-type transistor in the HKMG test pattern are both in a strip shape.
In a further improvement, in the mixed region of the silicon-based substrate and the shallow trench isolation medium, the silicon-based substrate is divided into a plurality of independent division structures by the shallow trench isolation medium, and the HKMG in the fourth HKMG test pattern, the fifth HKMG test pattern and the sixth HKMG test pattern forms a surface of the corresponding independent division structure.
In a further improvement, the thickness measurement substrate pattern corresponding to the measurement substrate pattern array includes 8 patterns, respectively:
the first thickness measurement substrate pattern is a silicon-based substrate pattern for measuring the HKMG thickness of the P-type transistor.
The second thickness measurement substrate pattern is a silicon-based substrate pattern measuring the HKMG thickness of the N-type transistor.
The third thickness measurement substrate pattern is a silicon-based substrate pattern for measuring the thickness of an interlayer film.
The fourth thickness measurement substrate pattern is a silicon-based substrate pattern for measuring the thickness of the polysilicon.
The fifth thickness measurement substrate pattern is a shallow trench isolation dielectric substrate pattern for measuring the HKMG thickness of the P-type transistor.
The sixth thickness measurement substrate pattern is a shallow trench isolation dielectric pattern for measuring the HKMG thickness of the N-type transistor.
The seventh thickness measurement substrate pattern is a shallow trench isolation dielectric pattern for measuring the thickness of the interlayer film.
The eighth thickness measurement substrate pattern is a shallow trench isolation dielectric pattern for measuring the thickness of the polysilicon.
In order to solve the technical problem, the modeling method of the HKMG CMP process model provided by the invention comprises the following steps:
designing a test structure, wherein the test structure comprises a final test pattern array formed by arranging final test pattern units; the final test pattern unit comprises a grid test pattern array and a measuring substrate pattern array.
The grid test pattern array is formed by arranging HKMG test patterns corresponding to various HKMG formed on various front-mounted topographic surfaces.
The substrate pattern array is formed by arranging thickness measurement substrate patterns for measuring the HKMG thickness, the interlayer film thickness and the polysilicon thickness formed on the surfaces of various pre-topographies.
Step two, processing and manufacturing a test wafer according to the designed test structure, wherein the wafer consists of a silicon-based substrate, and the manufacturing process comprises the following steps:
and step 21, forming shallow trenches in the selected area of the silicon-based substrate.
And 22, depositing a shallow trench isolation medium.
And step 23, carrying out chemical mechanical polishing on the shallow trench isolation medium.
And step 24, forming gate polysilicon.
And 25, growing silicon germanium in the active region of the P-type transistor.
Step 26, a silicon nitride layer is deposited.
And 27, depositing an interlayer medium.
And 28, carrying out chemical mechanical polishing on the interlayer medium.
And step 29, removing the grid polysilicon of the P-type transistor, and depositing a high dielectric constant dielectric layer, an isolation metal layer, a work function metal and metal aluminum which form the HKMG.
Step 210, performing a chemical mechanical polishing of the metallic aluminum of the HKMG of the P-type transistor.
And step 211, removing the grid polysilicon of the N-type transistor, and depositing a high dielectric constant dielectric layer, an isolation metal layer, a work function metal and metal aluminum which form the HKMG.
Step 212, metal aluminum chemical mechanical polishing of HKMG of the N-type transistor is performed.
And step three, carrying out model data collection on the test wafer and carrying out modeling on a CMP process model.
The further improvement is that the third step comprises the following steps:
and 31, acquiring the front surface topography.
And step 32, establishing a deposition model of the interlayer medium.
And step 33, establishing a grinding model of the interlayer medium.
And step 34, establishing a deposition model of the metallic aluminum of the HKMG of the P-type transistor.
And step 35, establishing a grinding model of the metallic aluminum of the HKMG of the P-type transistor.
And step 36, establishing a deposition model of the metallic aluminum of the HKMG of the N-type transistor.
And step 37, establishing a grinding model of the metallic aluminum of the HKMG of the N-type transistor.
In a further improvement, in step 31, a pre-surface topography is obtained by directly measuring the wafer after the step 23 is completed;
alternatively, the step of acquiring the front surface topography of step 31 is: the method comprises the steps of firstly predicting according to a chemical mechanical polishing model of the shallow trench isolation medium, and then adjusting the surface of the shallow trench in the global or local area to obtain the appearance of the preposed surface.
A further improvement is that only steps 36 and 37 are performed among steps 34, 35, 36 and 37 to save two steps.
In a further refinement, the pre-topographic surface comprises: the surface of the silicon substrate is formed on the surface of the shallow trench isolation medium in the silicon substrate.
Categories of HKMG include: HKMG for P-type transistors and HKMG for N-type transistors.
In a further improvement, the HKMG test pattern includes 9 patterns, which are respectively:
the first HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of P-type transistors simultaneously formed on the surface of a continuous silicon-based substrate.
The second HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of N-type transistors simultaneously formed on the surface of a continuous silicon-based substrate.
The third HKMG test pattern is a test pattern formed by alternately arranging HKMG of a plurality of N-type transistors and HKMG of P-type transistors simultaneously formed on the surface of a continuous silicon-based substrate.
And the fourth HKMG test pattern is formed by arranging HKMG of a plurality of P-type transistors formed on the surface of the silicon-based substrate and the shallow trench isolation medium mixed region.
The fifth HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of N-type transistors formed on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region.
The sixth HKMG test pattern is a test pattern formed by alternately arranging HKMG of a plurality of N-type transistors and HKMG of P-type transistors formed on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region.
The seventh HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium.
The eighth HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of N-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium.
The ninth HKMG test pattern is a test pattern formed by alternately arranging HKMGs of a plurality of N-type transistors and HKMGs of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium.
In a further improvement, the HKMG of the corresponding N-type transistor and the HKMG of the corresponding P-type transistor in the HKMG test pattern are both in a strip shape.
In a further improvement, in the mixed region of the silicon-based substrate and the shallow trench isolation medium, the silicon-based substrate is divided into a plurality of independent division structures by the shallow trench isolation medium, and the HKMG in the fourth HKMG test pattern, the fifth HKMG test pattern and the sixth HKMG test pattern forms a surface of the corresponding independent division structure.
In a further improvement, the thickness measurement substrate pattern corresponding to the measurement substrate pattern array includes 8 patterns, respectively:
the first thickness measurement substrate pattern is a silicon-based substrate pattern for measuring the HKMG thickness of the P-type transistor.
The second thickness measurement substrate pattern is a silicon-based substrate pattern measuring the HKMG thickness of the N-type transistor.
The third thickness measurement substrate pattern is a silicon-based substrate pattern for measuring the thickness of an interlayer film.
The fourth thickness measurement substrate pattern is a silicon-based substrate pattern for measuring the thickness of the polysilicon.
The fifth thickness measurement substrate pattern is a shallow trench isolation dielectric substrate pattern for measuring the HKMG thickness of the P-type transistor.
The sixth thickness measurement substrate pattern is a shallow trench isolation dielectric pattern for measuring the HKMG thickness of the N-type transistor.
The seventh thickness measurement substrate pattern is a shallow trench isolation dielectric pattern for measuring the thickness of the interlayer film.
The eighth thickness measurement substrate pattern is a shallow trench isolation dielectric pattern for measuring the thickness of the polysilicon.
The HKMG CMP process model test structure is combined with an actual manufacturing process, and HKMG test patterns and thickness measurement substrate patterns which reflect various pre-shaped surface appearances and output in various grinding processes are introduced into the HKMG process model test structure, so that the measurement result obtained based on the test pattern structure can accurately reflect the change trend of the grinding pre-shaped surface appearance and the output in each HKMG CMP grinding process along with the change of the geometric characteristics of the test pattern, the accuracy of the model can be ensured, namely the accuracy of the HKMG CMP process manufacturability detection can be ensured; in addition, the invention can obtain the grinding output of various graph structures after the P-type transistor HKMG CMP through direct measurement, thereby omitting two model establishing processes of the deposition of the metallic aluminum of the HKMG of the P-type transistor and the grinding of the metallic aluminum of the HKMG of the P-type transistor, and reducing the modeling period.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a flow chart of a prior art CMP process modeling;
FIG. 2 is a layout diagram of the final test pattern unit of the HKMG CMP process model test structure according to the embodiment of the present invention;
FIG. 3 is a block diagram of a first HKMG test pattern according to an embodiment of the present invention;
FIG. 4 is a block diagram of a second HKMG test pattern in accordance with an embodiment of the present invention;
FIG. 5 is a block diagram of a third HKMG test pattern in accordance with an embodiment of the present invention;
FIG. 6 is a block diagram of a fourth HKMG test pattern in accordance with an embodiment of the present invention;
FIG. 7 is a block diagram of a fifth HKMG test pattern in accordance with the embodiment of the present invention;
FIG. 8 is a block diagram of a sixth HKMG test pattern in accordance with the embodiment of the present invention;
FIG. 9 is a block diagram of a seventh HKMG test pattern in accordance with the embodiment of the present invention;
FIG. 10 is a block diagram of an eighth HKMG test pattern in accordance with the embodiment of the present invention;
FIG. 11 is a block diagram of a ninth HKMG test pattern in accordance with the embodiment of the present invention;
FIGS. 3A-3H are cross-sectional views of a first HKMG test pattern according to an embodiment of the present invention at various steps in the manufacturing process of an HKMG device;
FIGS. 4A-4H are cross-sectional views of a second HKMG test pattern according to an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
FIGS. 5A-5H are cross-sectional views of a third HKMG test pattern according to an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
6A-6H are cross-sectional views of a fourth HKMG test pattern according to an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
FIGS. 7A-7H are cross-sectional views of a fifth HKMG test pattern according to an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
8A-8H are cross-sectional views of a sixth HKMG test pattern of an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
FIGS. 9A-9H are cross-sectional views of a seventh HKMG test pattern according to an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
10A-10H are cross-sectional views of an eighth HKMG test pattern according to an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
11A-11H are cross-sectional views of a ninth HKMG test pattern according to an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
12A-12H are cross-sectional views of a first thickness measurement substrate pattern at various steps in the manufacturing process of the HKMG device according to an embodiment of the present invention;
13A-13H are cross-sectional views at various steps in the manufacturing process of the HKMG device for a second thickness-measuring substrate pattern in accordance with an embodiment of the present invention;
FIGS. 14A-14H are cross-sectional views of a third thickness measurement substrate pattern of an embodiment of the present invention at various steps in the fabrication process of the HKMG device;
FIGS. 15A-15H are cross-sectional views of a fourth thickness measurement substrate pattern of an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
FIGS. 16A-16H are cross-sectional views of a fifth thickness measurement substrate pattern of an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
FIGS. 17A-17H are cross-sectional views of a sixth thickness measurement substrate pattern of an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
FIGS. 18A-18H are cross-sectional views of a seventh thickness measurement substrate pattern of an embodiment of the present invention at various steps in the manufacturing process of the HKMG device;
fig. 19A-19H are cross-sectional views at various steps in the manufacturing process of an HKMG device for an eighth thickness-measuring substrate pattern in accordance with an embodiment of the present invention.
Detailed Description
FIG. 2 shows a layout diagram of a final test pattern unit 1 of the HKMG CMP process model test structure according to the embodiment of the present invention; the HKMG CMP process model test structure comprises a final test pattern array formed by arranging final test pattern units 1; the final test pattern unit 1 includes a gate test pattern array 2 and a metrology substrate pattern array 3.
The grid test pattern array 2 is formed by arranging HKMG test patterns corresponding to various HKMG formed on various front topographic surfaces.
The measurement substrate pattern array 3 is formed by arranging thickness measurement substrate patterns for measuring the HKMG thickness, the interlayer film thickness and the polysilicon thickness formed on the surfaces of various pre-topographies.
In an embodiment of the present invention, the front topographic surface includes: the surface of the silicon substrate 201, the surface of the shallow trench isolation medium 202 formed in the silicon substrate 201.
Categories of HKMG include: HKMG203 for P-type transistors and HKMG204 for N-type transistors.
FIG. 3 to FIG. 11 are structural diagrams of 9 HKMG test patterns according to the embodiment of the present invention; the 9 structures of the HKMG test pattern are respectively as follows:
as shown in fig. 3, the first HKMG test pattern 101 is a test pattern formed by arranging HKMG203 of a plurality of P-type transistors simultaneously formed on the surface of the continuous silicon-based substrate 201. In the embodiment of the invention, the HKMG203 of the P-type transistor is strip-shaped.
As shown in fig. 4, the second HKMG test pattern 102 is a test pattern formed by arranging HKMG204 of a plurality of N-type transistors simultaneously formed on the surface of the continuous silicon-based substrate 201.
In the embodiment of the invention, the HKMG204 of the N-type transistor is bar-shaped.
As shown in fig. 5, the third HKMG test pattern 103 is a test pattern formed by alternately arranging HKMGs 204 of a plurality of N-type transistors and HKMGs 203 of P-type transistors simultaneously formed on the surface of the continuous silicon-based substrate 201.
As shown in fig. 6, the fourth HKMG test pattern 104 is a test pattern formed by arranging HKMG203 of a plurality of P-type transistors formed on the surface of the mixed region of the silicon-based substrate 201 and the shallow trench isolation medium 202. In the embodiment of the invention, in the mixed region of the silicon-based substrate 201 and the shallow trench isolation medium 202, the silicon-based substrate 201 is divided into a plurality of independent division structures by the shallow trench isolation medium 202, and the HKMG in the fourth HKMG test pattern 104, the fifth HKMG test pattern 105 and the sixth HKMG test pattern 106 form the corresponding surfaces of the independent division structures.
As shown in fig. 7, the fifth HKMG test pattern 105 is a test pattern formed by arranging HKMG204 of a plurality of N-type transistors formed on the surface of the mixed region of the silicon-based substrate 201 and the shallow trench isolation medium 202.
As shown in fig. 8, the sixth HKMG test pattern 106 is a test pattern formed by a plurality of HKMG204 of N-type transistors and HKMG203 of P-type transistors alternately arranged on the surface of the mixed region of the silicon-based substrate 201 and the shallow trench isolation medium 202.
As shown in fig. 9, the seventh HKMG test pattern 107 is a test pattern formed by arranging HKMG203 of a plurality of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium 202.
As shown in fig. 10, the eighth HKMG test pattern 108 is a test pattern formed by arranging HKMG204 transistors of a plurality of N-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium 202.
As shown in fig. 11, the ninth HKMG test pattern 109 is a test pattern formed by alternately arranging HKMG204 of a plurality of N-type transistors and HKMG203 of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium 202.
The thickness measurement substrate pattern corresponding to the measurement substrate pattern array 3 comprises 8 thickness measurement substrate patterns, which can refer to a cross-sectional view corresponding to the last step of the manufacturing process of the HKMG device, and the 8 structures are respectively:
as shown in fig. 12H, the first thickness measurement substrate pattern is a silicon-based substrate 201 pattern measuring the thickness of HKMG203 of the P-type transistor.
As shown in fig. 13H, the second thickness measurement substrate pattern is a silicon-based substrate 201 pattern measuring the thickness of HKMG204 of the N-type transistor.
As shown in fig. 14H, the third thickness measurement substrate pattern is a silicon-based substrate 201 pattern for measuring the interlayer film thickness.
As shown in fig. 15H, the fourth thickness measurement substrate pattern is a silicon-based substrate 201 pattern for measuring the thickness of polysilicon.
As shown in fig. 16H, the fifth thickness measurement substrate pattern is a shallow trench isolation dielectric 202 substrate pattern measuring the thickness of HKMG203 of the P-type transistor.
As shown in fig. 17H, the sixth thickness measurement substrate pattern is a shallow trench isolation dielectric 202 pattern for measuring the thickness of HKMG204 of the N-type transistor.
As shown in fig. 18H, the seventh thickness measurement substrate pattern is a shallow trench isolation dielectric 202 pattern for measuring the interlayer film thickness.
As shown in fig. 19H, the eighth thickness measurement substrate pattern is a shallow trench isolation dielectric 202 pattern for measuring the polysilicon thickness.
According to the process shown in fig. 1, the design of the HKMG CMP process model test structure of the embodiment of the present invention belongs to the step of designing the test pattern of the chemical mechanical polishing process model of fig. 1, which is the most critical step, and most importantly, the embodiment of the present invention provides a set of complete test patterns reflecting various pre-topography surfaces and various polishing process outputs, and finally, the accuracy of the manufacturability detection of the HKMG CMP process can be well ensured.
According to the design of the test pattern corresponding to the test structure, the test photomask can be manufactured, and the test wafer can be directly processed and manufactured after the test photomask is manufactured.
The modeling method of the HKMG CMP process model provided by the embodiment of the invention comprises the following steps:
designing a test structure, wherein the test structure comprises a final test pattern array formed by arranging final test pattern units 1; the final test pattern unit 1 includes a gate test pattern array 2 and a metrology substrate pattern array 3.
The grid test pattern array 2 is formed by arranging HKMG test patterns corresponding to various HKMG formed on various front topographic surfaces.
The measurement substrate pattern array 3 is formed by arranging thickness measurement substrate patterns for measuring the HKMG thickness, the interlayer film thickness and the polysilicon thickness formed on the surfaces of various pre-topographies.
In an embodiment of the present invention, the front topographic surface includes: the surface of the silicon substrate 201, the surface of the shallow trench isolation medium 202 formed in the silicon substrate 201.
Categories of HKMG include: HKMG203 for P-type transistors and HKMG204 for N-type transistors.
FIG. 3 to FIG. 11 are structural diagrams of 9 HKMG test patterns according to the embodiment of the present invention; the 9 structures of the HKMG test pattern are respectively as follows:
as shown in fig. 3, the first HKMG test pattern 101 is a test pattern formed by arranging HKMG203 of a plurality of P-type transistors simultaneously formed on the surface of the continuous silicon-based substrate 201. In the embodiment of the invention, the HKMG203 of the P-type transistor is strip-shaped.
As shown in fig. 4, the second HKMG test pattern 102 is a test pattern formed by arranging HKMG204 of a plurality of N-type transistors simultaneously formed on the surface of the continuous silicon-based substrate 201.
In the embodiment of the invention, the HKMG204 of the N-type transistor is bar-shaped.
As shown in fig. 5, the third HKMG test pattern 103 is a test pattern formed by alternately arranging HKMGs 204 of a plurality of N-type transistors and HKMGs 203 of P-type transistors simultaneously formed on the surface of the continuous silicon-based substrate 201.
As shown in fig. 6, the fourth HKMG test pattern 104 is a test pattern formed by arranging HKMG203 of a plurality of P-type transistors formed on the surface of the mixed region of the silicon-based substrate 201 and the shallow trench isolation medium 202. In the embodiment of the invention, in the mixed region of the silicon-based substrate 201 and the shallow trench isolation medium 202, the silicon-based substrate 201 is divided into a plurality of independent division structures by the shallow trench isolation medium 202, and the HKMG in the fourth HKMG test pattern 104, the fifth HKMG test pattern 105 and the sixth HKMG test pattern 106 form the corresponding surfaces of the independent division structures.
As shown in fig. 7, the fifth HKMG test pattern 105 is a test pattern formed by arranging HKMG204 of a plurality of N-type transistors formed on the surface of the mixed region of the silicon-based substrate 201 and the shallow trench isolation medium 202.
As shown in fig. 8, the sixth HKMG test pattern 106 is a test pattern formed by a plurality of HKMG204 of N-type transistors and HKMG203 of P-type transistors alternately arranged on the surface of the mixed region of the silicon-based substrate 201 and the shallow trench isolation medium 202.
As shown in fig. 9, the seventh HKMG test pattern 107 is a test pattern formed by arranging HKMG203 of a plurality of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium 202.
As shown in fig. 10, the eighth HKMG test pattern 108 is a test pattern formed by arranging HKMG204 transistors of a plurality of N-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium 202.
As shown in fig. 11, the ninth HKMG test pattern 109 is a test pattern formed by alternately arranging HKMG204 of a plurality of N-type transistors and HKMG203 of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium 202.
The thickness measurement substrate pattern corresponding to the measurement substrate pattern array 3 comprises 8 thickness measurement substrate patterns, which can refer to a cross-sectional view corresponding to the last step of the manufacturing process of the HKMG device, and the 8 structures are respectively:
as shown in fig. 12H, the first thickness measurement substrate pattern is a silicon-based substrate 201 pattern measuring the thickness of HKMG203 of the P-type transistor.
As shown in fig. 13H, the second thickness measurement substrate pattern is a silicon-based substrate 201 pattern measuring the thickness of HKMG204 of the N-type transistor.
As shown in fig. 14H, the third thickness measurement substrate pattern is a silicon-based substrate 201 pattern for measuring the interlayer film thickness.
As shown in fig. 15H, the fourth thickness measurement substrate pattern is a silicon-based substrate 201 pattern for measuring the thickness of polysilicon.
As shown in fig. 16H, the fifth thickness measurement substrate pattern is a shallow trench isolation dielectric 202 substrate pattern measuring the thickness of HKMG203 of the P-type transistor.
As shown in fig. 17H, the sixth thickness measurement substrate pattern is a shallow trench isolation dielectric 202 pattern for measuring the thickness of HKMG204 of the N-type transistor.
As shown in fig. 18H, the seventh thickness measurement substrate pattern is a shallow trench isolation dielectric 202 pattern for measuring the interlayer film thickness.
As shown in fig. 19H, the eighth thickness measurement substrate pattern is a shallow trench isolation dielectric 202 pattern for measuring the polysilicon thickness.
And step two, processing and manufacturing a test wafer according to the designed test structure, wherein the wafer is composed of the silicon-based substrate 201. Before describing the manufacturing process in detail, the following description is made: in the manufacturing process of the test wafer, the above-described test structure comprising the various test patterns, i.e., the 9 HKMG test patterns corresponding to fig. 3 to 11 and the 8 thickness measurement substrate patterns corresponding to fig. 12H, 13H to 19H, are integrated on the same wafer. The various test patterns may have cross-sectional views of the corresponding steps in the various steps of the wafer fabrication process. The manufacturing process comprises the following steps:
and step 21, forming shallow trenches in selected areas of the silicon-based substrate 201.
Step 23, performing chemical mechanical polishing on the shallow trench isolation medium 202.
Step 24, forming gate polysilicon 302. Fig. 3A, 4A, through 19A correspond to cross-sectional views of the respective test patterns after completion of step 21, respectively, fig. 3A, 4A, through 19A are omitted representations of fig. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, and 19A, and the omitted representations of the subsequent drawings are the same as those in step 21.
Step 25, growing silicon germanium 301 in the active region of the P-type transistor. Referring again to fig. 3A, 4A through 19A, no longer 25, sige 301 is formed only around the active region of the P-type transistor; no silicon germanium 301 is grown outside the active region of the P-type transistor and is not shown in the corresponding figure.
Step 26, shown in fig. 3B, 4B through 19B, deposits a silicon nitride layer 303.
Step 27, shown in fig. 3C, 4C through 19C, deposits an interlayer dielectric 304.
Step 28, as shown in fig. 3D, 4D through 19D, performs a chemical mechanical polishing of the interlayer dielectric 304.
Step 29, as shown in fig. 3E, 4E and 19E, the gate polysilicon 302 of the P-type transistor is removed, and the high-k dielectric layer, the isolation metal layer, the work function metal and the aluminum metal 305 forming the HKMG are deposited. In step 29, the gate polysilicon 302 of the N-type transistor remains, as shown in fig. 4E.
Step 210, as shown in fig. 3F, 4F through 19F, performs a chemical mechanical polishing of the metallic aluminum 305 of HKMG203 of the P-type transistor.
Step 211, as shown in fig. 3G, 4G and 19G, the gate polysilicon 302 of the N-type transistor is removed, and the high-k dielectric layer, the isolation metal layer, the work function metal and the metal aluminum 306 forming the HKMG are deposited.
Step 212, as shown in fig. 3H, 4H through 19H, a chemical mechanical polishing of the metallic aluminum 306 of HKMG204 of the N-type transistor is performed.
And step three, carrying out model data collection on the test wafer and carrying out modeling on a CMP process model. The third step in the embodiment of the invention comprises the following steps:
and 31, acquiring the front surface topography. Preferably, the method comprises the following steps: in step 31, directly measuring the wafer after the step 23 to obtain a front surface topography; alternatively, the step of acquiring the front surface topography of step 31 is: the prediction is performed according to the chemical mechanical polishing model of the shallow trench isolation medium 202, and then the global or local area shallow trench surface adjustment is performed to obtain the pre-surface topography.
And step 32, establishing a deposition model of the interlayer medium 304.
Step 33, establishing a grinding model of the interlayer medium 304.
And step 34, establishing a deposition model of the metallic aluminum 305 of the HKMG203 of the P-type transistor.
And step 35, establishing a grinding model of the metal aluminum 305 of the HKMG203 of the P-type transistor.
Step 36, modeling the deposition of metallic aluminum 305 of HKMG204 for the N-type transistor.
Step 37, a grinding model of the metallic aluminum 305 of the HKMG204 of the N-type transistor is established.
Only steps 36 and 37 are performed among steps 34, 35, 36 and 37 to save two steps.
The embodiment of the invention combines an actual manufacturing process, and introduces the HKMG test pattern and the thickness measurement substrate pattern which reflect various pre-shaped surface appearances and output of various grinding processes into the HKMG CMP process model test structure, so that the measurement result obtained based on the test pattern structure can accurately reflect the grinding pre-shaped surface appearance and the variation trend of the output of each HKMG CMP grinding process along with the change of the geometric characteristics of the test pattern, thereby ensuring the accuracy of the model, namely ensuring the manufacturability detection accuracy of the HKMG CMP process; in addition, the embodiment of the invention can obtain the grinding output of various graph structures after the P-type transistor HKMG CMP through direct measurement, so that two model building processes of deposition of metal aluminum of the HKMG of the P-type transistor and grinding of the metal aluminum of the HKMG of the P-type transistor can be omitted, and the modeling period is shortened.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (12)
1. A HKMG CMP process model test structure is characterized in that: the test structure comprises a final test pattern array formed by arranging final test pattern units; the final test pattern unit comprises a grid test pattern array and a measuring substrate pattern array;
the grid test pattern array is formed by arranging HKMG test patterns corresponding to various HKMG formed on various front-mounted topography surfaces;
the substrate pattern array is formed by arranging thickness measurement substrate patterns for measuring the HKMG thickness, the interlayer film thickness and the polysilicon thickness formed on the surfaces of various pre-topographies;
the pre-topography surface comprises: the surface of the silicon substrate is formed on the surface of a shallow trench isolation medium in the silicon substrate;
categories of HKMG include: HKMG for P-type transistors and HKMG for N-type transistors;
the HKMG test pattern comprises 9 patterns, namely:
the first HKMG test pattern is a test pattern formed by HKMG arrangement of a plurality of P-type transistors simultaneously formed on the surface of the continuous silicon-based substrate;
the second HKMG test pattern is a test pattern formed by HKMG arrangement of a plurality of N-type transistors simultaneously formed on the surface of the continuous silicon-based substrate;
the third HKMG test pattern is formed by alternately arranging HKMG of a plurality of N-type transistors and HKMG of P-type transistors which are simultaneously formed on the surface of the continuous silicon-based substrate;
a fourth HKMG test pattern is formed by arranging HKMG of a plurality of P-type transistors formed on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region;
a fifth HKMG test pattern is formed by arranging HKMG of a plurality of N-type transistors formed on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region;
the sixth HKMG test pattern is formed by alternately arranging HKMG of a plurality of N-type transistors and HKMG of P-type transistors on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region;
the seventh HKMG test pattern is a test pattern formed by HKMG arrangement of a plurality of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium;
the eighth HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of N-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium;
the ninth HKMG test pattern is a test pattern formed by alternately arranging HKMGs of a plurality of N-type transistors and HKMGs of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium.
2. The HKMG CMP process model test structure of claim 1, wherein: the HKMG of the corresponding N-type transistor and the HKMG of the corresponding P-type transistor in the HKMG test pattern are both in a strip shape.
3. The HKMG CMP process model test structure of claim 1, wherein:
in the mixed region of the silicon-based substrate and the shallow trench isolation medium, the silicon-based substrate is divided into a plurality of independent division structures by the shallow trench isolation medium, and the HKMG in the fourth HKMG test pattern, the fifth HKMG test pattern and the sixth HKMG test pattern forms the corresponding surfaces of the independent division structures.
4. The HKMG CMP process model test structure of claim 1, wherein: the thickness measurement substrate patterns corresponding to the measurement substrate pattern array comprise 8 patterns, which are respectively as follows:
the first thickness measuring substrate pattern is a silicon substrate pattern for measuring the HKMG thickness of the P-type transistor;
the second thickness measuring substrate pattern is a silicon substrate pattern for measuring the HKMG thickness of the N-type transistor;
the third thickness measuring substrate pattern is a silicon-based substrate pattern for measuring the thickness of the interlayer film;
the fourth thickness measuring substrate pattern is a silicon-based substrate pattern for measuring the thickness of the polycrystalline silicon;
the fifth thickness measuring substrate graph is a shallow trench isolation medium substrate graph for measuring the HKMG thickness of the P-type transistor;
the sixth thickness measuring substrate graph is a shallow trench isolation medium graph for measuring the HKMG thickness of the N-type transistor;
the seventh thickness measuring substrate graph is a shallow trench isolation medium graph for measuring the thickness of the interlayer film;
the eighth thickness measurement substrate pattern is a shallow trench isolation dielectric pattern for measuring the thickness of the polysilicon.
5. A modeling method of an HKMG CMP process model is characterized by comprising the following steps:
designing a test structure, wherein the test structure comprises a final test pattern array formed by arranging final test pattern units; the final test pattern unit comprises a grid test pattern array and a measuring substrate pattern array;
the grid test pattern array is formed by arranging HKMG test patterns corresponding to various HKMG formed on various front-mounted topography surfaces;
the substrate pattern array is formed by arranging thickness measurement substrate patterns for measuring the HKMG thickness, the interlayer film thickness and the polysilicon thickness formed on the surfaces of various pre-topographies;
step two, processing and manufacturing a test wafer according to the designed test structure, wherein the wafer consists of a silicon-based substrate, and the manufacturing process comprises the following steps:
step 21, forming a shallow trench in a selected area of the silicon-based substrate;
step 22, depositing a shallow trench isolation medium;
step 23, performing chemical mechanical polishing on the shallow trench isolation medium;
step 24, forming grid polysilicon;
step 25, growing silicon germanium in an active area of the P-type transistor;
26, depositing a silicon nitride layer;
step 27, depositing an interlayer medium;
step 28, performing chemical mechanical polishing on the interlayer medium;
29, removing the grid polysilicon of the P-type transistor, and depositing a high dielectric constant dielectric layer, an isolation metal layer, a work function metal and metal aluminum which form the HKMG;
step 210, performing chemical mechanical polishing on the metallic aluminum of the HKMG of the P-type transistor;
step 211, removing the gate polysilicon of the N-type transistor, and depositing a high dielectric constant dielectric layer, an isolation metal layer, a work function metal and metal aluminum which form the HKMG;
step 212, performing metal aluminum chemical mechanical polishing of the HKMG of the N-type transistor;
thirdly, model data collection is carried out on the test wafer, and modeling of a CMP process model is carried out;
the third step comprises the following steps:
step 31, acquiring a preposed surface appearance;
step 32, establishing a deposition model of the interlayer medium;
step 33, establishing a grinding model of the interlayer medium;
step 34, establishing a deposition model of metallic aluminum of the HKMG of the P-type transistor;
step 35, establishing a grinding model of the metallic aluminum of the HKMG of the P-type transistor;
step 36, establishing a deposition model of metallic aluminum of the HKMG of the N-type transistor;
and step 37, establishing a grinding model of the metallic aluminum of the HKMG of the N-type transistor.
6. The modeling method of the HKMG CMP process model according to claim 5, characterized in that: in step 31, directly measuring the wafer after the step 23 to obtain a front surface topography;
alternatively, the step of acquiring the front surface topography of step 31 is: the method comprises the steps of firstly predicting according to a chemical mechanical polishing model of the shallow trench isolation medium, and then adjusting the surface of the shallow trench in the global or local area to obtain the appearance of the preposed surface.
7. The modeling method of the HKMG CMP process model according to claim 5, characterized in that: only steps 36 and 37 are performed among steps 34, 35, 36 and 37 to save two steps.
8. The modeling method of the HKMG CMP process model according to claim 5, characterized in that: the pre-topography surface comprises: the surface of the silicon substrate is formed on the surface of a shallow trench isolation medium in the silicon substrate;
categories of HKMG include: HKMG for P-type transistors and HKMG for N-type transistors.
9. The modeling method of the HKMG CMP process model according to claim 8, characterized in that: the HKMG test pattern comprises 9 patterns, namely:
the first HKMG test pattern is a test pattern formed by HKMG arrangement of a plurality of P-type transistors simultaneously formed on the surface of the continuous silicon-based substrate;
the second HKMG test pattern is a test pattern formed by HKMG arrangement of a plurality of N-type transistors simultaneously formed on the surface of the continuous silicon-based substrate;
the third HKMG test pattern is formed by alternately arranging HKMG of a plurality of N-type transistors and HKMG of P-type transistors which are simultaneously formed on the surface of the continuous silicon-based substrate;
a fourth HKMG test pattern is formed by arranging HKMG of a plurality of P-type transistors formed on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region;
a fifth HKMG test pattern is formed by arranging HKMG of a plurality of N-type transistors formed on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region;
the sixth HKMG test pattern is formed by alternately arranging HKMG of a plurality of N-type transistors and HKMG of P-type transistors on the surface of the silicon-based substrate and the shallow trench isolation medium mixing region;
the seventh HKMG test pattern is a test pattern formed by HKMG arrangement of a plurality of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium;
the eighth HKMG test pattern is a test pattern formed by an HKMG arrangement of a plurality of N-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium;
the ninth HKMG test pattern is a test pattern formed by alternately arranging HKMGs of a plurality of N-type transistors and HKMGs of P-type transistors simultaneously formed on the surface of the continuous shallow trench isolation medium.
10. The modeling method of the HKMG CMP process model according to claim 9, characterized in that: the HKMG of the corresponding N-type transistor and the HKMG of the corresponding P-type transistor in the HKMG test pattern are both in a strip shape.
11. The modeling method of the HKMG CMP process model according to claim 9, characterized in that: in the mixed region of the silicon-based substrate and the shallow trench isolation medium, the silicon-based substrate is divided into a plurality of independent division structures by the shallow trench isolation medium, and the HKMG in the fourth HKMG test pattern, the fifth HKMG test pattern and the sixth HKMG test pattern forms the corresponding surfaces of the independent division structures.
12. The modeling method of the HKMG CMP process model according to claim 8, characterized in that: the thickness measurement substrate patterns corresponding to the measurement substrate pattern array comprise 8 patterns, which are respectively as follows:
the first thickness measuring substrate pattern is a silicon substrate pattern for measuring the HKMG thickness of the P-type transistor;
the second thickness measuring substrate pattern is a silicon substrate pattern for measuring the HKMG thickness of the N-type transistor;
the third thickness measuring substrate pattern is a silicon-based substrate pattern for measuring the thickness of the interlayer film;
the fourth thickness measuring substrate pattern is a silicon-based substrate pattern for measuring the thickness of the polycrystalline silicon;
the fifth thickness measuring substrate graph is a shallow trench isolation medium substrate graph for measuring the HKMG thickness of the P-type transistor;
the sixth thickness measuring substrate graph is a shallow trench isolation medium graph for measuring the HKMG thickness of the N-type transistor;
the seventh thickness measuring substrate graph is a shallow trench isolation medium graph for measuring the thickness of the interlayer film;
the eighth thickness measurement substrate pattern is a shallow trench isolation dielectric pattern for measuring the thickness of the polysilicon.
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