CN102063528B - Method for extracting rhombus redundant filling parasitic capacitance based on lookup table algorithm - Google Patents

Abstract

The invention discloses a method for extracting rhombus redundant filling parasitic capacitance based on a lookup table algorithm, belonging to the technical field of microelectronics, and mainly solving problems of low processing speed of the existing extracting tools and low counting precision of simplified models. The method comprises the following steps of: firstly providing four parameters capable of fully describing rhombus redundant metal filling modes; based on the set of parameters, establishing a four-dimension lookup table relevant to the rhombus redundant metal filling parasitic capacitance; and using the lookup table to fast and correctly extract the parasitic capacitance of the special rhombus redundant metal filling examples by the table lookup and interpolation calculation. The method is wide in application and fast in counting speed, and is used for extracting parasitic parameters and optimizing performance of chips in design of integrated circuits.

Description

Based on the redundant stray capacitance method for distilling of filling of the rhombus of lookup table algorithm

Technical field

The invention belongs to microelectronics technology, relate to the parasitic technological parameter of VLSI (very large scale integrated circuits) and extract the field, particularly relate to the redundant stray capacitance method for distilling of filling of a kind of rhombus, the parasitic parameter that can be used in the IC design process extracts and performance optimization.

Technical background

In the VLSI (very large scale integrated circuits) manufacturing process, chemically mechanical polishing CMP technology has become the major technique of interlayer dielectric planarization, and along with the development of manufacturing technology, CMP also is widely used in shallow grooved-isolation technique and Damascus technics.The advanced person's that adopt today photoetching process has proposed very high requirement to local and overall flatness; Although the CMP technology has good relatively flatness; But because lower floor's domain pattern density is inhomogeneous; Still can cause the dielectric variation in thickness in polishing back inhomogeneous, and this problem become more and more sharp-pointed along with the increase day by day of raising day by day, wafer size and the die-size of circuit performance requirement.

Can reach the requirement of photoetching process for the effect that makes chemically mechanical polishing; The areal concentration of requirement domain in the process of chemically mechanical polishing is constant value, and the method that is employed in the metal filled figure that inserts redundancy in the domain figure usually is to reach the purpose that makes the density homogenising.Redundant metal filled planarization is to adopt extra metallic pattern to make the domain density area be tending towards the technology of equalization; This technology is inserted redundant metal with the uneven situation of the density of compensation domain own through the white space on domain, the redundant metal that is received in can ground connection also can be unsettled.Yet redundant metal filled being widely used in brought new problem aspect sequential when improving flatness.Redundant metal filled meeting increases the electric capacity of interconnection line, and Sinha points out in " Impact of modern process technologies on the electricalparameters of interconnects Proceedings of the 20th InternationalConference on VLSI Design " literary composition: the redundant metal filled total capacitance of crucial gauze that makes is increased to 2.6 times at most.The increase of interconnection capacitance will postpone, crosstalk, aspect such as power consumption produces significant effects; In patent " Diamond metal-filledpatterns achieving low parasitic coupling capacitance ", propose the redundant metal filled pattern of rhombus for this situation Hung, can when satisfying density homogenization requirement, reduce the extra capacitor of introducing.

Generally speaking, redundancy is metal filled to be the technological process of carrying out in the flow stage, does to consider fully so should just insert the capacitance increase that causes to redundant metal in chip design stage, otherwise can increase the uncertainty in the sequential calculating.And should in design, be directed against this effect is that parameters stays suitable surplus in advance, otherwise may cause chip functions to degenerate or thoroughly lost efficacy.

Capacitor model that adopts when current electric capacity extracting tool calculates interconnection capacitance and computation process are all comparatively complicated, and the computing time of when a large amount of interconnection graph data of computing, expending is longer.This can prolong the circuit design disadvantage in time in the shortening of design cycle, increases design cost.

Calculate parasitic redundant capacitor increment for ease fast, proposed the some kinds of simplified models that extract stray capacitance roughly.Kurokawa provides a kind of redundant electric capacity computation model of filling width of ignoring in article " Efficient capacitance extractionmethod for interconnects with dummy fills ".Block of metal that redundant fill area is simplified to approximate when in this model, calculating redundant capacitor is handled; Because equaling actual range, the equivalent distances between the capacitor two-plate deducts unsettled metal thickness; So two the effective medium width between the interconnection line equals actual pitch and deducts the redundant width of filling, and is as shown in Figure 1.

Kim Y has proposed more accurately simplified model of another kind in " Simple and accurate models for capacitance increment dueto metal fill insertion Proceedings of Asia and South Pacific DesignAutomation Conference " literary composition; This simplified model is when calculating coupling length; With the fill area and be not filled the zone the medium width calculate respectively, the medium width of fill area equals the width that interconnect pitch deducts redundant metal; The interconnect pitch that is not filled part equals interconnect width.In final calculation result, total capacitance is regarded as the parallel connection of this two parts electric capacity and handled, as shown in Figure 2.

The limitation of these two kinds of models is only to be applicable to the comparatively simple pattern filling of processing, and stray capacitance inapplicable and the redundant metal filled figure of calculation of complex, like the redundant metal filled figure of rhombus.First kind of model simplification degree is higher, and be bigger with the results of calculation deviation, and second kind of model do not considered the edge effect of electric capacity, also can produce bigger error.Though these models improve counting yield through the actual interconnect simplified models is reduced computation complexity.But they only are adapted under the not high situation of accuracy requirement comparatively simple redundant metallic pattern being calculated.Along with the development of ic manufacturing technology, under the deep submicron process condition, various deep-submicron effects make the deviation of above-mentioned several kinds of electric capacity computing method and actual capacitance increment constantly increase.The inexactness of these models is brought new difficulty to circuit design.

Summary of the invention

The objective of the invention is to overcome the deficiency of above-mentioned prior art; The redundant stray capacitance method for distilling of filling of a kind of rhombus based on lookup table algorithm is proposed; To improve computational accuracy; Realize the accurate extraction of rhombus fill pattern redundant capacitor, satisfy the more harsh requirement that present IC design faces.

The technical thought that realizes the object of the invention is: at first set up one group and can describe rhombus fill pattern and parameter few parameter group of trying one's best fully; Set up look-up table according to the key parameter in the parameter group then, utilize this look-up table can obtain comparatively accurate redundant capacitor value with a kind of interpolation algorithm calculating of science.Its concrete performing step comprises as follows:

(1) with buffer distance BS, fill width W, filling block length of side L, four key parameters of filling block space D are as the parameter sets of describing the redundant fill pattern of rhombus fully;

(2) set up with above-mentioned four four-dimensional look-up table that parameter is input.:

2a) will fill the 4 dimension parameter spaces that these 4 parameters of width W, buffer distance BS, filling block length of side H and filling block space D constitute, according to the integrated circuit fabrication process node and as a result the desired SI of precision be divided into grid, and grid is numbered;

2b) to each grid point, utilize the electric capacity extracting tool to obtain its corresponding parasitic capacitance value;

2c) deposit in respectively in the array, form look-up table according to grid number order capacitance and parameter sets that grid point is corresponding;

(3) use interpolation method to calculate parasitic capacitance value according to look-up table

3a) for any input vector (w ₀, b ₀, h ₀, d ₀) respectively its coordinate element is rounded the four-dimension input monumented point that obtains correspondence to the SI:

Wherein (w, b, h, d) expression parameter space coordinate figure, k, l, m, n represent the SI of w, b, h, d respectively;

3b) for arbitrary grid, establish its 16 lattice points and be respectively: c (w, b, h, d), c (w+k, b, h, d), c (w, b+l, h, d), c (w; B, h+m, d), c (w, b, h, d+n), c (w+k, b+l, h, d), c (w+k, b, h+m; D), c (w+k, b, h, d+n), c (w, b+l, h+m, d), c (w, b+l, h, d+n), c (w, b; H+m, d+n), c (w+k, b+l, h+m, d), c (w, b+l, h+m, d+n), c (w+k, b, h+m, d+n), c (w+k; B+l, h, d+n), c (w+k, b+l, h+m, d+n), (h is d) as the grid monumented point for w, b from 16 lattice points, fixedly to choose lattice point: c;

3c) calculating the corresponding grid monumented point coordinate of input point is that (sm un), according to the coordinate of all the other 15 grid points of SI calculating, can find the corresponding grid of input vector for rk, tl;

3d) establishing input vector is (w ₀, b ₀, h ₀, d ₀), its grid point of corresponding grid be A _i, the appearance value in the electric capacity space that grid point is corresponding is respectively C _i, i=0 wherein, 1 ... 15; The SI of W, B, H, four coordinate axis of D is respectively k, l, m, n, with input vector (w ₀, b ₀, h ₀, d ₀) the coordinate element respectively the SI of its coordinate axis is got the surplus intermediate vector (w ', b ', h ', d ') that obtains;

3e) input point is divided into 16 4 dimension zones with its pairing grid, and each zone comprises the lattice point of this grid, calculates the volume V of each lattice point region _i, i=0 wherein, 1 ... 15, the applying volume method of interpolation is tried to achieve the unit length parasitic capacitance value:

$C_p=\underset{i=1}{\overset{16}{\mathrm{\Σ}}}\frac{V_i}{V}\·C_i,$

C wherein _iBe lattice point electric capacity, V=klmn is the cumulative volume of grid.

3f) unit length parasitic capacitance value and interconnect length L are multiplied each other obtain exporting parasitic capacitance value C _Out=C _pL.

The present invention has following advantage:

1) the present invention is owing to adopt lookup table algorithm to replace traditional capacitor model computing method, thereby following advantage is being arranged aspect the stray capacitance extraction:

At first, the lookup table algorithm highly versatile, and can satisfy the requirement of nonlinear transformation.

Its two, lookup table algorithm characterizes the influential key factor of result with parameter space, promptly can be applicable to solve complicated problems more so only need simply expand dimension.

Its three, it is often a lot of soon than the complicated calculations speed based on the electric capacity physical model from internal memory, to extract numerical value, can promote computing velocity significantly.

2) the present invention compares it and has comprised various known deep-submicron effects owing to adopt existing mature electric capacity extracting tool to obtain the grid point capacitance with existing simplified model, and like the resistance shielding effect, precision is higher.

3) the present invention is owing to expand to four-dimentional space handling the difference problem of four-dimensional look-up table with the cube method of interpolation, its explicit physical meaning, calculate simple and precision higher.

Description of drawings

Fig. 1 is the existing interconnection capacitance simplified model synoptic diagram of filling width of ignoring;

Fig. 2 is the interconnection capacitance simplified model synoptic diagram of existing electric capacity parallel connection;

Fig. 3 is a rhombus fill pattern parameter synoptic diagram of the present invention;

Fig. 4 is coupling capacitance increment of the present invention and filling width graph of a relation;

Fig. 5 is coupling capacitance increment of the present invention and buffer distance BS graph of a relation;

Fig. 6 is coupling capacitance increment of the present invention and H/D graph of a relation;

Fig. 7 is a realization flow block diagram of the present invention;

Fig. 8 is that the present invention searches the sub-process block diagram.

Embodiment

One. set the parameter group that the expression rhombus is filled capacitance increase

With reference to Fig. 3, the present invention fills buffer distance BS with width W, filling block length of side H, and four model parameters of filling block space D are as the key parameter of describing the rhombus fill pattern.

Each parameter-definition is following:

Buffer distance BS is meant the minor increment that is allowed between signal wire and the pattern filling.Fig. 4 has represented the redundant variation relation of filling the capacitance increase that causes with buffer distance of rhombus.As can be seen from Figure 5, buffer distance is the principal element that capacitance increase between the interconnection line of back is filled in influence, along with the increase coupling capacitance increment monotone decreasing of BS.Experiment shows; In the range of size that current integrated circuit fabrication process node allows; Along with the minimizing speed of the increase capacitance increase of BS reduces gradually, be example with 90nm silicon technology node, can be similar under at BS and think that capacitance increase reduces along with the increase of BS is linear greater than the situation of 150nm.

Fill width W, be meant as the vertical range between two parallel interconnection lines on border, fill area.Fig. 5 has represented that four kinds of down redundant metal filled capacitance increase that cause of different buffer distances are with the variation relation of filling width W.As can be seen from Figure 4, fill width W capacitance increase is had remarkable influence, capacitance increase increases along with the increase of filling width.When W was big, the pace of change of capacitance increase slowed down gradually, and is example with 90nm silicon technology node, and after the filling width was greater than 1600nm, capacitance increase can be ignored with the variation of filling width W.

Filling block length of side H is meant the size dimension of rhombus filling block.

The filling block space D is meant the vertical range between the adjacent two rhombus filling blocks.

Lee W S is another principal element that influence the redundant capacitor increment through experiment proof packed density in article " Investigation of the capacitance deviation due tometal-fills and the effective interconnect geometry modeling ", and packed density is meant the ratio that is filled rhombus redundancy metallic area and the total area in the zone.Under the situation that BS confirms, the packed density of rhombus fill pattern is by redundant filling block length of side H and filling block space D two parameter determining.It has been generally acknowledged that filling block quantity far more than interconnections, this moment, packed density can be expressed as:

$\mathrm{\ρ}=\frac{H^2}{{(H+D)}^2}=\frac{1}{{(1+\frac{D}{H})}^2}.$

Formula can be found out thus;

determining packed density, and more greatly then packed density is more little for its ratio.When the packed density of fill area was confirmed, then the ratio of H and D also was determined.

Fig. 6 has represented the variation tendency of M3 layer metal interconnecting wires total capacitance increment with packed density and filling block size.Can draw as drawing a conclusion by Fig. 6:

A. the capacitance increase that redundant metal causes increases with packed density;

B. it is certain to work as packed density, and when promptly H/D was constant, capacitance increase reduced along with the increase of the rhombus filling block length of side.

C. in order to make redundant interconnections electric capacity as far as possible little, in the metal filled technology of redundancy,, should in the scope that process conditions allow, adopt bigger filling size especially for large-area redundant the filling.

Two. use lookup table algorithm and calculate rhombus filling stray capacitance

With reference to Fig. 7, the present invention includes following steps:

Step 1. fills buffer distance BS with width W, filling block length of side L, and four key parameters of filling block space D are as the parameter sets of describing the redundant fill pattern of rhombus fully.

Step 2. is set up look-up table

2.1) cut apart

Cutting apart, is in process conditions institute restricted portion, to be divided into grid to parameter space according to certain SI.Electric capacity for redundant metal capacitance extracts problem, and parameter space is by filling 4 dimension spaces that width W, buffer distance BS, filling block length of side H and 4 parameters of filling block space D constitute.

Uniformly-spaced divide for parameter space, perhaps divide, perhaps in the high scope of accuracy requirement, segment rough segmentation in the not high scope of accuracy requirement according to the amplitude of variation of the corresponding a certain special parameter of capacitance variation unit-sized; In order to search conveniently; The present invention adopts uniformly-spaced and evenly divides; With filling the 4 dimension parameter spaces that these 4 parameters of width W, buffer distance BS, filling block length of side H and filling block space D constitute; According to the integrated circuit fabrication process node and as a result the desired SI of precision be divided into grid, and grid is numbered.

The division number of grid depends on the precision of needs and the capacity that storage space allows; When accuracy requirement during higher and don't limited storage space; Then can choose more sampled point, simultaneously, it is too much that sampled point should not be chosen; Too much sampled point can make the capacity of look-up table excessive, influences seek rate then.

The present invention is an example with 90nm silicon technology node, adopts the SI of 1.0-2.5nm that parameter space is divided, and sets up look-up table.

2) mapping

Mapping is to each grid point in the parameter space, calculates it through the stray capacitance extracting tool and corresponds to the appearance value in electric capacity space.The selection of mapping function is most important; The mapping function that does not satisfy accuracy requirement possibly bring variation in capacitance value very on a large scale; Traditional method is to record the mapping one by one of data realization accurately and reliably through experiment, but in the metal filled field of redundancy, this method does not have operability.Simple more and direct method is employing, and existing mature electric capacity extracting tool is realized the mapping relations from parameter space to the electric capacity space.Compare with existing simplified model, high performance electric capacity extracting tool has comprised various known deep-submicron effects, and like the resistance shielding effect, so precision is higher.Present embodiment adopts the quickcap instrument under the fastmodel to accomplish the work of setting up of look-up table as the reference capacitance extracting tool, but is not limited to this instrument.

3) build table

Building table, is to put into form with grid point corresponding parameters spatial data with through the electric capacity spatial data that mapping obtains, and forms look-up table.In practical application, building table handling is depositing in respectively in the array with its corresponding capacitance according to the parameter group of grid number order with grid point, forming look-up table.The advantage of the look-up table of this form is to search fast, and is consuming time fewer, can reach higher precision.

Step 3. is carried out the look-up table interpolation arithmetic

Set up after the look-up table, in order to obtain the corresponding parasitic capacitance value of input vector, need do the look-up table interpolation arithmetic one time to input vector, it mainly contains two steps:

3.1) search

Searching is for a known input point, searches for the grid at its place, and selects the step of the grid point that helps to calculate, and with reference to Fig. 8, it is following that it searches flow process:

At first, read in input vector (w ₀, b ₀, h ₀, d ₀);

Then, with input vector (w ₀, b ₀, h ₀, d ₀) the coordinate element respectively the SI of its coordinate axis is rounded, obtain corresponding four-dimension input monumented point:

Wherein (w, b, h, d) expression parameter space coordinate figure, k, l, m, n represent the SI of w, b, h, d respectively;

Then,, establish its 16 lattice points and be respectively for arbitrary grid: c (w, b, h, d), c (w+k, b, h, d), c (w, b+l, h; D), c (w, b, h+m, d), c (w, b, h, d+n), c (w+k, b+l, h, d), c (w+k, b; H+m, d), c (w+k, b, h, d+n), c (w, b+l, h+m, d), c (w, b+l, h, d+n), c (w; B, h+m, d+n), c (w+k, b+l, h+m, d), c (w, b+l, h+m, d+n), c (w+k, b, h+m; D+n), c (w+k, b+l, h, d+n), c (w+k, b+l, h+m, d+n), (h is d) as the grid monumented point for w, b from these 16 lattice points, fixedly to choose lattice point: c;

At last, calculating the corresponding grid monumented point coordinate of input point is that (sm un), according to the coordinate of all the other 15 grid points of SI calculating, can find the corresponding grid of input vector for rk, tl;

3.2: interpolation

Interpolation is the method that adopts interpolation according to the numerical evaluation input point of the selected grid point output valve in the electric capacity space, and it is realized as follows:

At first, by input point its pairing grid is divided into 16 4 dimension zones, each zone comprises the lattice point of this grid, calculates the volume V of each lattice point region _i, i=0 wherein, 1 ... 15, its computing formula is following:

V ₀＝w′·b′·h′·d′

V ₁＝(k-w′)·b′·h′·d′

V ₂＝w′·(l-b′)·h′·d′

V ₃＝w′·b′·(m-h′)·d′

V ₁₅＝(k-w′)·(l-b′)·(m-h′)·(n-d′)

K wherein, l, m, n are respectively the SIs of W axle, B axle, H axle and D axle, w ', b ', h ', d ' be input point to being the distance of four coordinate axis of initial point with the grid monumented point, it is worth by input vector (w ₀, b ₀, h ₀, d ₀) the coordinate element respectively the SI of its coordinate axis is got surplus obtaining.

Then, the applying volume method of interpolation is tried to achieve the unit length parasitic capacitance value:

, C wherein _iBe lattice point electric capacity, i=0,1 ... 15, V=klmn is the cumulative volume of grid.

At last, unit length parasitic capacitance value and interconnect length L are multiplied each other, obtain exporting parasitic capacitance value C _Out=C _pL.

Above step has been described the redundant metal filled instance of rhombus that the present invention is confirmed by W, B, H, four parameters of D; Obviously those skilled in the art passes through with reference to instance of the present invention and accompanying drawing; Can make various modifications and replacement to the present invention, these modifications and replacement all should fall within protection scope of the present invention.

Claims (1)

1. the redundant stray capacitance method for distilling of filling of the rhombus based on lookup table algorithm comprises the steps:

(1) with buffer distance BS, fill width W, filling block length of side L, four key parameters of filling block space D are as the parameter group of describing the redundant fill pattern of rhombus fully;

(2) set up with above-mentioned four four-dimensional look-up table that parameter is input:

2a) will fill the 4 dimension parameter spaces that these 4 parameters of width W, buffer distance BS, filling block length of side L and filling block space D constitute, according to the integrated circuit fabrication process node and as a result the desired SI of precision be divided into grid, and grid is numbered;

2b) to each grid point, utilize the electric capacity extracting tool to obtain its corresponding parasitic capacitance value;

2c) deposit in respectively in the array, form look-up table according to grid number order capacitance and parameter group that grid point is corresponding;

(3) use interpolation method to calculate parasitic capacitance value according to look-up table:

3a) for any input vector (w ₀, b ₀, h ₀, d ₀) its coordinate element was rounded the SI obtain vector respectively:

Wherein (w, b, h, d) expression parameter space coordinate figure, k, l, m, n represent the SI of w, b, h, d respectively;

3b) for arbitrary grid, establish its 16 lattice points and be respectively: c (w, b, h, d), c (w+k, b, h, d), c (w, b+l, h, d), c (w; B, h+m, d), c (w, b, h, d+n), c (w+k, b+l, h, d), c (w+k, b, h+m; D), c (w+k, b, h, d+n), c (w, b+l, h+m, d), c (w, b+l, h, d+n), c (w, b; H+m, d+n), c (w+k, b+l, h+m, d), c (w, b+l, h+m, d+n), c (w+k, b, h+m, d+n), c (w+k; B+l, h, d+n), c (w+k, b+l, h+m, d+n), (h is d) as the grid monumented point for w, b from 16 lattice points, fixedly to choose lattice point: c;

3c) calculating the corresponding grid monumented point coordinate of input point is that (sm un), according to the coordinate of all the other 15 grid points of SI calculating, can find the corresponding grid of input vector for rk, tl;

3d) establishing input vector is (w ₀, b ₀, h ₀, d ₀), its grid point of corresponding grid be A _i, the appearance value in the electric capacity space that grid point is corresponding is respectively C _i, i=0 wherein, 1 ... 15; The SI of W, B, H, four coordinate axis of D is respectively k, l, m, n, with input vector (w ₀, b ₀, h ₀, d ₀) the coordinate element respectively the SI of its coordinate axis is got the surplus intermediate vector (w ', b ', h ', d ') that obtains;

3e) input point is divided into 16 4 dimension zones with its pairing grid, and each zone comprises the lattice point of this grid, calculates the volume V of each lattice point region _i, i=0 wherein, 1 ... 15, the applying volume method of interpolation is tried to achieve the unit length parasitic capacitance value:

C wherein _iBe lattice point electric capacity, V=klmn is the cumulative volume of grid;

The volume V of each lattice point region of described calculating _i, be to calculate through following formula:

V ₀=w′·b′·h′·d′

V ₁=(k-w′)·b′·h′·d′

V ₂=w′·(l-b′)·h′·d′

V ₃=w′·b′·(m-h′)·d′

......

V ₁₅=(k-w′)·(l-b′)·(m-h′)·(n-d′)

K wherein, l, m, n are respectively the SIs of W axle, B axle, H axle and D axle, w ', b ', h ', d ' be input point to being the distance of four coordinate axis of initial point with the grid monumented point, it is worth by input vector (w ₀, b ₀, h ₀, d ₀) the coordinate element respectively the SI of its coordinate axis is got surplus obtaining;

3f) unit length parasitic capacitance value and interconnect length L are multiplied each other obtain exporting parasitic capacitance value C _Out=C _pL.

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