CN103164572B - A kind of modeling method of integrated circuit interconnection line stray capacitance - Google Patents

Abstract

A kind of modeling method for integrated circuit interconnection line stray capacitance.Described modeling method is: for a given interconnecting construction, the single order of its stray capacitance is asked with finite element method, second order susceptibility, set up corresponding second order stray capacitance base expression, and the stray capacitance initial value of some calculation levels in design size parameter effective range is calculated by this expression formula, the parasitic capacitance value of these calculation levels is directly calculated again with finite element field solver, these two capacitances of identical point are subtracted each other, obtain a series of error amount, an error correction expression formula is simulated with these error amounts, on the second order stray capacitance base expression obtained before this error correction expression formula is added to, finally obtain the more accurate stray capacitance expression formula of this interconnecting construction.

Description

A kind of modeling method of integrated circuit interconnection line stray capacitance

Technical field

The present invention relates to a kind of method of designing integrated circuit, particularly a kind of method for building up of interconnection line stray capacitance mode storehouse.

Background technology

In recent years, because interconnection line parasitic parameter in integrated circuit is to the tremendous influence of the aspects such as the integrality of circuit signal and reliability, people are made to have to pay attention to the accurate extraction to interconnection line parasitic parameter.The analytic method of parasitic parameter extraction early application is suitable only for some very simple structures, and along with the day by day complicated and more and more higher solving precision requirement of interconnection structure, direct field solves becomes a kind of effective method.But for huge interconnection structure, all use carrys out direct solution, high time cost is obviously unworkable, so the method in establishment model storehouse is used so far always.Comprise a lot of model in pattern base, the corresponding a kind of conventional structure of each model, during circuit characteristic verification, just calculates the parasitic parameter of true interconnection line with these models.At present, because interconnection line scale is increasing, interconnection line complexity is more and more higher, the model quantity in interconnection pattern storehouse sharply increases, add technique change, make conductor shape off-design size, add difficulty to the foundation of pattern base, spend the less time to set up high-precision model is pursuing a goal of people always, and seems even more important current.

Capacitor model has two kinds of existence forms: interpolation form and approximate analytical expression.If interpolation point is abundant, this method has higher precision, because each interpolation point needs the calculating or the experiment test that carry out primary field, so interpolation point means that will carry out more times calculates or test more, and storing a lot of interpolation points needs to take a lot of internal memory.Analytical expression is then very terse, all very convenient for designer and layout instrument, but, under shorter time restriction, obtain expression formula not a duck soup more accurately.

Along with the increase of the thick wide ratio of wire, reducing of characteristic dimension, former expression precision no longer can meet the demands, and, for each technique, all will modeling again, pure experimental formula is obviously infeasible.As can be seen from the document retrieved, at present, major part capacitor model is all based on Electric Field Distribution, resolve into some components, then find out the relation between electric flux and geometric parameter, only this relation is fairly simple at the beginning, degree of approximation is weaker, have employed more complicated relational expression afterwards, simulation closer to some, depend on the experience of modeler to a great extent.But for technique of new generation, size is less, approximation relation error originally will increase, and modeling is more difficult.Within the shorter time, how to set up parasitic parameter pattern base become an important ring in integrated circuit (IC) design.

Summary of the invention

The object of the invention is the shortcoming overcoming prior art, the method for a kind of integrated circuit interconnection line stray capacitance modeling is provided.The present invention in the short period of time, can set up interconnection line stray capacitance mode storehouse with the form of expression formula, for the circuit characteristic verification during integrated circuit back-end designs provides reliable support, finally reaches the object improving product reliability and shorten the launch cycle.

The step of the modeling method of integrated circuit interconnection line stray capacitance of the present invention is as follows:

For a given interconnecting construction, the single order of its stray capacitance is asked with finite element method, second order susceptibility, set up corresponding second order stray capacitance base expression, and the stray capacitance initial value of some calculation levels in design size parameter effective range is calculated with this second order stray capacitance base expression, the parasitic capacitance value of described calculation level is directly calculated again with finite element field solver, two capacitances of the identical calculations point to calculate for twice are subtracted each other, obtain corresponding a series of error amount, an error correction expression formula is simulated with described error amount, on the second order stray capacitance base expression obtained before this error correction expression formula is added to, finally obtain the stray capacitance expression formula of this interconnecting construction.

Described given interconnecting construction can choose any one interconnecting construction wherein in interconnection line stray capacitance mode storehouse.

The modeling method of described interconnecting construction stray capacitance expression formula comprises following four steps:

1, choose an interconnecting construction in interconnection line stray capacitance mode storehouse, set up its second order stray capacitance base expression.In design size parameter p ₁, p ₂, p ₃... rated point (the p of required scope ₁₀, p ₂₀, p ₃₀...) above directly calculate a capacitance as C with finite element field solver ₀, this rated point calculates stray capacitance to the first order derivative of each design size parameter by the method for finite element local J acobian Matrix Calculating derivative and second derivative thus obtain this interconnecting construction second order stray capacitance base expression:

$C1=C_0+\underset{i}{\mathrm{\Σ}}\frac{\∂C_{\left(0\right)}}{\∂p_i}\·\mathrm{\Δ}{p}_i+\underset{i}{\mathrm{\Σ}}\frac{{\∂}^2{\text{C}}_{\left(0\right)}}{\∂p_i^2}\·\mathrm{\Δ}{p}_i^2+\underset{i\≠j}{\underset{i,j}{\mathrm{\Σ}}}\frac{{\∂}^2{C}_{\left(0\right)}}{\∂p_i\∂p_j}\·\mathrm{\Δ}{p}_i\mathrm{\Δ}{p}_j---\left(1\right)$

P in above-mentioned (1) formula _i0be the rated point size of i-th design size parameter, Δ p _ibe the value of i-th design size parameter drift-out rated point, i.e. (p _i-p _i0), with (p _i-p _i0) replace Δ p _i, can obtain with p _ifor this interconnecting construction second order stray capacitance base expression of variable.

2, directly calculate the parasitic capacitance value of some points in design size parameter effective range with finite element field solver, the position of each calculation level and quantity adopt the orthogonal arrage in orthogonal experiment design method to choose.Each design size parameter, i.e. factor, chooses some values, i.e. level value in its effective range, is generally no more than 10 values, selects closeer near rated point, comparatively more sparse away from rated point.According to because of prime number and level value, adopt corresponding orthogonal arrage in orthogonal experiment design method, which determine to calculate with finite element field solver on calculation level of each design size parameter, with finite element field solver, selected calculation level is calculated, obtain a series of parasitic capacitance value C2, in (1) formula in part 1 described in simultaneously the calculation level chosen by orthogonal arrage being substituted into, calculate a series of more rough stray capacitance initial value C1.

3, error correction expression formula is set up.The a series of parasitic capacitance value C2 obtained with finite element solving device in described the step 2 and a series of stray capacitance initial value C1 calculated by (1) formula, according to the principle that same design dimensional parameters point subtracts each other between two, the parasitic capacitance value C2 that stray capacitance initial value C1 on identical calculations point and described use finite element field solver obtain is subtracted each other between two, that is: Δ C=C2-C1, obtain a series of error amount Δ C, by the design size parameter p of error amount Δ C with its correspondence ₁, p ₂, p ₃... matching second order error innovation representation:

$\mathrm{\ΔC}=a_0+\underset{i}{\mathrm{\Σ}}{a}_i{p}_i+\underset{j}{\mathrm{\Σ}}{b}_j{p}_j^2+\underset{k\≠l}{\underset{k,l}{\mathrm{\Σ}}}{c}_{\mathrm{kl}}{p}_k{p}_l---\left(2\right)$

Obtain each undetermined coefficient a ₀, a _i, b _j, c _kl.Above-mentioned (2) formula also becomes with design parameter p ₁, p ₂, p ₃... for the expression formula of variable, represent the error caused as the stray capacitance expression formula of the interconnecting construction of wanted modeling by (1) formula.

4, for given interconnecting construction, the final interconnection line stray capacitance expression formula set up is second order stray capacitance base expression (1) in step 1 and the superposing of error correction expression formula (2) set up in step 3, i.e. C=C1+ Δ C.

The present invention at the beginning of integrated circuit (IC) design, efficiently can set up high-precision stray capacitance mode storehouse rapidly, for technical support is done in back-end physical verification, shortens the launch cycle.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of an interconnecting construction in interconnection line stray capacitance mode storehouse to be created in the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, the invention will be further described.

The modeling method of interconnecting construction stray capacitance expression formula of the present invention is: first choose any one interconnecting construction in interconnection line stray capacitance mode storehouse, according to its stray capacitance expression formula of method establishment of the present invention, all the other interconnecting construction stray capacitance expression formulas just can be set up with the modeling method of this interconnecting construction stray capacitance expression formula.

Figure 1 shows that an interconnecting construction in interconnection line stray capacitance mode storehouse to be created in the present invention.As shown in Figure 1, p ₁, p ₂, p ₃... for design size parameter, p ₁conductor thickness, p ₂the distance of this layer conductor from substrate, p ₃adjacent lines spacing, p ₄line width, each own corresponding Significant Change scope, and have a rated point (p ₁₀, p ₂₀, p ₃₀...), the stray capacitance setting up expression formula can be the stray capacitance C in Fig. 1 _cor C _g.Rated point calculates a capacitance as C with finite element field solver ₀, and calculate stray capacitance to single order, the second derivative values of each design size parameter by the method for finite element local J acobian Matrix Calculating derivative, thus obtain this interconnecting construction second order stray capacitance base expression: $C1=C_0+\underset{i}{\mathrm{\Σ}}\frac{\∂C_{\left(0\right)}}{\∂p_i}\·\mathrm{\Δ}{p}_i+\underset{i}{\mathrm{\Σ}}\frac{{\∂}^2{\text{C}}_{\left(0\right)}}{\∂{p^2}_i}\mathrm{\Δ}{p}_i^2+\underset{i\≠j}{\underset{i,j}{\mathrm{\Σ}}}\frac{{\∂}^2{C}_{\left(0\right)}}{\∂p_i\∂p_j}\·\mathrm{\Δ}{p}_i\mathrm{\Δ}{p}_j,$ The Δ p in this formula _iall expand into (p _i-p _i0), p _i0for rated point size, can obtain with p _ifor the second order stray capacitance base expression of variable.

In design size parameter p ₁, p ₂, p ₃some values are got in respective effective range, i.e. level value, generally be no more than 10 values, choose closeer near rated point, comparatively more sparse away from rated point, design size number of parameters is because of prime number, according to because of prime number and level value, adopt corresponding orthogonal arrage in orthogonal experiment design method, determine to calculate with finite element field solver on which calculation level.Select through orthogonal arrage, calculating counts can reduce to the magnitude of dozens of.The parasitic capacitance value of these calculation levels is directly calculated with finite element field solver, obtain a series of parasitic capacitance value C2, the design size parameter value of these calculation levels is substituted in foregoing second order stray capacitance base expression respectively simultaneously, calculate a series of stray capacitance initial value C1.Then the parasitic capacitance value C2 of identical calculations point and stray capacitance initial value C1 is subtracted each other between two, i.e. Δ C=C2-C1, obtain a series of error amount Δ C, with the design size parameter fitting second order error innovation representation of error amount Δ C and correspondence thereof $\mathrm{\ΔC}=a_0+\underset{i}{\mathrm{\Σ}}{a}_i{p}_i+\underset{j}{\mathrm{\Σ}}{b}_j{p}_j^2+\underset{k\≠l}{\underset{k,l}{\mathrm{\Σ}}}{c}_{\mathrm{kl}}{p}_k{p}_l,$ Obtain each undetermined coefficient a ₀, a _i, b _j, c _kl.

The stray capacitance expression formula of final foundation is foregoing second order stray capacitance base expression $C1=C_0+\underset{i}{\mathrm{\Σ}}\frac{\∂C_{\left(0\right)}}{\∂p_i}\·\mathrm{\Δ}{p}_i+\underset{i}{\mathrm{\Σ}}\frac{{\∂}^2{\text{C}}_{\left(0\right)}}{\∂{p^2}_i}\mathrm{\Δ}{p}_i^2+\underset{i\≠j}{\underset{i,j}{\mathrm{\Σ}}}\frac{{\∂}^2{C}_{\left(0\right)}}{\∂p_i\∂p_j}\·\mathrm{\Δ}{p}_i\mathrm{\Δ}{p}_j$ With error correction expression formula $\mathrm{\ΔC}=a_0+\underset{i}{\mathrm{\Σ}}{a}_i{p}_i+\underset{j}{\mathrm{\Σ}}{b}_j{p}_j^2+\underset{k\≠l}{\underset{k,l}{\mathrm{\Σ}}}{c}_{\mathrm{kl}}{p}_k{p}_l$ Superposition, i.e. C=C1+ Δ C, wherein, second order stray capacitance base expression has been launched into p _ifor the expression formula of variable.

All the other interconnecting construction stray capacitance expression formulas can be set up according to the modeling method of described interconnecting construction stray capacitance expression formula.

Claims (1)

1. the modeling method of an integrated circuit interconnection line stray capacitance, it is characterized in that, described modeling method is: for a given interconnecting construction, the single order of the stray capacitance of described interconnecting construction is asked with finite element method, second order susceptibility, set up corresponding second order stray capacitance base expression, and the stray capacitance initial value of some calculation levels in design size parameter effective range is calculated with described second order stray capacitance base expression, the parasitic capacitance value of described calculation level is directly calculated again with finite element field solver, two capacitances of the identical calculations point to calculate for twice are subtracted each other, obtain corresponding error amount, error correction expression formula is simulated with described error amount, on the second order stray capacitance base expression that described error correction expression formula is added to described, obtain the stray capacitance expression formula that this interconnecting construction is final,

Establishment step for the second order stray capacitance base expression of described given interconnecting construction is as follows: in design size parameter p ₁, p ₂, p ₃... rated point (the p of effective range ₁₀, p ₂₀, p ₃₀...) above directly calculate a capacitance as C with finite element field solver ₀, this rated point calculates stray capacitance to single order, the second derivative values of each design size parameter by the method for finite element local J acobian Matrix Calculating derivative, obtains the second order stray capacitance base expression of this interconnecting construction: $C1=C_0+\underset{i}{\mathrm{\Σ}}\frac{\∂C_{\left(0\right)}}{\∂p_i}\·{\mathrm{\Δp}}_i+\underset{i}{\mathrm{\Σ}}\frac{{\∂}^2{C}_{\left(0\right)}}{\∂{p^2}_i}{\mathrm{\Δp}}_i^2+\underset{i\≠j}{\underset{i,j}{\mathrm{\Σ}}}\frac{{\∂}^2{C}_{\left(0\right)}}{\∂p_i\∂p_j}{\mathrm{\Δp}}_i{\mathrm{\Δp}}_j,$ The △ p in this formula _iall expand into (p _i-p _i0), p _i0for rated point size, obtain with p _ifor the second order stray capacitance base expression of variable;

When calculating stray capacitance with finite element field solver, the position of described calculation level and the choosing method of quantity are: in each design size valid parameter value, choose some values, according to design size number of parameters and selected value, corresponding orthogonal arrage in orthogonal experiment design method is adopted to choose calculation level; Adopt finite element field solver to calculate selected calculation level, obtain parasitic capacitance value C2;

Described error correction expression formula method for building up is as follows: in the second order stray capacitance base expression described in the described calculation level chosen by orthogonal arrage is substituted into, obtain stray capacitance initial value C1, and the parasitic capacitance value C2 that the electric capacity initial value C1 on identical calculations point and described use finite element field solver obtain is subtracted each other between two, obtain error amount △ C, △ C=C2-C1; By the design size parameter p of error amount △ C with its correspondence ₁, p ₂, p ₃... matching second order error innovation representation $\mathrm{\Δ}C=a_0+\underset{i}{\mathrm{\Σ}}{a}_i{p}_i+\underset{j}{\mathrm{\Σ}}{b}_j{p}_j^2+\underset{k\≠l}{\underset{k,l}{\mathrm{\Σ}}}{c}_{kl}{p}_k{p}_l,$ Obtain each coefficient a ₀, a _i, b _j, c _kl.