CN106154052A - The method for measurement of the parasitic capacitance of the metal routing of display floater - Google Patents
The method for measurement of the parasitic capacitance of the metal routing of display floater Download PDFInfo
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- CN106154052A CN106154052A CN201610567180.0A CN201610567180A CN106154052A CN 106154052 A CN106154052 A CN 106154052A CN 201610567180 A CN201610567180 A CN 201610567180A CN 106154052 A CN106154052 A CN 106154052A
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- metal routing
- parasitic capacitance
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- measurement
- display floater
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
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- Measurement Of Resistance Or Impedance (AREA)
Abstract
The present invention relates to the method for measurement of the parasitic capacitance of the metal routing of a kind of display floater.The method includes: step 10, provide first group of circuit layout, and it includes part of detecting and common portion, and this part of detecting comprises metal routing to be measured, and this common portion comprises lead-in wire and the measurement pad being connected with lead-in wire；Step 20, the measurement pad in this first group of circuit layout is utilized to measure first group of parasitic capacitance data；Step 30, providing second group of circuit layout, it only includes the common portion in this first group of circuit layout；Step 40, the measurement pad in this second group of circuit layout is utilized to measure second group of parasitic capacitance data；Step 50, by these first group of parasitic capacitance data and second group of corresponding parasitic capacitance subtracting each other to obtain corresponding metal routing of parasitic capacitance data.The present invention is applicable to the electric capacitance measurement of LTPS panel, it is possible to measures effective lateral electric capacity and overlap capacitance size between metal routing, designs the good reference value of offer for small-size product.
Description
Technical field
The present invention relates to field of liquid crystal, particularly relate to the amount of the parasitic capacitance of the metal routing of a kind of display floater
Survey method.
Background technology
Liquid crystal display (Liquid Crystal Display, LCD) have low in energy consumption, volume is little, the feature such as lightweight,
Therefore the favor of user is enjoyed.Along with the development of flat panel display technology, there are the need of the liquid crystal display of high-resolution, low energy consumption
Ask and be suggested.
Along with the development of low temperature polycrystalline silicon (LTPS) semiconductor thin-film transistor, and due to the superelevation of LTPS quasiconductor own
The characteristic of carrier mobility, corresponding panel periphery integrated circuit also becomes everybody focus of attention, and a lot of people puts into
The relation technological researching of the system integration on panel (System on Panel, SOP), and progressively become a reality.
Seeing Fig. 1 and Fig. 2, Fig. 1 is the metal routing design diagram in existing general small size LTPS panel, and Fig. 2 is
The equivalent schematic of parasitic capacitance between existing general small size LTPS panel metal routing.Design at undersized panel
Cheng Zhong, it is desirable to have WOA region and the design in GOA region.Wherein, WOA region is array cabling (Wire On Array) region,
Metal routing arrangement for chip (IC) to territory, effective display area (AA) and GOA region.GOA region is Array gate (Gate
On Array) region, produce grid displacement and drive signal for the driving of AA area pixel (Pixel).At WOA region and GOA
Region certainly exist some metal routings side by side and overlapping design, for the transmission of signal.Due to small size Display panel
The restriction of pattern, the electric capacity in its signal lead extracts and makes a big difference relative to large size panel.Wherein, metal routing
Lateral electric capacity and overlap capacitance are exactly the emphasis of small size panel design consideration, and lateral electric capacity and overlap capacitance are small size panel
The basic load that metal routing drives.Therefore, how to efficiently extract the parasitic capacitance of metal routing to become small size panel and set
The emphasis of meter.
From schematic diagram analysis, Fig. 1 can wait corresponding to the parasitic capacitance between each metal routing of numeral 1 to 9
Effect is for every metal routing respectively to the electric capacity of GND (ground wire), and parasitic capacitance is expressed as Ct1 extremely the most as shown in Figure 2
Ct9, effective measurement of every metal routing parasitic capacitance is then the emphasis of small size panel cabling design.
Summary of the invention
Therefore, it is an object of the invention to provide the method for measurement of the parasitic capacitance of the metal routing of a kind of display floater,
For effectively measuring the lateral electric capacity between metal routing or overlap capacitance size.
For achieving the above object, the present invention provides the method for measurement of the parasitic capacitance of the metal routing of a kind of display floater,
Including:
Step 10, providing first group of circuit layout, it includes part of detecting and common portion, and this part of detecting comprises the amount for the treatment of
The metal routing surveyed, this common portion comprises lead-in wire and the measurement pad being connected with lead-in wire；This lead-in wire and the measurement pad being connected
One_to_one corresponding is in this metal routing, and this lead-in wire one end connects corresponding metal routing, and other end connection measures pad accordingly；
Step 20, the measurement pad in this first group of circuit layout is utilized to measure first group of parasitic capacitance data；
Step 30, providing second group of circuit layout, it only includes the common portion in this first group of circuit layout；
Step 40, the measurement pad in this second group of circuit layout is utilized to measure second group of parasitic capacitance data；
Step 50, by corresponding with second group of parasitic capacitance data for these first group of parasitic capacitance data subtract each other to obtain corresponding
The parasitic capacitance of metal routing.
Wherein, the shape being shaped as this corresponding metal routing of one end that described lead-in wire is connected with corresponding metal routing
Naturally extend.
Wherein, described in metal routing to be measured be parallel metal routing, the parasitic capacitance of described metal routing is side
To electric capacity.
Wherein, described in metal routing to be measured be overlapping metal routing, the parasitic capacitance of described metal routing for hand over
Folded electric capacity.
Wherein, described display floater is LTPS panel.
Wherein, described lead-in wire includes connecting with corresponding metal routing and according to this corresponding metal routing shape extension
First parallel extending portions, connects the oblique line extension of this first parallel extending portions, and connects this oblique line extension
And second parallel extending portions parallel with this first parallel extending portions.
Wherein, metal routing to be measured described in is corresponding to the WOA region of this display floater.
Wherein, metal routing to be measured described in is corresponding to the GOA region of this display floater.
To sum up, the method for measurement of the parasitic capacitance of the metal routing of the display floater of the present invention is applicable to the electricity of LTPS panel
Capacity is surveyed, it is possible to measures effective lateral electric capacity and overlap capacitance size between metal routing, designs for small-size product and carry
For good reference value.
Accompanying drawing explanation
Below in conjunction with the accompanying drawings, by the detailed description of the invention of the present invention is described in detail, technical scheme will be made
And other beneficial effects are apparent.
In accompanying drawing,
Fig. 1 is the metal routing design diagram in existing general small size LTPS panel；
Fig. 2 is the equivalent schematic of parasitic capacitance between existing general small size LTPS panel metal routing；
Fig. 3 is the flow chart of the method for measurement of the parasitic capacitance of the metal routing of display floater of the present invention；
Fig. 4 is the circuit layout schematic diagram of lateral capacitance measurement between metal routing in the present invention the first preferred embodiment；
Fig. 5 is the equivalent circuit diagram of lateral capacitance measurement in the present invention the first preferred embodiment；
Fig. 6 is the circuit layout schematic diagram that in the present invention the second preferred embodiment, between metal routing, overlap capacitance is measured；
Fig. 7 is the equivalent circuit diagram that in the present invention the second preferred embodiment, overlap capacitance is measured.
Detailed description of the invention
Seeing Fig. 3, it is the flow chart of method for measurement of parasitic capacitance of metal routing of display floater of the present invention.The party
Method specifically includes that
Step 10, providing first group of circuit layout, it includes part of detecting and common portion, and this part of detecting comprises the amount for the treatment of
The metal routing surveyed, this common portion comprises lead-in wire and the measurement pad being connected with lead-in wire；This lead-in wire and the measurement pad being connected
One_to_one corresponding is in this metal routing, and this lead-in wire one end connects corresponding metal routing, and other end connection measures pad accordingly；
Step 20, the measurement pad in this first group of circuit layout is utilized to measure first group of parasitic capacitance data；
Step 30, providing second group of circuit layout, it only includes the common portion in this first group of circuit layout；
Step 40, the measurement pad in this second group of circuit layout is utilized to measure second group of parasitic capacitance data；
Step 50, by corresponding with second group of parasitic capacitance data for these first group of parasitic capacitance data subtract each other to obtain corresponding
The parasitic capacitance of metal routing.
Due to the restriction of small size Display panel pattern, the electric capacity in its signal lead (metal routing) extracts relative to greatly
Sized panel makes a big difference.Wherein, lateral electric capacity and the overlap capacitance of metal routing is exactly small size panel design consideration
Emphasis, lateral electric capacity and overlap capacitance be small size panel metal routing drive basic load.Therefore, the most effectively extract
The parasitic capacitance taking metal routing becomes the emphasis of small size panel design.Wherein, display floater can be LTPS panel.The amount for the treatment of
The metal routing surveyed can correspond to the WOA region of this display floater, it is also possible to corresponding to the GOA region of this display floater.Treat
The metal routing measured can be parallel metal routing, and the parasitic capacitance of metal routing is lateral electric capacity；Metal to be measured
Cabling can also be for overlapping metal routing, and the parasitic capacitance of metal routing is overlap capacitance.
Seeing Fig. 4 and Fig. 5, Fig. 4 is the electricity of lateral capacitance measurement between metal routing in the present invention the first preferred embodiment
Road layout design schematic diagram, Fig. 5 is the equivalent circuit diagram of lateral capacitance measurement in the present invention the first preferred embodiment.
For measuring lateral electric capacity, Fig. 4 respectively illustrates the gold provided in the present invention the first preferred embodiment up and down
Belong to first group and second group of two groups of circuit layouts design of the lateral capacitance measurement of cabling.The present invention is provided by two groups of layout design
Two groups of measuring point positions (Testkey).As shown in Figure 4, one group of measuring point position uses generally (Normal) design, test department subpackage
Containing parallel metal routing to be measured, common portion comprises lead-in wire and the measurement pad 1 being connected with lead-in wire ... 9.Lead-in wire is (tiltedly
Line region) with corresponding metal routing be connected one end the shape being shaped as this corresponding metal routing naturally extend, bag
Include the first parallel extending portions 11 connecting with corresponding metal routing and extending according to this corresponding metal routing shape, connect
The oblique line extension 12 of this first parallel extending portions, and connect this oblique line extension 12 and first extend in parallel with this
The second parallel extending portions 13 that part 11 is parallel.It is connected to measure pad (Pad) by lead-in wire from parallel metal routing, utilizes
Measure pad and carry out the measurement of lateral electric capacity between metal routing.Another group measuring point position does not carry out setting of parallel metal cabling
Meter, only hatched example areas (lead-in wire) and measurement pad area, utilizes measurement pad carry out hatched example areas and measure pad area parasitic capacitance
Measurement.The data that two groups of test point positions measure being analyzed, the capacitance data of first group of measuring point position measurement deducts
The capacitance data that second group of measuring point position measures, is i.e. the most lateral electric capacity between real parallel metal cabling.
The equivalent circuit diagram respectively illustrating in Fig. 4 first group and second group two groups of circuit layouts design up and down in Fig. 5.
From Fig. 5 analysis, the electric capacity of first group of measuring point position measurement is C (common portion)) and C (part of detecting, i.e. lateral electric capacity)
Sum, i.e. Ct1+Cc1, Ct2+Cc2 ... Ct9+Cc9, the electric capacity of second group of measuring point position measurement is C (common portion), i.e.
Cc1, Cc2 ... Cc9.First group of measuring point position metric data deducts second group of measuring point position metric data and is C (laterally electricity
Hold).
The layout design of the lateral electric capacity of metal routing that the present invention provides can effectively get rid of measurement pad area and oblique line
The impact of regional metal electric capacitance measurement lateral for parallel metal routing region, it is possible to measure between parallel signal cabling effective
Lateral capacitance size, for small-size product design offer good reference value.
Seeing Fig. 6 and Fig. 7, Fig. 6 is the electricity that in the present invention the second preferred embodiment, between metal routing, overlap capacitance is measured
Road layout design schematic diagram, Fig. 7 is the equivalent circuit diagram that in the present invention the second preferred embodiment, overlap capacitance is measured.
For measuring overlap capacitance, Fig. 6 respectively illustrates the gold provided in the present invention the second preferred embodiment up and down
Belong to first group and second group of two groups of circuit layouts design of the lateral capacitance measurement of cabling.The present invention is provided by two groups of layout design
Two groups of measuring point positions.As shown in Figure 6, one group of measuring point position uses and is commonly designed, and part of detecting comprises to be measured in cross
Overlapping metal routing, common portion comprises lead-in wire and the measurement pad 1,2 being connected with lead-in wire, and lead-in wire (hatched example areas) is with corresponding
Metal routing be connected one end the metal routing being shaped as this correspondence shape naturally extend, from overlapping metal routing
It is connected to measure pad by lead-in wire, utilizes measurement pad to carry out the measurement of overlap capacitance between metal routing.Another organizes measuring point position
Do not carry out the design of overlapping metal routing, only hatched example areas (lead-in wire) and measurement pad area, utilize measurement pad to carry out oblique line
Region and the measurement of measurement pad area parasitic capacitance.The data that two groups of test point positions measure are analyzed, first group of amount
The capacitance data that measuring point position measures deducts the capacitance data that second group of measuring point position measures, be i.e. overlap really metal routing it
Between effective parasitic capacitance.
The equivalent circuit diagram respectively illustrating in Fig. 6 first group and second group two groups of circuit layouts design up and down in Fig. 7.
From Fig. 6 analysis, the electric capacity that first group of measuring point position measures be C (common portion) and C (part of detecting, i.e. overlap capacitance) it
With, the electric capacity of second group of measuring point position measurement is C (common portion).First group of measuring point position metric data deducts second group of measurement
Point position metric data is C (overlap capacitance).
The layout design of the metal routing overlap capacitance that the present invention provides can effectively get rid of testing cushion region and oblique line
The impact that regional metal measures for overlapping metal routing region overlap capacitance, it is possible to measure between overlap signal cabling effective
Overlap capacitance size, for small-size product design offer good reference value.
Present invention can apply to:
1. thin film in liquid crystal display row scanning (Gate) drive circuit being integrated on array (Array) substrate and pixel
Transistor (TFT) designs；
2. mobile phone, display, the design field of TV；
3. contain LTPS TFT design field.
To sum up, the method for measurement of the parasitic capacitance of the metal routing of the display floater of the present invention is applicable to the electricity of LTPS panel
Capacity is surveyed, it is possible to measures effective lateral electric capacity and overlap capacitance size between metal routing, designs for small-size product and carry
For good reference value.
The above, for the person of ordinary skill of the art, can be according to technical scheme and technology
Other various corresponding changes and deformation are made in design, and all these change and deformation all should belong to the appended right of the present invention
The protection domain required.
Claims (8)
1. the method for measurement of the parasitic capacitance of the metal routing of a display floater, it is characterised in that including:
Step 10, providing first group of circuit layout, it includes part of detecting and common portion, and this part of detecting comprises to be measured
Metal routing, this common portion comprises lead-in wire and the measurement pad being connected with lead-in wire；This lead-in wire and the measurement pad that is connected are one by one
Corresponding to this metal routing, this lead-in wire one end connects corresponding metal routing, and other end connection measures pad accordingly；
Step 20, the measurement pad in this first group of circuit layout is utilized to measure first group of parasitic capacitance data；
Step 30, providing second group of circuit layout, it only includes the common portion in this first group of circuit layout；
Step 40, the measurement pad in this second group of circuit layout is utilized to measure second group of parasitic capacitance data；
Step 50, these first group of parasitic capacitance data is obtained corresponding metal with second group of corresponding subtracting each other of parasitic capacitance data
The parasitic capacitance of cabling.
2. the method for measurement of the parasitic capacitance of the metal routing of display floater as claimed in claim 1, it is characterised in that described
Naturally extending of the shape being shaped as this corresponding metal routing of one end that lead-in wire is connected with corresponding metal routing.
3. the method for measurement of the parasitic capacitance of the metal routing of display floater as claimed in claim 1, it is characterised in that described
Metal routing to be measured is parallel metal routing, and the parasitic capacitance of described metal routing is lateral electric capacity.
4. the method for measurement of the parasitic capacitance of the metal routing of display floater as claimed in claim 1, it is characterised in that described
Metal routing to be measured is overlapping metal routing, and the parasitic capacitance of described metal routing is overlap capacitance.
5. the method for measurement of the parasitic capacitance of the metal routing of display floater as claimed in claim 1, it is characterised in that described
Display floater is LTPS panel.
6. the method for measurement of the parasitic capacitance of the metal routing of display floater as claimed in claim 3, it is characterised in that described
Lead-in wire includes the first parallel extending portions connecting with corresponding metal routing and extending according to this corresponding metal routing shape,
Connect the oblique line extension of this first parallel extending portions, and connect this oblique line extension and first extend in parallel with this
The second parallel extending portions that part is parallel.
7. the method for measurement of the parasitic capacitance of the metal routing of display floater as claimed in claim 1, it is characterised in that described
Metal routing to be measured is corresponding to the WOA region of this display floater.
8. the method for measurement of the parasitic capacitance of the metal routing of display floater as claimed in claim 1, it is characterised in that described
Metal routing to be measured is corresponding to the GOA region of this display floater.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610567180.0A CN106154052A (en) | 2016-07-18 | 2016-07-18 | The method for measurement of the parasitic capacitance of the metal routing of display floater |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610567180.0A CN106154052A (en) | 2016-07-18 | 2016-07-18 | The method for measurement of the parasitic capacitance of the metal routing of display floater |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106680591A (en) * | 2016-12-21 | 2017-05-17 | 北京集创北方科技股份有限公司 | Touch control display panel detection circuit and detection method |
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| CN102243275A (en) * | 2011-04-25 | 2011-11-16 | 上海宏力半导体制造有限公司 | Measuring method for parasitic capacitance in capacitance DC (direct current) model |
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| CN103164572A (en) * | 2013-02-22 | 2013-06-19 | 中国科学院电工研究所 | Modeling method of integrated circuit interconnecting wire stray capacitance |
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| CN106680591A (en) * | 2016-12-21 | 2017-05-17 | 北京集创北方科技股份有限公司 | Touch control display panel detection circuit and detection method |
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Application publication date: 20161123 |