CN104465432A - Structure for monitoring stray capacitance - Google Patents
Structure for monitoring stray capacitance Download PDFInfo
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- CN104465432A CN104465432A CN201310438663.7A CN201310438663A CN104465432A CN 104465432 A CN104465432 A CN 104465432A CN 201310438663 A CN201310438663 A CN 201310438663A CN 104465432 A CN104465432 A CN 104465432A
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- parasitic capacitance
- dielectric layer
- monitoring
- semiconductor device
- grid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a structure for monitoring stray capacitance. In the structure for monitoring stray capacitance, a semiconductor device is formed on a dielectric layer. The semiconductor device comprises a gate dielectric layer, a gate, a side wall and an inner connecting wire. The side wall separates the gate and the inner connecting wire. The semiconductor device is formed on the dielectric layer so that the stray capacitance between the gate and the inner connecting wire can be accurately monitored, and then the problem that the performance of the semiconductor device is affected due to the fact that stray capacitance is too high can be avoided.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of structure of monitoring parasitic capacitance.
Background technology
In the process that semiconductor device manufactures; the performance test that those skilled in the art can be correlated with to semiconductor device usually; such as monitor grid and connecting line in semiconductor device, parasitic capacitance etc. between grid and intraconnections, to guarantee that the semiconductor device produced meets technological requirement.If parasitic capacitance is excessive in semiconductor device, then the reaction speed of semiconductor device can be caused lower, tackle corresponding technique and be optimized.
Please refer to Fig. 1, semiconductor device comprises: Semiconductor substrate 10; Be formed at the fleet plough groove isolation structure 20 in Semiconductor substrate 10; Be formed at gate dielectric layer 31 and the grid 32 on described Semiconductor substrate 10 surface successively; Be formed at the side wall 33 of described gate dielectric layer 31 and grid 32 two side; To be formed in described Semiconductor substrate 10 and to be positioned at the source/drain 40 of described side wall 33 both sides; Be formed at described side wall both side surface and be positioned at the intraconnections 50 on fleet plough groove isolation structure 20 and Semiconductor substrate 10 surface; And be formed at the connecting line 60 on described intraconnections 50 and grid 32 surface.
In traditional handicraft, semiconductor device does not form intraconnections 50, however along with dimensions of semiconductor devices continue reduce, in order to the density that can improve semiconductor device in unit are then needs to increase certain intraconnections 50.The increase of intraconnections 50, can improve the density of semiconductor device in unit are, also can cause the increase of semiconductor device endoparasitism electric capacity simultaneously.Such as, the parasitic capacitance formed between intraconnections 50 and grid 32.
But, owing to there is no intraconnections 50 in the semiconductor device in traditional handicraft, there is not the structure that parasitic capacitance between intraconnections 50 and grid 32 is monitored yet, therefore the parasitic capacitance formed between intraconnections 50 and grid 32 how is monitored, avoid the excessive performance affecting semiconductor device of parasitic capacitance, just become the technical problem that those skilled in the art are badly in need of solving.
Summary of the invention
The object of the present invention is to provide a kind of structure of monitoring parasitic capacitance, the parasitic capacitance between grid and intraconnections can be monitored out accurately.
To achieve these goals, the present invention proposes a kind of structure of monitoring parasitic capacitance, comprising:
Dielectric layer;
Be formed at the semiconductor device on described dielectric layer; Wherein, described semiconductor device comprises the gate dielectric layer and grid that are formed at described dielectric layer surface successively, is formed at the side wall of described gate dielectric layer and grid both sides, is formed at described side wall two sides and is positioned at the intraconnections of described dielectric layer surface;
And be formed at the connecting line of described intraconnections and gate surface.
Further, the structure of described monitoring parasitic capacitance also comprises Semiconductor substrate, and described dielectric layer is formed in described Semiconductor substrate.
Further, the material of described dielectric layer is silica.
Further, the material of described Semiconductor substrate is silicon.
Further, the number of described semiconductor device is more than or equal to 1.
Further, the material of described gate dielectric layer is silicon dioxide.
Further, the material of described grid is polysilicon.
Further, the material of described side wall is silicon nitride or silicon dioxide.
Further, the structure of described monitoring parasitic capacitance also comprises the metal wire be formed on described connecting line, and described metal wire is connected with described connecting line.
Further, the material of described metal wire is copper.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: in the structure of monitoring parasitic capacitance, form semiconductor device on described dielectric layer, described semiconductor device comprises gate dielectric layer, grid, side wall and intraconnections, described side wall isolates described grid and intraconnections, because described semiconductor device is formed on described dielectric layer, thus the parasitic capacitance can monitored out accurately between described grid and intraconnections, and then the excessive performance affecting semiconductor device of parasitic capacitance can be avoided.
Accompanying drawing explanation
Fig. 1 is the structural representation of semiconductor device;
Fig. 2 is the front view of the structure of monitoring parasitic capacitance in one embodiment of the invention;
Fig. 3 is the structural profile schematic diagram of monitoring parasitic capacitance in one embodiment of the invention.
Embodiment
Be described in more detail below in conjunction with the structure of schematic diagram to monitoring parasitic capacitance of the present invention, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2 and Fig. 3, in the present embodiment, propose a kind of structure of monitoring parasitic capacitance, comprising:
Semiconductor substrate 100 and dielectric layer 200; Described dielectric layer 200 is formed in Semiconductor substrate 100, and the material of described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or silicon-on-insulator; The material of described dielectric layer 200 is silica, is the known fleet plough groove isolation structure of industry (STI), and chemical vapour deposition (CVD) mode can be taked to be formed;
Be formed at the semiconductor device 800 on described dielectric layer 200; Wherein, described semiconductor device 800 comprises the gate dielectric layer 310 and grid 320 that are formed at described dielectric layer 200 surface successively, be formed at the side wall 330 of described gate dielectric layer 310 and grid 320 both sides, be formed at the two sides of described side wall 330 and be positioned at the intraconnections 500 on described dielectric layer 200 surface;
The number of described semiconductor device 800 is more than or equal to 1, and the number of described semiconductor device 800 is more, more can accurately monitor out the value of parasitic capacitance, and concrete number can be selected according to different process; The material of described gate dielectric layer 310 is silicon dioxide, and the material of described grid 320 is polysilicon; The material of described side wall 320 can be silicon nitride or silicon dioxide, also can be both combinations; The material of described intraconnections 500 is polysilicon; The surface described semiconductor device 800 being formed in described dielectric layer 200 is that the parasitic capacitance between the grid 320 that causes measuring of the surface in order to avoid being formed in the Semiconductor substrate 100 being similarly conductor and intraconnections 500 is inaccurate, simultaneously, due to need not source/drain be formed in described dielectric layer 200, source/drain also can be avoided the impact of the parasitic capacitance monitoring between grid 320 and intraconnections 500;
And be formed at the connecting line 600 on described intraconnections 500 and grid 320 surface;
Wherein, after formation connecting line 600, described connecting line is formed metal wire 700, and described metal wire 700 is connected with described connecting line 600, and be convenient to the follow-up structure to described monitoring parasitic capacitance and monitor, the material of wherein said metal wire 700 is copper.
When carrying out monitoring leakage current or junction capacitance to the structure of monitoring parasitic capacitance, monitoring method belongs to the common practise in art technology, and those skilled in the art should know, and therefore, does not repeat them here monitoring method.
To sum up, in the structure of the monitoring parasitic capacitance provided in the embodiment of the present invention, Semiconductor substrate described in the structure of monitoring parasitic capacitance forms grid unit, grid unit is identical with the grid structure of semiconductor device, make the domain semiconductor device structure of monitoring parasitic capacitance similar, thus the impact on joint leakage current and junction capacitance of grid, shallow doped region and source/drain can be monitored out accurately.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (11)
1. monitor a structure for parasitic capacitance, comprising:
Dielectric layer;
Be formed at the semiconductor device on described dielectric layer; Wherein, described semiconductor device comprises the gate dielectric layer and grid that are formed at described dielectric layer surface successively, is formed at the side wall of described gate dielectric layer and grid both sides, is formed at described side wall two sides and is positioned at the intraconnections of described dielectric layer surface; And be formed at the connecting line of described intraconnections and gate surface.
2. the structure of monitoring parasitic capacitance as claimed in claim 1, it is characterized in that, the structure of described monitoring parasitic capacitance also comprises Semiconductor substrate, and described dielectric layer is formed in described Semiconductor substrate.
3. the structure of monitoring parasitic capacitance as claimed in claim 2, it is characterized in that, the material of described dielectric layer is silica.
4. the structure of monitoring parasitic capacitance as claimed in claim 3, it is characterized in that, the material of described Semiconductor substrate is silicon.
5. the structure of monitoring parasitic capacitance as claimed in claim 1, it is characterized in that, the number of described semiconductor device is more than or equal to 1.
6. the structure of monitoring parasitic capacitance as claimed in claim 1, it is characterized in that, the material of described gate dielectric layer is silicon dioxide.
7. the structure of monitoring parasitic capacitance as claimed in claim 1, it is characterized in that, the material of described grid is polysilicon.
8. the structure of monitoring parasitic capacitance as claimed in claim 1, it is characterized in that, the material of described intraconnections is polysilicon.
9. the structure of monitoring parasitic capacitance as claimed in claim 1, it is characterized in that, the material of described side wall is silicon nitride or silicon dioxide.
10. the structure of monitoring parasitic capacitance as claimed in claim 1, it is characterized in that, the structure of described monitoring parasitic capacitance also comprises the metal wire be formed on described connecting line, and described metal wire is connected with described connecting line.
The structure of 11. monitoring parasitic capacitances as claimed in claim 10, it is characterized in that, the material of described metal wire is copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310438663.7A CN104465432A (en) | 2013-09-23 | 2013-09-23 | Structure for monitoring stray capacitance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310438663.7A CN104465432A (en) | 2013-09-23 | 2013-09-23 | Structure for monitoring stray capacitance |
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| CN104465432A true CN104465432A (en) | 2015-03-25 |
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| CN201310438663.7A Pending CN104465432A (en) | 2013-09-23 | 2013-09-23 | Structure for monitoring stray capacitance |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154052A (en) * | 2016-07-18 | 2016-11-23 | 武汉华星光电技术有限公司 | The method for measurement of the parasitic capacitance of the metal routing of display floater |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050030057A1 (en) * | 2003-08-04 | 2005-02-10 | Kwang-Il Kim | Semiconductor test device using leakage current and compensation system of leakage current |
| CN1677614A (en) * | 2004-03-31 | 2005-10-05 | 夏普株式会社 | Semiconductor device, electrical inspection method thereof, and electronic apparatus including the semiconductor device |
| US20050260776A1 (en) * | 2004-05-19 | 2005-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for extraction of parasitic junction capacitance in deep submicron technology |
| CN101770965A (en) * | 2008-12-31 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Testing structure and testing method of capacitance between contact hole and grid |
| CN102299095A (en) * | 2010-06-22 | 2011-12-28 | 中国科学院微电子研究所 | Inter-layer dielectric layer and manufacturing method thereof as well as semiconductor device with dielectric layer |
| CN103137605A (en) * | 2011-12-02 | 2013-06-05 | 上海华虹Nec电子有限公司 | Test structure and manufacturing method of monitoring leakage source polycrystalline silicon and pipe side wall stray capacitance |
-
2013
- 2013-09-23 CN CN201310438663.7A patent/CN104465432A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050030057A1 (en) * | 2003-08-04 | 2005-02-10 | Kwang-Il Kim | Semiconductor test device using leakage current and compensation system of leakage current |
| CN1677614A (en) * | 2004-03-31 | 2005-10-05 | 夏普株式会社 | Semiconductor device, electrical inspection method thereof, and electronic apparatus including the semiconductor device |
| US20050260776A1 (en) * | 2004-05-19 | 2005-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for extraction of parasitic junction capacitance in deep submicron technology |
| CN101770965A (en) * | 2008-12-31 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Testing structure and testing method of capacitance between contact hole and grid |
| CN102299095A (en) * | 2010-06-22 | 2011-12-28 | 中国科学院微电子研究所 | Inter-layer dielectric layer and manufacturing method thereof as well as semiconductor device with dielectric layer |
| CN103137605A (en) * | 2011-12-02 | 2013-06-05 | 上海华虹Nec电子有限公司 | Test structure and manufacturing method of monitoring leakage source polycrystalline silicon and pipe side wall stray capacitance |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154052A (en) * | 2016-07-18 | 2016-11-23 | 武汉华星光电技术有限公司 | The method for measurement of the parasitic capacitance of the metal routing of display floater |
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Application publication date: 20150325 |