CN104752403B - A kind of test structure and its manufacture method - Google Patents
A kind of test structure and its manufacture method Download PDFInfo
- Publication number
- CN104752403B CN104752403B CN201310729232.6A CN201310729232A CN104752403B CN 104752403 B CN104752403 B CN 104752403B CN 201310729232 A CN201310729232 A CN 201310729232A CN 104752403 B CN104752403 B CN 104752403B
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor substrate
- test structure
- hard mask
- shallow trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention provides a kind of test structure and its manufacture method, is related to technical field of semiconductors.This method includes：S101：First Semiconductor substrate and the second Semiconductor substrate disposed thereon are provided, form hard mask layer；102：Hard mask layer is patterned, the second Semiconductor substrate performed etching using patterned hard mask layer to form groove and the fin structure between groove；S103：Shallow trench isolation is formed in groove；S104：Remove certain thickness shallow trench to isolate so that its height be less than fin structure, and removes the part that hard mask layer is located on fin structure, reservation hard mask layer is located at part outside fin structure region as isolation structure；S105：Covering fin structure and the high k dielectric layer and metal gates of shallow trench isolation are formed between isolation structure.The test structure for testing CV curves can be more easily made in this method.The test structure can relatively easily measure CV curves, and then obtain the work function of metal gates.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of test structure and its manufacture method.
Background technology
In technical field of semiconductors, with the continuous development of semiconductor technology, to obtain higher device density, efficiency
With relatively low cost, the manufacture of semiconductor devices often uses three dimensional design, for example with fin field-effect transistor (fin
Field effect transistor, below can abbreviation FinFET).In addition, in order to improve the performance of semiconductor devices, high k gold
Category gate technique also begins to obtain more and more extensive application.
Currently, increasing semiconductor manufacturing manufacturer starts to use high-k/metal gate technology and fin field effect simultaneously
Transistor technology manufactures semiconductor devices, and in obtained semiconductor devices, used transistor is high-k/metal gate fin
Type field-effect transistor.It is well known that how quickly and accurately to obtain the metal of high-k/metal gate fin FET
The work function of grid, the exploitation for semiconductor devices are most important.However, there is no but one kind to can be used for obtaining metal at present
The effective method of the work function of grid.
In the prior art, there is a kind of method can be based on the relation between the parameter such as work function and electric capacity, voltage（Mainly
Including following equilibrium relationships： Vfb=φm-φsi, φm=
Vfb+φsi,AndWherein, CtotalFor unit area
Total capacitance；CoxFor the electric capacity of unit area oxide layer；CsiFor the electric capacity of unit area silicon substrate；CfbFor flatband capacitanse；VfbIt is flat
It is with voltage；εsiFor the dielectric constant of silicon substrate；LDDistance between substrate；Q is electronic charge；NaFor substrate doping density；K is
Boltzmann constant；T is thermodynamic temperature；φmFor the work function of metal gates；φsiFor the work function of silicon substrate；χ is electronics parent
And power, generally 4.05；EgFor energy gap width；ψBFor fermi level and the energy difference of intrinsic level；niFor intrinsic carrier concentration）,
With reference to capacitance voltage curves as shown in Figure 4（CV curves）, extract the work function of a certain material.Specifically, this method is included such as
Lower content：（1）ByUnderstandWillSubstitute intoAnd
The concrete numerical value of each parameter is substituted into, then can calculate Cfb；（2）Obtaining CfbAfterwards, according to capacitance voltage as shown in Figure 4
Curve（CV curves）Obtain Vfb；（3）By Vfb=φm-φsiUnderstand φm=Vfb+φsi, andAlso, χ mono-
As be 4.05,Generally 0.56,It can then obtain
By VfbAnd the numerical value of other specification substitutes into equationφ can then be calculatedm
Value.That is, according to above-mentioned equation and CV curves, the work function φ of metal gates can be obtainedm。
Obviously, the work function of metal gates is obtained according to the above method of the prior art, only need to obtain corresponding electric capacity
Voltage curve, in conjunction with above-mentioned equation and each known parameters.However, to obtain capacitance voltage curves, it is necessary to have phase
The test structure answered；In the prior art, and in the absence of one kind can be used for obtaining high-k/metal gate fin FET
Metal gates work function test structure.
Therefore, it is solution problem above, it is necessary to propose a kind of new test structure and its manufacture method.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of test structure and its manufacture method.
The embodiment of the present invention one provides a kind of manufacture method of test structure, including：
Step S101：There is provided includes the composite semiconductor of the first Semiconductor substrate and the second Semiconductor substrate disposed thereon
Substrate, hard mask layer is formed in second Semiconductor substrate；
Step S102：The hard mask layer is patterned, using through the patterned hard mask layer to described
Two Semiconductor substrates are performed etching to form groove and the fin structure between the groove；
Step S103：Shallow trench isolation is formed in the groove；
Step S104：The certain thickness shallow trench is removed to isolate so that its height is less than the fin structure, and goes
Except the hard mask layer is located at the part on the fin structure, retains the hard mask layer and be located at where the fin structure
Part outside region is as isolation structure；
Step S105：The high k for covering the fin structure and shallow trench isolation is formed between the isolation structure
Dielectric layer and the metal gates on the high k dielectric layer.
Wherein, first Semiconductor substrate is P+ Semiconductor substrates, and/or, second Semiconductor substrate is P- half
Conductor substrate.
Alternatively, the hard mask layer is the double-decker being made up of oxide skin(coating) and silicon nitride layer disposed thereon.
Alternatively, the material of the shallow trench isolation is oxide.
Alternatively, in the step S102, the method being patterned to the hard mask layer includes：
Step S1021：Advanced pattern material layer is formed on the hard mask layer；
Step S1022：The advanced pattern material layer is patterned, through the patterned advanced pattern material
Disposable spacer material and performed etching between the pattern of layer to form wall, remove the advanced pattern material layer；
Step S1023：The hard mask layer is patterned using the wall.
Alternatively, step S1045 is included between the step S104 and the step S105：Carry out chamfering and damage is released
Put processing.
Alternatively, in the step S105, before the high k dielectric layer is formed, formed and cover the fin structure
And the boundary layer of the shallow trench isolation.
Alternatively, in the step S105, the high k dielectric layer also covers the inside side walls of the isolation structure.
The embodiment of the present invention two provides a kind of test structure, including：First Semiconductor substrate, positioned at first semiconductor
Second Semiconductor substrate of substrate, high k dielectric layer on second Semiconductor substrate and positioned at the high k
Metal gates on dielectric layer, wherein, second Semiconductor substrate has fin structure and positioned at the fin structure
The height of both sides is isolated less than the shallow trench of the fin structure, and the high k dielectric layer covers the fin structure and described
Shallow trench is isolated.
Alternatively, first Semiconductor substrate is P+ Semiconductor substrates, and/or, second Semiconductor substrate is P-
Semiconductor substrate.
Alternatively, the material of the shallow trench isolation is oxide.
Alternatively, the test structure also includes the boundary layer for covering the fin structure and shallow trench isolation,
The boundary layer is located at the lower section of the high k dielectric layer.
Alternatively, the test structure also includes：Between the high k dielectric layer and the metal gates from lower and
On high the k cap and work-function layer that stack gradually.
Alternatively, the test structure also includes being formed on second Semiconductor substrate and being located at the fin knot
Isolation structure outside structure region, wherein, the high k dielectric layer and the metal gates be located at the isolation structure it
Between.
Alternatively, the isolation structure is the double-decker being made up of oxide skin(coating) and silicon nitride layer disposed thereon.
Alternatively, the high k dielectric layer also covers the inside side walls of the isolation structure.
The manufacture method of the test structure of the present invention, can more easily be made the test knot for testing CV curves
Structure, and then the work function for obtaining metal gates can be relatively easy to.The test structure of the present invention, including the first semiconductor lining
Bottom, metal gates and formation positioned there between have the second Semiconductor substrate of fin structure and high k dielectric layer, their structures
Into a capacity plate antenna structure, therefore, the CV curves of the test structure can be relatively easily measured, and then obtain metal gates
Work function.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 K are that a kind of committed step of the manufacture method for test structure that the embodiment of the present invention one proposes is formed
The schematic diagram of figure；Wherein, Figure 1A -1,1B-1,1C-1,1D-1,1E-1,1F-1,1G-1,1H-1,1I-1,1J-1 and 1K-1 are
Top view, Figure 1A -2,1B-2,1C-2,1D-2,1E-2,1F-2,1G-2,1H-2,1I-2,1J-2 and 1K-2 are to be overlooked along corresponding
The sectional view of XX ' lines in figure；
Fig. 2 is a kind of typical flowchart of the manufacture method for test structure that the embodiment of the present invention one proposes；
Fig. 3 is a kind of schematic figure for test structure that the embodiment of the present invention two proposes, wherein Fig. 3 A are top view, Fig. 3 B
For the sectional view of the XX ' lines along Fig. 3 A；
Fig. 4 is a kind of schematic diagram of capacitance voltage curves of the prior art.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore,
Embodiments of the invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as that the injection region of rectangle generally has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this
Invention can also have other embodiment.
Embodiment one
Below, reference picture 1A- Fig. 1 K and Fig. 2 come describe the embodiment of the present invention proposition semiconductor devices manufacture method one
The detailed step of individual illustrative methods.Figure 1A-Fig. 1 K are a kind of key of the manufacture method of test structure of the embodiment of the present invention
The schematic figure for the figure that step is formed；Wherein, Figure 1A -1,1B-1,1C-1,1D-1,1E-1,1F-1,1G-1,1H-1,1I-1,
1J-1 and 1K-1 is top view, Figure 1A -2,1B-2,1C-2,1D-2,1E-2,1F-2,1G-2,1H-2,1I-2,1J-2 and 1K-2
For sectional view of the corresponding top view along XX ' lines；Fig. 2 is a kind of typical case of the manufacture method of test structure of the embodiment of the present invention
Flow chart.
The manufacture method of the test structure of the present embodiment, comprises the following steps：
Step A1：There is provided includes compound the half of the first Semiconductor substrate 101 and the second Semiconductor substrate 102 disposed thereon
Conductor substrate, as shown in Figure 1A；In second Semiconductor substrate 102 formed hard mask layer 103, hard mask layer 103 it
It is upper to form advanced pattern material layer（Advanced pattern film, APF）104, as shown in Figure 1B.
Exemplarily, the first Semiconductor substrate 101 is P+ Semiconductor substrates, and the second Semiconductor substrate 102 is P- semiconductors
Substrate.Advanced pattern material layer（APF）104 are generally amorphous carbon.
Hard mask layer 103 can be single layer structure or sandwich construction, and exemplarily, hard mask layer 103 includes oxide skin(coating)
1031 and silicon nitride layer 1032 disposed thereon, as shown in Figure 1B.
Wherein, the method for forming the first Semiconductor substrate 101 and the second Semiconductor substrate 102, can be epitaxial growth method
Or other suitable methods.The method for forming hard mask layer 103, can be sedimentation or other suitable methods.Formed advanced
Pattern material layer（APF）104, it is sedimentation or other suitable methods.
Step A2：To advanced pattern material layer（APF）104 are patterned, and form patterned advanced pattern material layer
（APF）104 ', as shown in Figure 1 C.In the patterned advanced pattern material layer（APF）Disposable spacer between 104 ' pattern
Material is simultaneously performed etching to form wall 105, removes the patterned advanced pattern material layer 104 ', as shown in figure iD.
Wherein, the material of wall 105 is generally silicon nitride or other suitable materials.
Step A3：Hard mask layer 103 is patterned using wall 105, is with patterned hard mask layer 103 '
Mask performs etching to the second Semiconductor substrate 102, groove 1021 is formed in the second Semiconductor substrate 102 and positioned at groove
Fin structure between 1021（Fin）1022, retain patterned hard mask layer 103 ', as referring to figure 1E.
Wherein, fin structure 1022 can be one or more, and multiple fin structures are shown in Fig. 1 E.With multiple
In the embodiment of fin structure, size, the shape of each fin structure be able to can also be differed with identical.
Exemplarily, patterned hard mask layer 103 ' includes patterned oxide skin(coating) 1031 ' and figure disposed thereon
The silicon nitride layer 1032 ' of shape, as referring to figure 1E.
Step A4：Shallow trench isolation is formed in the groove 1021（STI）106, as shown in fig. 1F.
Exemplarily, forming the method for shallow trench isolation 106 includes：In the groove 1021 and the groove 1021
Top filling isolated material；The isolated material being located on the patterned hard mask layer 103 ' is removed with shape by CMP
Isolate into shallow trench（STI）106.Wherein, the isolated material can be oxide or other suitable materials.
Step A5：Remove certain thickness shallow trench isolation（STI）1060, and remove the patterned hard mask layer
103 ' the part on fin structure 1022, retain the patterned hard mask layer 103 ' and be located at the institute of fin structure 1022
Part outside region is as isolation structure 10301, as shown in Figure 1 I.
Exemplarily, it is hard to include the first hard mask layer 1031 ' and disposed thereon second for patterned hard mask layer 103 '
Mask layer 1032 ', step A5 can include：
Step A51：Remove shallow trench isolation（STI）106 are higher than the part of the first hard mask layer 1031 ', as shown in Figure 1 G.
The method of removal, can be wet etching or other suitable methods.
Step A52：The part that the second hard mask layer 1032 ' is located on fin structure 1022 is removed, retains second and covers firmly
Film layer 1032 ' is located at the part outside the region of fin structure 1022, as shown in fig. 1H.
Step A53：The part that the first hard mask layer 1031 ' is located on fin structure 1022 is removed, retains first and covers firmly
Film layer 1031 ' is located at the part outside the region of fin structure 1022, and removes certain thickness shallow trench isolation（STI）
106, as shown in Figure 1 I.
Exemplarily, it is less than fin structure 1022 by step A5, the height of the remainder of shallow trench isolation 106, such as
Shown in Fig. 1 I.In the present embodiment, when the material of shallow trench isolation 1060 is oxide, shallow trench isolates 106 remainder
Can be as the boundary layer for being subsequently formed structure.Also, when the first hard mask layer 1031 ' is oxide, the first hard mask layer
It can retain a part in step A51 with part of the shallow trench isolation on fin structure 1022, it is complete to be formed
Cover the boundary layer of fin structure 1022.
Step A6：Carry out chamfering（corner rounding）Discharged with damage（damage release）Processing, such as Fig. 1 J
It is shown.
The step can using it is of the prior art it is various it is feasible by the way of realize, here is omitted.Pass through the step
Suddenly, it is ensured that the structure being subsequently formed has better performance.It is to be understood that in order to brief, Fig. 1 J do not show that
The change of two Semiconductor substrates 102 and other assemblies after the treatment.Also, step A6 can be omitted.
Step A7：The high k dielectric layer 107 of the remainder 106 of covering fin structure 1022 and shallow trench isolation is formed,
And the metal gates 108 formed on the high k dielectric layer 107 between the isolation structure 10301, such as Fig. 1 K institutes
Show.
Exemplarily, the method for forming high k dielectric layer is deposition.Formed metal gates 108 method be：In isolation structure
Metal material is filled between 10301, and passes through CMP（Chemically mechanical polishing）It is unnecessary on isolation structure 10301 to remove
Metal material.
In the present embodiment, high k dielectric layer 107 can also cover the close fin structure of isolation structure 10301 simultaneously
1022 side wall.Now high k dielectric layer can preferably isolating metal grid 108, therefore have superior technique effect.
In this step, before high k dielectric layer is formed, boundary layer can also be formed；After high k dielectric layer is formed,
Before metal gates 108, high k cap and the work-function layer on high k cap can also be formed.Wherein, high k lids
Cap layers are generally TiN and TaN, and the material of metal gates 108 is generally aluminium or tungsten.That is, in the present embodiment, most end form
Into gate stack structure can include successively from bottom to top：Boundary layer, high k dielectric layer, high k cap, work-function layer, metal
Grid.
In addition it is also necessary to explain, in various embodiments of the present invention, Figure 1A -2,1B-2,1C-2,1D-2,1E-2,1F-
2nd, the sectional view such as 1G-2,1H-2,1I-2,1J-2 and 1K-2 and Figure 1A -1,1B-1,1C-1,1D-1,1E-1,1F-1,1G-1,1H-
1st, the top view such as 1I-1,1J-1 and 1K-1 might not correspond to completely, and each sectional view can be one along the sectional view of XX ' lines
Part.
So far, the introduction of the manufacture method of the test structure of the embodiment of the present invention is completed.With it, it can compare
The test of the work function of the metal gates for obtaining high-k/metal gate fin FET cmos device is easily made
Structure.
Test structure made from the manufacture method of test structure according to embodiments of the present invention, including the first semiconductor lining
Bottom, metal gates and formation positioned there between have the second Semiconductor substrate of fin structure and high k dielectric layer, their structures
Into a capacity plate antenna structure（Second Semiconductor substrate is bottom electrode, metal gates are Top electrode）, therefore, can be easy to survey
Obtain the capacitance voltage curves of the test structure（CV curves）, and then obtain the work function of metal gates.According to embodiments of the present invention
Test structure manufacture method, the test structure for testing CV curves can more easily be made, and then can compare
Readily obtain the work function of metal gates.
Reference picture 2, a kind of flow chart of typical method in the manufacture method of test proposed by the present invention is illustrated therein is,
For schematically illustrating the flow of whole manufacturing process.
Step S101：There is provided includes the composite semiconductor of the first Semiconductor substrate and the second Semiconductor substrate disposed thereon
Substrate, hard mask layer is formed in second Semiconductor substrate；
Step S102：The hard mask layer is patterned, using through the patterned hard mask layer to described
Two Semiconductor substrates are performed etching to form groove and the fin structure between the groove；
Step S103：Shallow trench isolation is formed in the groove；
Step S104：The certain thickness shallow trench is removed to isolate so that its height is less than the fin structure, and goes
Except the hard mask layer is located at the part on the fin structure, retains the hard mask layer and be located at where the fin structure
Part outside region is as isolation structure；
Step S105：The high k for covering the fin structure and shallow trench isolation is formed between the isolation structure
Dielectric layer and the metal gates on the high k dielectric layer.
Embodiment two
The embodiment of the present invention provides a kind of test structure, can be used for obtaining using high-k/metal gate fin field effect crystalline substance
The work function of the metal gates of the semiconductor devices of body pipe.The test structure, it can be made by the method described in embodiment one.
Below, reference picture 3 introduces the test structure of the present embodiment, and wherein Fig. 3 A are the top view of the test structure, figure
3B is the sectional view of the XX ' lines along Fig. 3 A.As shown in figure 3, the test structure of the present embodiment includes：First Semiconductor substrate 101,
The second Semiconductor substrate 102 on the first Semiconductor substrate 101, on second Semiconductor substrate 102
High k dielectric layer 107 and the metal gates 108 on the high k dielectric layer, wherein, second Semiconductor substrate 102
With at least one fin structure（Fin）1022, the high k dielectric layer 107 covers top surface and the side of the fin structure 1022
Wall and the shallow trench of the both sides of the fin structure 1022 isolation 106, shallow trench isolates 106 height and is less than fin structure 1022.
Wherein, the first Semiconductor substrate 101, the second Semiconductor substrate 102, high k dielectric layer 107 and metal gates 108
A capacity plate antenna structure is formed, the first Semiconductor substrate 101 and metal gates 108 are respectively the Top electrode of the capacity plate antenna
And bottom electrode.
Exemplarily, the first Semiconductor substrate 101 is P+ Semiconductor substrates, and the second Semiconductor substrate 102 is P- semiconductors
Substrate.
Further, the test structure also includes the isolation structure 10301 positioned at the both sides of metal gates 108, institute
Isolation structure 10301 is stated to be arranged on second Semiconductor substrate 102.Wherein, the high k dielectric layer 107 and the gold
Belong to grid 108 between the isolation structure 10301.
Wherein, the isolation structure 10301 can be single layer structure, or sandwich construction.Exemplarily, it is described every
It is double-decker from structure 10301, including oxide skin(coating) and silicon nitride layer disposed thereon.
Further, the test structure can also include the boundary between high k dielectric layer 107 and metal gates 108
Surface layer 106.Boundary layer 106 can be located at subregion or the Zone Full of the high lower section of k dielectric layer 107, herein and without limit
It is fixed.
Exemplarily, the material of boundary layer 106 is oxide.
Further, high k dielectric layer 107 can also cover the close fin structure 1022 of isolation structure 10301 simultaneously
Side wall（That is, inside side walls）.Now high k dielectric layer can preferably isolating metal grid 108, therefore with superior technique effect
Fruit.
The test structure of the embodiment of the present invention, including the first Semiconductor substrate, metal gates and positioned there between
The second Semiconductor substrate and high k dielectric layer formed with fin structure, they form a capacity plate antenna structure（Second semiconductor
Substrate is bottom electrode, metal gates are Top electrode）, therefore, the capacitance voltage that comparatively can easily measure the test structure is bent
Line（CV curves）, and then obtain the work function of metal gates.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (16)
1. a kind of manufacture method of test structure, it is characterised in that methods described includes：
Step S101：There is provided includes the composite semiconductor lining of the first Semiconductor substrate and the second Semiconductor substrate disposed thereon
Bottom, hard mask layer is formed in second Semiconductor substrate；
Step S102：The hard mask layer is patterned, using through the patterned hard mask layer to described the second half
Conductor substrate is performed etching to form groove and the fin structure between the groove；
Step S103：Shallow trench isolation is formed in the groove；
Step S104：The certain thickness shallow trench is removed to isolate so that its height is less than the fin structure, and removes institute
The part that hard mask layer is located on the fin structure is stated, retains the hard mask layer and is located at the fin structure region
Outside part as isolation structure；
Step S105：The high k dielectric for covering the fin structure and shallow trench isolation is formed between the isolation structure
Layer and the metal gates on the high k dielectric layer.
2. the manufacture method of test structure as claimed in claim 1, it is characterised in that first Semiconductor substrate is P+ half
Conductor substrate, and/or, second Semiconductor substrate is P- Semiconductor substrates.
3. the manufacture method of test structure as claimed in claim 1, it is characterised in that the hard mask layer is by oxide skin(coating)
The double-decker formed with silicon nitride layer disposed thereon.
4. the manufacture method of test structure as claimed in claim 1, it is characterised in that the material of the shallow trench isolation is oxygen
Compound.
5. the manufacture method of the test structure as described in any one of Claims 1-4, it is characterised in that in the step S102
In, the method being patterned to the hard mask layer includes：
Step S1021：Advanced pattern material layer is formed on the hard mask layer；
Step S1022：The advanced pattern material layer is patterned, through the patterned advanced pattern material layer
Disposable spacer material and performed etching between pattern to form wall, remove the advanced pattern material layer；
Step S1023：The hard mask layer is patterned using the wall.
6. the manufacture method of the test structure as described in any one of Claims 1-4, it is characterised in that in the step S104
Include step S1045 between the step S105：Carry out chamfering and damage release processing.
7. the manufacture method of the test structure as described in any one of Claims 1-4, it is characterised in that in the step S105
In, before the high k dielectric layer is formed, form the boundary layer for covering the fin structure and shallow trench isolation.
8. the manufacture method of the test structure as described in any one of Claims 1-4, it is characterised in that in the step S105
In, the high k dielectric layer also covers the inside side walls of the isolation structure.
A kind of 9. test structure, it is characterised in that including：First Semiconductor substrate, on first Semiconductor substrate
The second Semiconductor substrate, high k dielectric layer on second Semiconductor substrate and positioned at the high k dielectric layer it
On metal gates, wherein, second Semiconductor substrate has fin structure and the height positioned at the fin structure both sides
Degree is isolated less than the shallow trench of the fin structure, the high k dielectric layer cover the fin structure and the shallow trench every
From wherein first Semiconductor substrate, the second Semiconductor substrate, high k dielectric layer and metal gates form a flat board electricity
Hold structure.
10. test structure as claimed in claim 9, it is characterised in that first Semiconductor substrate is P+ Semiconductor substrates,
And/or second Semiconductor substrate is P- Semiconductor substrates.
11. test structure as claimed in claim 9, it is characterised in that the material of the shallow trench isolation is oxide.
12. test structure as claimed in claim 9, it is characterised in that the test structure also includes covering the fin knot
Structure and the boundary layer of shallow trench isolation, the boundary layer are located at the lower section of the high k dielectric layer.
13. test structure as claimed in claim 9, it is characterised in that the test structure also includes：It is situated between positioned at the high k
High the k cap and work-function layer that stack gradually from bottom to top between electric layer and the metal gates.
14. the test structure as described in any one of claim 9 to 13, it is characterised in that the test structure also includes being formed
Isolation structure on second Semiconductor substrate and outside the fin structure region, wherein, the high k
Dielectric layer and the metal gates are between the isolation structure.
15. test structure as claimed in claim 14, it is characterised in that the isolation structure is by oxide skin(coating) and positioned at it
On silicon nitride layer composition double-decker.
16. test structure as claimed in claim 14, it is characterised in that the high k dielectric layer also covers the isolation structure
Inside side walls.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310729232.6A CN104752403B (en) | 2013-12-26 | 2013-12-26 | A kind of test structure and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310729232.6A CN104752403B (en) | 2013-12-26 | 2013-12-26 | A kind of test structure and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104752403A CN104752403A (en) | 2015-07-01 |
| CN104752403B true CN104752403B (en) | 2018-02-06 |
Family
ID=53591854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310729232.6A Active CN104752403B (en) | 2013-12-26 | 2013-12-26 | A kind of test structure and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104752403B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106340466B (en) * | 2016-08-30 | 2019-09-17 | 深圳天通信息科技有限公司 | A kind of IC test structure and forming method thereof |
| US10083878B1 (en) * | 2017-06-05 | 2018-09-25 | Globalfoundries Inc. | Fin fabrication process with dual shallow trench isolation and tunable inner and outer fin profile |
| CN108038260B (en) * | 2017-11-10 | 2021-04-13 | 上海华力微电子有限公司 | HKMG CMP process model test structure and modeling method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683192A (en) * | 2011-02-22 | 2012-09-19 | 格罗方德半导体公司 | Fin-transistor formed on a patterned sti region by late fin etch |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4907014B2 (en) * | 2001-06-22 | 2012-03-28 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
| US6713884B2 (en) * | 2001-12-20 | 2004-03-30 | Infineon Technologies Ag | Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors |
-
2013
- 2013-12-26 CN CN201310729232.6A patent/CN104752403B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683192A (en) * | 2011-02-22 | 2012-09-19 | 格罗方德半导体公司 | Fin-transistor formed on a patterned sti region by late fin etch |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104752403A (en) | 2015-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI480982B (en) | Vertical memory cell | |
| US7112490B1 (en) | Hot carrier injection programmable structure including discontinuous storage elements and spacer control gates in a trench | |
| CN102751230B (en) | Isolating capacitor in shallow trench isolation | |
| US20190280119A1 (en) | Super junction power transistor and preparation method thereof | |
| TWI652804B (en) | Semiconductor memory device | |
| CN102810476B (en) | The manufacture method of fin formula field effect transistor | |
| TWI570917B (en) | Trench power mosfet and manufacturing method thereof | |
| CN104752403B (en) | A kind of test structure and its manufacture method | |
| TWI749697B (en) | Semiconductor device and method for fabricating the same | |
| JP2013175593A (en) | Semiconductor device and manufacturing method of the same | |
| CN104009078A (en) | Junction-free transistor and manufacturing method thereof | |
| US8936981B2 (en) | Method for fabricating semiconductor device with mini SONOS cell | |
| KR100905138B1 (en) | Semiconductor device | |
| CN107644906A (en) | A kind of black phosphorus field-effect transistor and its manufacture method | |
| CN102956456B (en) | A kind of manufacture method of semiconductor device | |
| TWM480763U (en) | Trench power MOSFET | |
| CN110010691B (en) | Negative capacitance field effect transistor and preparation method thereof | |
| TW201240089A (en) | Transistor structure and method for preparing the same | |
| CN105097693A (en) | Semiconductor device and manufacture method thereof, and electronic device | |
| TWI505376B (en) | Method of forming a non-planar transistor | |
| TWI544635B (en) | Trench power mosfet and manufacturing method thereof | |
| US20240014212A1 (en) | Stacked fet architecture with separate gate regions | |
| TWI555120B (en) | Semiconductor device and method for fabricating the same | |
| CN103839981A (en) | Semiconductor device and method for manufacturing same | |
| US20230231057A1 (en) | 2d materials with inverted gate electrode for high density 3d stacking |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |