CN104752403A - Testing structure and manufacturing method thereof - Google Patents
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- CN104752403A CN104752403A CN201310729232.6A CN201310729232A CN104752403A CN 104752403 A CN104752403 A CN 104752403A CN 201310729232 A CN201310729232 A CN 201310729232A CN 104752403 A CN104752403 A CN 104752403A
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Abstract
The invention provides a testing structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The method comprises the steps of S101, providing a first semiconductor substrate and a second semiconductor substrate located on the first semiconductor substrate and forming a hard mask layer, S102, performing patterning on the hard mask layer, etching the second semiconductor substrate with the patterned hard mask layer to form trenches and fins located between the trenches, S103, forming shallow trench isolation in the trenches, S104, removing the shallow trench isolation with certain thickness to allow the height of the shallow trench isolation to be less than that of the fins, removing the hard mask layer located above the fins, and reserving the hard mask layer located outside the fins to serve as isolation structures, and S105, forming a high-k dielectric layer and a metal gate which cover the fins and the shallow trench isolation between the isolation structures. The method can conveniently manufacture the testing structure used for testing a CV (Capacitance-Voltage) curve. The testing structure can easily test the CV curve, thereby obtaining a work function of the metal gate.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of test structure and manufacture method thereof.
Background technology
In technical field of semiconductors, along with the development of semiconductor technology, for obtaining higher device density, usefulness and lower cost, the manufacture of semiconductor device often adopts three dimensional design, such as adopt fin field-effect transistor (fin field effect transistor, below can be called for short FinFET).In addition, in order to improve the performance of semiconductor device, high-k/metal gate technology also starts to obtain applying more and more widely.
Current, increasing semiconductor manufacturing manufacturer starts to adopt high-k/metal gate technology and fin FET technology to manufacture semiconductor device simultaneously, in obtained semiconductor device, the transistor used is high-k/metal gate fin FET.As everyone knows, how to obtain the work function of the metal gates of high-k/metal gate fin FET quickly and accurately, the exploitation for semiconductor device is most important.But, but there is no a kind of effective method that may be used for the work function obtaining metal gates at present.
In the prior art, have a kind of method can based between work function and the parameter such as electric capacity, voltage relation (mainly comprise following equilibrium relationships:
v
fb=φ
m-φ
si, φ
m=V
fb+ φ
si,
and
wherein, C
totalfor the total capacitance of unit area; C
oxfor the electric capacity of unit area oxide layer; C
sifor the electric capacity of unit area silicon substrate; C
fbfor flatband capacitanse; V
fbfor flat band voltage; ε
sifor the dielectric constant of silicon substrate; L
dfor the distance between substrate; Q is electronic charge; N
afor substrate doping density; K is Boltzmann constant; T is thermodynamic temperature; φ
mfor the work function of metal gates; φ
sifor the work function of silicon substrate; χ is electron affinity, is generally 4.05; E
gfor energy gap width; ψ
bfor the energy difference of Fermi level and intrinsic level; n
ifor intrinsic carrier concentration), in conjunction with capacitance voltage curves (CV curve) as shown in Figure 4, extract the work function of a certain material.Specifically, the method comprises following content: (1) by
Known
Will
Substitute into
And substitute into the concrete numerical value of each parameter, then can calculate C
fb; (2) at acquisition C
fbafterwards, V is obtained according to capacitance voltage curves (CV curve) as shown in Figure 4
fb; (3) by V
fb=φ
m-φ
siknown φ
m=V
fb+ φ
si, and
further, χ is generally 4.05,
be generally 0.56,
Then can obtain
By V
fband the numerical value of other parameters substitutes into equation
then φ can be calculated
mvalue.That is, according to above-mentioned equation and CV curve, the work function φ of metal gates can be obtained
m.
Obviously, obtain the work function of metal gates according to said method of the prior art, only need obtain corresponding capacitance voltage curves, then in conjunction with above-mentioned equation and each known parameters.But, capacitance voltage curves be obtained, corresponding test structure must be had; In the prior art, there is not a kind of test structure that may be used for the work function of the metal gates obtaining high-k/metal gate fin FET.
Therefore, for overcoming the above problems, be necessary to propose a kind of new test structure and manufacture method thereof.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of test structure and manufacture method thereof.
The embodiment of the present invention one provides a kind of manufacture method of test structure, comprising:
Step S101: provide and comprise the first Semiconductor substrate and the composite semiconductor substrate of the second Semiconductor substrate be located thereon, described second Semiconductor substrate forms hard mask layer;
Step S102: carry out graphically to described hard mask layer, utilizes and etches to form groove and the fin structure between described groove to described second Semiconductor substrate through patterned described hard mask layer;
Step S103: formed in described groove shallow trench isolation from;
Step S104: remove certain thickness described shallow trench isolation from make its height lower than described fin structure, and remove described hard mask layer and be positioned at part on described fin structure, retain described hard mask layer and be positioned at part outside described fin structure region as isolation structure;
Step S105: formed between described isolation structure cover described fin structure and described shallow trench isolation from high k dielectric layer and the metal gates that is positioned on described high k dielectric layer.
Wherein, described first Semiconductor substrate is P+ Semiconductor substrate, and/or described second Semiconductor substrate is P-Semiconductor substrate.
Alternatively, described hard mask layer is the double-decker be made up of with the silicon nitride layer be located thereon oxide skin(coating).
Alternatively, described shallow trench isolation from material be oxide.
Alternatively, in described step S102, patterned method is carried out to described hard mask layer and comprises:
Step S1021: form advanced pattern material layer on described hard mask layer;
Step S1022: carry out graphically to described advanced pattern material layer, disposable spacer material between the pattern through patterned described advanced pattern material layer also carries out etching to form wall, removes described advanced pattern material layer;
Step S1023: utilize described wall to carry out graphically described hard mask layer.
Alternatively, between described step S104 and described step S105, step S1045 is comprised: carry out chamfering and damage to discharge processing.
Alternatively, in described step S105, before the described high k dielectric layer of formation, formed cover described fin structure and described shallow trench isolation from boundary layer.
Alternatively, in described step S105, described high k dielectric layer also covers the inside side walls of described isolation structure.
The embodiment of the present invention two provides a kind of test structure, comprise: the first Semiconductor substrate, be positioned at the second Semiconductor substrate on described first Semiconductor substrate, the metal gates being positioned at the high k dielectric layer on described second Semiconductor substrate and being positioned on described high k dielectric layer, wherein, the height that described second Semiconductor substrate has fin structure and is positioned at described fin structure both sides lower than described fin structure shallow trench isolation from, described high k dielectric layer cover described fin structure and described shallow trench isolation from.
Alternatively, described first Semiconductor substrate is P+ Semiconductor substrate, and/or described second Semiconductor substrate is P-Semiconductor substrate.
Alternatively, described shallow trench isolation from material be oxide.
Alternatively, described test structure also comprise cover described fin structure and described shallow trench isolation from boundary layer, described boundary layer is positioned at the below of described high k dielectric layer.
Alternatively, described test structure also comprises: the high k cap stacked gradually from bottom to top between described high k dielectric layer and described metal gates and work-function layer.
Alternatively, described test structure also comprises and to be formed on described second Semiconductor substrate and the isolation structure be positioned at outside described fin structure region, and wherein, described high k dielectric layer and described metal gates are between described isolation structure.
Alternatively, described isolation structure is the double-decker be made up of with the silicon nitride layer be located thereon oxide skin(coating).
Alternatively, described high k dielectric layer also covers the inside side walls of described isolation structure.
The manufacture method of test structure of the present invention, can obtain the test structure for testing CV curve more easily, and then can be relatively easy to the work function obtaining metal gates.Test structure of the present invention, the second Semiconductor substrate being formed with fin structure comprising the first Semiconductor substrate, metal gates and be positioned at therebetween and high k dielectric layer, they form a capacity plate antenna structure, therefore, the CV curve of this test structure can be recorded with comparalive ease, and then obtain the work function of metal gates.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 K is the schematic diagram of the figure that the committed step of the manufacture method of a kind of test structure that the embodiment of the present invention one proposes is formed; Wherein, Figure 1A-1,1B-1,1C-1,1D-1,1E-1,1F-1,1G-1,1H-1,1I-1,1J-1 and 1K-1 are vertical view, and Figure 1A-2,1B-2,1C-2,1D-2,1E-2,1F-2,1G-2,1H-2,1I-2,1J-2 and 1K-2 are the cutaway view along XX ' line in respective top;
Fig. 2 is the typical flowchart of the manufacture method of a kind of test structure that the embodiment of the present invention one proposes;
Fig. 3 is the illustrative diagram of a kind of test structure that the embodiment of the present invention two proposes, and wherein Fig. 3 A is vertical view, and Fig. 3 B is the cutaway view along XX ' line in Fig. 3 A;
Fig. 4 is the schematic diagram of a kind of capacitance voltage curves of the prior art.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
Here with reference to the cross-sectional view as the schematic diagram of desirable embodiment of the present invention (and intermediate structure), inventive embodiment is described.Like this, it is expected to the change from shown shape because such as manufacturing technology and/or tolerance cause.Therefore, embodiments of the invention should not be confined to the given shape in district shown here, but comprise owing to such as manufacturing the form variations caused.Such as, the injection region being shown as rectangle has round or bending features and/or implantation concentration gradient usually at its edge, instead of the binary from injection region to non-injection regions changes.Equally, by inject formed disposal area this disposal area and injection can be caused to carry out time process surface between district some inject.Therefore, the district shown in figure is in fact schematic, and their shape is not intended the true form in the district of display device and is not intended to limit scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Embodiment one
Below, the detailed step of a manufacture method illustrative methods of the semiconductor device that the embodiment of the present invention proposes is described with reference to Figure 1A-Fig. 1 K and Fig. 2.Figure 1A-Fig. 1 K is the illustrative diagram of the figure that the committed step of the manufacture method of a kind of test structure of the embodiment of the present invention is formed; Wherein, Figure 1A-1,1B-1,1C-1,1D-1,1E-1,1F-1,1G-1,1H-1,1I-1,1J-1 and 1K-1 are vertical view, and Figure 1A-2,1B-2,1C-2,1D-2,1E-2,1F-2,1G-2,1H-2,1I-2,1J-2 and 1K-2 are the cutaway view of corresponding vertical view along XX ' line; Fig. 2 is the typical flowchart of the manufacture method of a kind of test structure of the embodiment of the present invention.
The manufacture method of the test structure of the present embodiment, comprises the steps:
Steps A 1: provide the composite semiconductor substrate of the second Semiconductor substrate 102 comprising the first Semiconductor substrate 101 and be located thereon, as shown in Figure 1A; Described second Semiconductor substrate 102 forms hard mask layer 103, on hard mask layer 103, forms advanced pattern material layer (advanced pattern film, APF) 104, as shown in Figure 1B.
Exemplarily, the first Semiconductor substrate 101 is P+ Semiconductor substrate, and the second Semiconductor substrate 102 is P-Semiconductor substrate.Advanced pattern material layer (APF) 104 is generally amorphous carbon.
Hard mask layer 103 can be single layer structure or sandwich construction, exemplarily, and the silicon nitride layer 1032 that hard mask layer 103 comprises oxide skin(coating) 1031 and is located thereon, as shown in Figure 1B.
Wherein, forming the method for the first Semiconductor substrate 101 and the second Semiconductor substrate 102, can be epitaxial growth method or other suitable methods.Forming the method for hard mask layer 103, can be sedimentation or other suitable methods.Forming advanced pattern material layer (APF) 104, is sedimentation or other suitable methods.
Steps A 2: carry out graphically to advanced pattern material layer (APF) 104, forms patterned advanced pattern material layer (APF) 104 ', as shown in Figure 1 C.Disposable spacer material between the pattern of described patterned advanced pattern material layer (APF) 104 ' also carries out etching to form wall 105, removes described patterned advanced pattern material layer 104 ', as shown in figure ip.
Wherein, the material of wall 105 is generally silicon nitride or other suitable materials.
Steps A 3: utilize wall 105 pairs of hard mask layers 103 to carry out graphically, with patterned hard mask layer 103 ' for mask etches the second Semiconductor substrate 102, second Semiconductor substrate 102 is formed groove 1021 and the fin structure (Fin) 1022 between groove 1021, retain patterned hard mask layer 103 ', as referring to figure 1e.
Wherein, fin structure 1022 can be one or more, and multiple fin structure has been shown in Fig. 1 E.In the embodiment with multiple fin structure, the size of each fin structure, shape can identical also can not be identical.
Exemplarily, the patterned silicon nitride layer 1032 ' that patterned hard mask layer 103 ' comprises patterned oxide skin(coating) 1031 ' and is located thereon, as referring to figure 1e.
Steps A 4: form shallow trench isolation from (STI) 106 in described groove 1021, as shown in fig. 1f.
Exemplarily, form the method for shallow trench isolation from 106 to comprise: in described groove 1021 and above described groove 1021, fill isolated material; The isolated material that is positioned on described patterned hard mask layer 103 ' is removed to form shallow trench isolation from (STI) 106 by CMP.Wherein, described isolated material can be oxide or other suitable materials.
Steps A 5: remove certain thickness shallow trench isolation from (STI) 1060, and remove described patterned hard mask layer 103 ' and be positioned at part on fin structure 1022, retain described patterned hard mask layer 103 ' and be positioned at part outside fin structure 1022 region as isolation structure 10301, as shown in Figure 1 I.
Exemplarily, the second hard mask layer 1032 ' that patterned hard mask layer 103 ' comprises the first hard mask layer 1031 ' and is located thereon, steps A 5 can comprise:
Steps A 51: remove shallow trench isolation from the part of (STI) 106 higher than the first hard mask layer 1031 ', as shown in Figure 1 G.The method removed can be wet etching or other suitable methods.
Steps A 52: remove the second hard mask layer 1032 ' and be positioned at part on fin structure 1022, retains the second hard mask layer 1032 ' and is positioned at part outside fin structure 1022 region, as shown in fig. 1h.
Steps A 53: remove the first hard mask layer 1031 ' and be positioned at part on fin structure 1022, retain the first hard mask layer 1031 ' and be positioned at part outside fin structure 1022 region, and remove certain thickness shallow trench isolation from (STI) 106, as shown in Figure 1 I.
Exemplarily, through steps A 5, the height of the remainder of shallow trench isolation from 106 lower than fin structure 1022, as shown in Figure 1 I.In the present embodiment, when the material of shallow trench isolation from 1060 is oxide, shallow trench isolation can as the boundary layer of follow-up formation structure from the remainder of 106.Further, when the first hard mask layer 1031 ' is for oxide, the part that the first hard mask layer and shallow trench isolation are offed normal on fin structure 1022 all can retain a part in steps A 51, to form the boundary layer covering fin structure 1022 completely.
Steps A 6: carry out chamfering (corner rounding) and damage release (damage release) process, as shown in figure ij.
This step can adopt various feasible mode of the prior art to realize, and repeats no more herein.By this step, can ensure that the structure of follow-up formation has better performance.It is to be understood that in order to briefly, Fig. 1 J not shown second Semiconductor substrate 102 and the change after the treatment of other assemblies.Further, steps A 6 can be omitted.
Steps A 7: formed cover fin structure 1022 and shallow trench isolation from the high k dielectric layer 107 of remainder 106, and on described high k dielectric layer 107, form the metal gates 108 between described isolation structure 10301, as shown in figure ik.
Exemplarily, the method for high k dielectric layer is formed for deposition.The method forming metal gates 108 is: between isolation structure 10301, fill metal material, and by CMP(chemico-mechanical polishing) remove the unnecessary metal material be positioned on isolation structure 10301.
In the present embodiment, high k dielectric layer 107 can also cover the sidewall of the close fin structure 1022 of isolation structure 10301 simultaneously.Now high k dielectric layer can isolating metal grid 108 better, therefore has better technique effect.
In this step, before the high k dielectric layer of formation, boundary layer can also be formed; After the high k dielectric layer of formation, before metal gates 108, the work-function layer that can also form high k cap and be positioned on high k cap.Wherein, high k cap is generally TiN and TaN, and the material of metal gates 108 is generally aluminium or tungsten.That is, in the present embodiment, the final gate stack structure formed can comprise from bottom to top successively: boundary layer, high k dielectric layer, high k cap, work-function layer, metal gates.
In addition, also it should be explained that, in various embodiments of the present invention, the cutaway view such as Figure 1A-2,1B-2,1C-2,1D-2,1E-2,1F-2,1G-2,1H-2,1I-2,1J-2 and 1K-2 might not be completely corresponding with the vertical view such as Figure 1A-1,1B-1,1C-1,1D-1,1E-1,1F-1,1G-1,1H-1,1I-1,1J-1 and 1K-1, and each cutaway view can be a part for the cutaway view along XX ' line.
So far, the introduction of the manufacture method of the test structure of the embodiment of the present invention is completed.By the method, the test structure of the work function of the metal gates for obtaining high-k/metal gate fin FET cmos device can be obtained more easily.
The test structure obtained according to the manufacture method of the test structure of the embodiment of the present invention, the second Semiconductor substrate being formed with fin structure comprising the first Semiconductor substrate, metal gates and be positioned at therebetween and high k dielectric layer, they form capacity plate antenna structure (the second Semiconductor substrate be bottom electrode, metal gates be top electrode), therefore, the capacitance voltage curves (CV curve) recording this test structure can be easy to, and then obtain the work function of metal gates.According to the manufacture method of the test structure of the embodiment of the present invention, the test structure for testing CV curve can be obtained more easily, and then the work function obtaining metal gates can be relatively easy to.
With reference to Fig. 2, illustrated therein is the flow chart of a kind of typical method in the manufacture method of the test that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
Step S101: provide and comprise the first Semiconductor substrate and the composite semiconductor substrate of the second Semiconductor substrate be located thereon, described second Semiconductor substrate forms hard mask layer;
Step S102: carry out graphically to described hard mask layer, utilizes and etches to form groove and the fin structure between described groove to described second Semiconductor substrate through patterned described hard mask layer;
Step S103: formed in described groove shallow trench isolation from;
Step S104: remove certain thickness described shallow trench isolation from make its height lower than described fin structure, and remove described hard mask layer and be positioned at part on described fin structure, retain described hard mask layer and be positioned at part outside described fin structure region as isolation structure;
Step S105: formed between described isolation structure cover described fin structure and described shallow trench isolation from high k dielectric layer and the metal gates that is positioned on described high k dielectric layer.
Embodiment two
The embodiment of the present invention provides a kind of test structure, may be used for the work function of the metal gates obtaining the semiconductor device adopting high-k/metal gate fin FET.This test structure, can be obtained by the method described in embodiment one.
Below, introduce the test structure of the present embodiment with reference to Fig. 3, wherein Fig. 3 A is the vertical view of this test structure, and Fig. 3 B is the cutaway view along XX ' line in Fig. 3 A.As shown in Figure 3, the test structure of the present embodiment comprises: the first Semiconductor substrate 101, be positioned at the second Semiconductor substrate 102 on the first Semiconductor substrate 101, the metal gates 108 being positioned at the high k dielectric layer 107 on described second Semiconductor substrate 102 and being positioned on described high k dielectric layer, wherein, described second Semiconductor substrate 102 has at least one fin structure (Fin) 1022, the shallow trench isolation of end face and sidewall and described fin structure 1022 both sides that described high k dielectric layer 107 covers described fin structure 1022 is from 106, shallow trench isolation from 106 height lower than fin structure 1022.
Wherein, the first Semiconductor substrate 101, second Semiconductor substrate 102, high k dielectric layer 107 and metal gates 108 form a capacity plate antenna structure, and the first Semiconductor substrate 101 and metal gates 108 are respectively top electrode and the bottom electrode of this capacity plate antenna.
Exemplarily, the first Semiconductor substrate 101 is P+ Semiconductor substrate, and the second Semiconductor substrate 102 is P-Semiconductor substrate.
Further, described test structure also comprises the isolation structure 10301 being positioned at described metal gates 108 both sides, and described isolation structure 10301 is arranged on described second Semiconductor substrate 102.Wherein, described high k dielectric layer 107 and described metal gates 108 are between described isolation structure 10301.
Wherein, described isolation structure 10301 can be single layer structure, also can be sandwich construction.Exemplarily, described isolation structure 10301 is double-decker, the silicon nitride layer comprising oxide skin(coating) He be located thereon.
Further, described test structure can also comprise the boundary layer 106 between high k dielectric layer 107 and metal gates 108.Boundary layer 106 can be positioned at subregion below high k dielectric layer 107 or Zone Full, does not limit at this.
Exemplarily, the material of boundary layer 106 is oxide.
Further, high k dielectric layer 107 can also cover the sidewall (that is, inside side walls) of the close fin structure 1022 of isolation structure 10301 simultaneously.Now high k dielectric layer can isolating metal grid 108 better, therefore has better technique effect.
The test structure of the embodiment of the present invention, the second Semiconductor substrate being formed with fin structure comprising the first Semiconductor substrate, metal gates and be positioned at therebetween and high k dielectric layer, they form capacity plate antenna structure (the second Semiconductor substrate be bottom electrode, metal gates be top electrode), therefore, comparatively easily can record the capacitance voltage curves (CV curve) of this test structure, and then obtain the work function of metal gates.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (16)
1. a manufacture method for test structure, is characterized in that, described method comprises:
Step S101: provide and comprise the first Semiconductor substrate and the composite semiconductor substrate of the second Semiconductor substrate be located thereon, described second Semiconductor substrate forms hard mask layer;
Step S102: carry out graphically to described hard mask layer, utilizes and etches to form groove and the fin structure between described groove to described second Semiconductor substrate through patterned described hard mask layer;
Step S103: formed in described groove shallow trench isolation from;
Step S104: remove certain thickness described shallow trench isolation from make its height lower than described fin structure, and remove described hard mask layer and be positioned at part on described fin structure, retain described hard mask layer and be positioned at part outside described fin structure region as isolation structure;
Step S105: formed between described isolation structure cover described fin structure and described shallow trench isolation from high k dielectric layer and the metal gates that is positioned on described high k dielectric layer.
2. the manufacture method of test structure as claimed in claim 1, it is characterized in that, described first Semiconductor substrate is P+ Semiconductor substrate, and/or described second Semiconductor substrate is P-Semiconductor substrate.
3. the manufacture method of test structure as claimed in claim 1, is characterized in that, described hard mask layer is the double-decker be made up of with the silicon nitride layer be located thereon oxide skin(coating).
4. the manufacture method of test structure as claimed in claim 1, is characterized in that, described shallow trench isolation from material be oxide.
5. the manufacture method of the test structure as described in any one of Claims 1-4, is characterized in that, in described step S102, carries out patterned method comprise described hard mask layer:
Step S1021: form advanced pattern material layer on described hard mask layer;
Step S1022: carry out graphically to described advanced pattern material layer, disposable spacer material between the pattern through patterned described advanced pattern material layer also carries out etching to form wall, removes described advanced pattern material layer;
Step S1023: utilize described wall to carry out graphically described hard mask layer.
6. the manufacture method of the test structure as described in any one of Claims 1-4, is characterized in that, between described step S104 and described step S105, comprise step S1045: carry out chamfering and damage to discharge processing.
7. the manufacture method of the test structure as described in any one of Claims 1-4, is characterized in that, in described step S105, before the described high k dielectric layer of formation, formed cover described fin structure and described shallow trench isolation from boundary layer.
8. the manufacture method of the test structure as described in any one of Claims 1-4, is characterized in that, in described step S105, described high k dielectric layer also covers the inside side walls of described isolation structure.
9. a test structure, it is characterized in that, comprise: the first Semiconductor substrate, be positioned at the second Semiconductor substrate on described first Semiconductor substrate, the metal gates being positioned at the high k dielectric layer on described second Semiconductor substrate and being positioned on described high k dielectric layer, wherein, the height that described second Semiconductor substrate has fin structure and is positioned at described fin structure both sides lower than described fin structure shallow trench isolation from, described high k dielectric layer cover described fin structure and described shallow trench isolation from.
10. test structure as claimed in claim 9, it is characterized in that, described first Semiconductor substrate is P+ Semiconductor substrate, and/or described second Semiconductor substrate is P-Semiconductor substrate.
11. test structures as claimed in claim 9, is characterized in that, described shallow trench isolation from material be oxide.
12. test structures as claimed in claim 9, is characterized in that, described test structure also comprise cover described fin structure and described shallow trench isolation from boundary layer, described boundary layer is positioned at the below of described high k dielectric layer.
13. test structures as claimed in claim 9, it is characterized in that, described test structure also comprises: the high k cap stacked gradually from bottom to top between described high k dielectric layer and described metal gates and work-function layer.
14. test structures as described in any one of claim 9 to 13, it is characterized in that, described test structure also comprises and to be formed on described second Semiconductor substrate and the isolation structure be positioned at outside described fin structure region, wherein, described high k dielectric layer and described metal gates are between described isolation structure.
15. test structures as claimed in claim 14, is characterized in that, described isolation structure is the double-decker be made up of with the silicon nitride layer be located thereon oxide skin(coating).
16. test structures as claimed in claim 14, it is characterized in that, described high k dielectric layer also covers the inside side walls of described isolation structure.
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| CN201310729232.6A Active CN104752403B (en) | 2013-12-26 | 2013-12-26 | A kind of test structure and its manufacture method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106340466A (en) * | 2016-08-30 | 2017-01-18 | 张为凤 | Integrated circuit test structure and formation method thereof |
| CN108038260A (en) * | 2017-11-10 | 2018-05-15 | 上海华力微电子有限公司 | HKMG CMP process model measurement structures and modeling method |
| CN108987345A (en) * | 2017-06-05 | 2018-12-11 | 格芯公司 | Fin processing procedure with dual shallow trench isolation and adjustable interior outer-finned profile |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020197819A1 (en) * | 2001-06-22 | 2002-12-26 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device including a step of forming element isolation trench and semiconductor device |
| US20030119274A1 (en) * | 2001-12-20 | 2003-06-26 | Infineon Technologies North America Corp. | Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors |
| CN102683192A (en) * | 2011-02-22 | 2012-09-19 | 格罗方德半导体公司 | Fin-transistor formed on a patterned sti region by late fin etch |
-
2013
- 2013-12-26 CN CN201310729232.6A patent/CN104752403B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020197819A1 (en) * | 2001-06-22 | 2002-12-26 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device including a step of forming element isolation trench and semiconductor device |
| US20030119274A1 (en) * | 2001-12-20 | 2003-06-26 | Infineon Technologies North America Corp. | Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors |
| CN102683192A (en) * | 2011-02-22 | 2012-09-19 | 格罗方德半导体公司 | Fin-transistor formed on a patterned sti region by late fin etch |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106340466A (en) * | 2016-08-30 | 2017-01-18 | 张为凤 | Integrated circuit test structure and formation method thereof |
| CN108987345A (en) * | 2017-06-05 | 2018-12-11 | 格芯公司 | Fin processing procedure with dual shallow trench isolation and adjustable interior outer-finned profile |
| CN108038260A (en) * | 2017-11-10 | 2018-05-15 | 上海华力微电子有限公司 | HKMG CMP process model measurement structures and modeling method |
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| CN104752403B (en) | 2018-02-06 |
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