CN108010848A - The production method of planar vertical bilateral diffusion metal oxide transistor - Google Patents
The production method of planar vertical bilateral diffusion metal oxide transistor Download PDFInfo
- Publication number
- CN108010848A CN108010848A CN201711364914.6A CN201711364914A CN108010848A CN 108010848 A CN108010848 A CN 108010848A CN 201711364914 A CN201711364914 A CN 201711364914A CN 108010848 A CN108010848 A CN 108010848A
- Authority
- CN
- China
- Prior art keywords
- polysilicon layer
- type
- layer
- production method
- metal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000009792 diffusion process Methods 0.000 title claims abstract description 23
- 230000002146 bilateral effect Effects 0.000 title claims abstract description 22
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 22
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 61
- 229920005591 polysilicon Polymers 0.000 claims abstract description 60
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 8
- 230000000717 retained effect Effects 0.000 claims abstract description 8
- 230000003213 activating effect Effects 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 239000010936 titanium Substances 0.000 claims description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910018594 Si-Cu Inorganic materials 0.000 claims description 3
- 229910008465 Si—Cu Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229940090044 injection Drugs 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of production method of planar vertical bilateral diffusion metal oxide transistor comprises the following steps：N-type extension with N-type substrate is provided, gate oxide, polysilicon layer and silicon nitride layer are sequentially formed in N-type extension；Silicon nitride layer and polysilicon layer are performed etching using photoresist so as to remove partial nitridation silicon layer and polysilicon layer, remaining another part polysilicon layer polysilicon layer associated with as grid and mutually, and the silicon nitride layer at the top of remaining polysilicon layer is retained；Photoresist is removed, p-type ion implanting is carried out in N-type extension；Ion is injected to p-type and forms PXing Ti areas into line activating and propulsion；By photoetching process, source region position is defined, and gate oxide is performed etching using another photoresist and removes part gate oxide, the gate oxide below polysilicon layer is retained；N-type region domain is formed as source region in p-type body surface；Another photoresist is removed, and removes the partial nitridation silicon layer above polysilicon layer.
Description
【Technical field】
The present invention relates to semiconductor fabrication process technical field, especially, is related to a kind of planar vertical double diffused metal
The production method of oxide transistor.
【Background technology】
It is by source and body ion implanting in plane VDMOS (vertical DMOS transistor)
Transverse diffusion distance difference forms raceway groove, it is widely used in field of switch power.
In plane VDMOS techniques, gate oxide thickness generally between 800 angstroms~1200 angstroms, etching polysilicon it
Afterwards, the loss of gate oxide is also right in 100 Izods, so after etching polysilicon, also has dioxy at least 700 angstroms remaining in source region
SiClx layer.If source region injection ion is arsenic (symbol of element As), then 700 angstroms of oxidated layer thickness is undoubtedly blocked up, arsenic
Ion is difficult to penetrate so thick oxide layer and be injected into inside silicon and go., generally all can be so in plane VDMOS techniques
Increase the etching of a step silica before source region ion implanting, between thickness is etched into 200 angstroms~300 angstroms, in favor of source region
Ion implanting.In traditional handicraft, this step silica etching is generally placed upon after source region photoetching.In the design of VDMOS, in source region
After photoetching, the area of grid that source region closes polysilicon is all exposed.So in the etching of silica, unavoidably
Meeting be damaged to polysilicon layer, this is that we are unwilling to see.
From the above, it may be appreciated that in existing plane VDMOS techniques, after oxide layer etching, the surface of polysilicon layer may be same
When can be damaged in etching technics, after damage, the threshold voltage of semiconductor devices can fluctuate, and can also influence device
Reliability.
【The content of the invention】
One of purpose of the present invention is that providing a kind of plane for the above-mentioned at least one technical problem of solution hangs down
The production method of straight bilateral diffusion metal oxide transistor.
A kind of production method of planar vertical bilateral diffusion metal oxide transistor, it comprises the following steps：
N-type extension with N-type substrate is provided, gate oxide, polysilicon layer and nitrogen are sequentially formed in the N-type extension
SiClx layer；
The silicon nitride layer and polysilicon layer are performed etching using photoresist so as to remove partial nitridation silicon layer and polycrystalline
Silicon layer, remaining another part polysilicon layer polysilicon layer associated with as grid and mutually, and at the top of remaining polysilicon layer
Silicon nitride layer is retained；
The photoresist is removed, p-type ion implanting is carried out in the N-type extension；
Ion is injected to the p-type and forms PXing Ti areas into line activating and propulsion；
By photoetching process, source region position is defined, and the gate oxide is performed etching using another photoresist
Except part gate oxide, the gate oxide below the polysilicon layer is retained；
N-type region domain is formed as source region in the p-type body surface；
Another photoresist is removed, and removes the partial nitridation silicon layer above the polysilicon layer；
Gate oxide side wall at the top of the polysilicon layer and below side wall, the polysilicon layer forms dielectric layer；
Front metal is formed on the PXing Ti areas, the source region and the dielectric layer；
In the N-type substrate back metal is formed away from the N-type extension side.
In one embodiment, the thickness of the gate oxide is in the range of 800 angstroms to 1200 angstroms.
In one embodiment, the step of removing the partial nitridation silicon layer above the polysilicon layer includes the use of heat
Phosphoric acid removes the partial nitridation silicon layer above the polysilicon layer using wet processing.
In one embodiment, the silicon nitride layer and polysilicon layer is performed etching using photoresist so as to removal portion
In the step of dividing silicon nitride layer and polysilicon layer, partial nitridation silicon layer is first removed using dry etching, then go using dry etching
Except partial polysilicon layer.
In one embodiment, the thickness of the silicon nitride layer is in the range of 300 angstroms to 600 angstroms.
In one embodiment, the p-type ion includes boron, and the dosage of the p-type ion implanting is every square centimeter 1
13 powers in the range of 15 powers every square centimeter gone, the energy of the p-type ion implanting is in 600KEV to 1000KEV
In the range of.
In one embodiment, to the p-type inject ion into line activating and promote form PXing Ti areas the step of temperature
Degree in the range of 900 degrees Celsius to 1200 degrees Celsius, the time in the range of 50 minutes to 200 minutes, the gas bag that is passed through
Nitrogen and oxygen are included, the flow of the nitrogen is in the range of per minute 8 are raised to 12 liters, and the flow of the oxygen is per minute
0.04 is raised in the range of 0.2 liter.
In one embodiment, the N-type substrate is the dense substrate of N-type, and extension is lightly doped for N-type in the N-type extension.
In one embodiment, the material of the front metal includes Al-Si-Cu alloy.
In one embodiment, the back metal includes titanium, nickel, the composite bed of silver.
Compared to the prior art, in the production method of planar vertical bilateral diffusion metal oxide transistor of the present invention, by
There is silicon nitride layer protection in polysilicon layer surface, to the damage problem of polysilicon when completely solving etching, avoid polysilicon layer
The problem of damaging the influence device reliability that may occur.
【Brief description of the drawings】
To describe the technical solutions in the embodiments of the present invention more clearly, used in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the flow chart of the production method of planar vertical bilateral diffusion metal oxide transistor of the present invention.
Fig. 2-Fig. 8 is each step of the production method of planar vertical bilateral diffusion metal oxide transistor shown in Fig. 1
Structure diagram.
Main element symbol description
N-type substrate 1；N-type extension 2；Gate oxide 3；Polysilicon layer 4；Silicon nitride layer 5；PXing Ti areas；Photoresist 7；Source region
8；Dielectric layer 9；Front metal 10；Back metal 11；Step S1-S10
【Embodiment】
The technical solution in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only the part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this area is common
All other embodiment that technical staff is obtained without making creative work, belongs to the model that the present invention protects
Enclose.
- Fig. 8 is please referred to Fig.1, Fig. 1 is the production method of planar vertical bilateral diffusion metal oxide transistor of the present invention
Flow chart, Fig. 2-Fig. 8 are the knot of each step of the production method of planar vertical bilateral diffusion metal oxide transistor shown in Fig. 1
Structure schematic diagram.The production method of the planar vertical bilateral diffusion metal oxide transistor comprises the following steps S1-S10.
Step S1, referring to Fig. 2, providing the N-type extension 2 with N-type substrate 1, sequentially forms in the N-type extension 2
Gate oxide 3, polysilicon layer 4 and silicon nitride layer 5.Specifically, the N-type substrate 1 is the dense substrate of N-type, and the N-type extension 2 is N
Extension is lightly doped in type.The thickness of the gate oxide 3 is in the range of 800 angstroms to 1200 angstroms.The thickness of the silicon nitride layer exists
In the range of 300 angstroms to 600 angstroms.
Step S2, referring to Fig. 3, being performed etching using photoresist 7 to the silicon nitride layer 5 and polysilicon layer 4 so as to go
Except partial nitridation silicon layer 5 and polysilicon layer 4, remaining another part polysilicon layer 4 polysilicon layer associated with as grid and mutually
4, and the silicon nitride layer 5 at the top of remaining polysilicon layer 4 is retained.Specifically, partial silicon nitride is first removed using dry etching
Layer 5, then partial polysilicon layer 4 is removed using dry etching.
Step S3, referring to Fig. 4, removing the photoresist 7, p-type ion implanting is carried out in the N-type extension 2.Specifically
Ground, the p-type ion include boron, and the dosage of the p-type ion implanting is gone in every square centimeter 1 13 powers to every square centimeter
15 powers in the range of, the energy of the p-type ion implanting is in the range of 600KEV to 1000KEV.
Step S4, referring to Fig. 5, inject ion to the p-type forms PXing Ti areas 6 into line activating and propulsion.Specifically,
To the p-type inject ion into line activating and promote form PXing Ti areas 6 when, model of the temperature at 900 degrees Celsius to 1200 degrees Celsius
In enclosing, the time, the gas being passed through included nitrogen and oxygen, and the flow of the nitrogen exists in the range of 50 minutes to 200 minutes
Per minute 8 are raised in the range of 12 liters, and the flow of the oxygen is raised in the range of 0.2 liter per minute 0.04.
Step S5, referring to Fig. 6, by photoetching process, defines source region position, and using another photoresist to the grid
Oxide layer 3, which performs etching, removes part gate oxide 3, and the gate oxide 3 of the lower section of polysilicon layer 4 is retained.Specifically, go
The thickness of the part gate oxide 3 removed is equal to the thickness of the silicon nitride layer 5.
Step S6, referring to Fig. 7, forming N-type region domain on 6 surface of PXing Ti areas as source region 8.
Step S7, referring to Fig. 7, removing another photoresist, and removes the partial nitridation silicon layer of the top of polysilicon layer 4
5.Specifically, the phosphoric acid of heat can be used to remove the partial nitridation silicon layer 5 of the top of polysilicon layer 4 using wet processing.
Step S8, referring to Fig. 8, the gate oxidation below the top of polysilicon layer 4 and side wall, the polysilicon layer 4
3 side wall of layer form dielectric layer 9.
Step S9, referring to Fig. 8, forming front metal on the PXing Ti areas 6, the source region 8 and the dielectric layer
10.Specifically, the material of the front metal 10 includes Al-Si-Cu alloy.
Step S10, referring to Fig. 8, forming back metal 11 away from 2 side of N-type extension in the N-type substrate 1.Tool
Body, the back metal 11 includes titanium, nickel, the composite bed of silver.
Compared to the prior art, in the production method of planar vertical bilateral diffusion metal oxide transistor of the present invention, by
There is silicon nitride layer 5 to protect in 4 surface of polysilicon layer, to the damage problem of polysilicon when completely solving etching, avoid more
Crystal silicon layer 4 damages the problem of influence device reliability that may occur.
Above-described is only embodiments of the present invention, it should be noted here that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
Enclose.
Claims (10)
- A kind of 1. production method of planar vertical bilateral diffusion metal oxide transistor, it is characterised in that：The production method Comprise the following steps：N-type extension with N-type substrate is provided, gate oxide, polysilicon layer and silicon nitride are sequentially formed in the N-type extension Layer；The silicon nitride layer and polysilicon layer are performed etching using photoresist so as to remove partial nitridation silicon layer and polysilicon layer, Remaining another part polysilicon layer polysilicon layer associated with as grid and mutually, and the silicon nitride at the top of remaining polysilicon layer Layer is retained；The photoresist is removed, p-type ion implanting is carried out in the N-type extension；Ion is injected to the p-type and forms PXing Ti areas into line activating and propulsion；By photoetching process, source region position is defined, and removal portion is performed etching to the gate oxide using another photoresist Point gate oxide, the gate oxide below the polysilicon layer are retained；N-type region domain is formed as source region in the p-type body surface；Another photoresist is removed, and removes the partial nitridation silicon layer above the polysilicon layer；Gate oxide side wall at the top of the polysilicon layer and below side wall, the polysilicon layer forms dielectric layer；Front metal is formed on the PXing Ti areas, the source region and the dielectric layer；In the N-type substrate back metal is formed away from the N-type extension side.
- 2. the production method of planar vertical bilateral diffusion metal oxide transistor as claimed in claim 1, it is characterised in that： The thickness of the gate oxide is in the range of 800 angstroms to 1200 angstroms.
- 3. the production method of planar vertical bilateral diffusion metal oxide transistor as claimed in claim 1, it is characterised in that： The step of removing the partial nitridation silicon layer above the polysilicon layer includes the use of the phosphoric acid of heat using described in wet processing removal Partial nitridation silicon layer above polysilicon layer.
- 4. the production method of planar vertical bilateral diffusion metal oxide transistor as claimed in claim 1, it is characterised in that： The silicon nitride layer and polysilicon layer are performed etching using photoresist so as to remove the step of partial nitridation silicon layer and polysilicon layer In rapid, partial nitridation silicon layer is first removed using dry etching, then partial polysilicon layer is removed using dry etching.
- 5. the production method of planar vertical bilateral diffusion metal oxide transistor as claimed in claim 1, it is characterised in that： The thickness of the silicon nitride layer is in the range of 300 angstroms to 600 angstroms.
- 6. the production method of planar vertical bilateral diffusion metal oxide transistor as claimed in claim 1, it is characterised in that： The p-type ion includes boron, and the dosage of the p-type ion implanting is gone in every square centimeter 1 13 powers to every square centimeter In the range of 15 powers, the energy of the p-type ion implanting is in the range of 600KEV to 1000KEV.
- 7. the production method of planar vertical bilateral diffusion metal oxide transistor as claimed in claim 1, it is characterised in that： Ion is injected to the p-type into line activating and promotes the temperature for the step of forming PXing Ti areas at 900 degrees Celsius to 1200 degrees Celsius In the range of, the time, the gas being passed through included nitrogen and oxygen, the stream of the nitrogen in the range of 50 minutes to 200 minutes In the range of per minute 8 are raised to 12 liters, the flow of the oxygen is raised in the range of 0.2 liter amount per minute 0.04.
- 8. the production method of planar vertical bilateral diffusion metal oxide transistor as claimed in claim 1, it is characterised in that： The N-type substrate is the dense substrate of N-type, and extension is lightly doped for N-type in the N-type extension.
- 9. the production method of planar vertical bilateral diffusion metal oxide transistor as claimed in claim 1, it is characterised in that： The material of the front metal includes Al-Si-Cu alloy.
- 10. the production method of planar vertical bilateral diffusion metal oxide transistor as claimed in claim 1, its feature exist In：The back metal includes titanium, nickel, the composite bed of silver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711364914.6A CN108010848A (en) | 2017-12-18 | 2017-12-18 | The production method of planar vertical bilateral diffusion metal oxide transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711364914.6A CN108010848A (en) | 2017-12-18 | 2017-12-18 | The production method of planar vertical bilateral diffusion metal oxide transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108010848A true CN108010848A (en) | 2018-05-08 |
Family
ID=62059531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711364914.6A Pending CN108010848A (en) | 2017-12-18 | 2017-12-18 | The production method of planar vertical bilateral diffusion metal oxide transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108010848A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6159805A (en) * | 1995-06-16 | 2000-12-12 | Stmicroelectronics S.R.L. | Semiconductor electronic device with autoaligned polysilicon and silicide control terminal |
| US20150162431A1 (en) * | 2013-12-09 | 2015-06-11 | Micrel, Inc. | Planar vertical dmos transistor with reduced gate charge |
-
2017
- 2017-12-18 CN CN201711364914.6A patent/CN108010848A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6159805A (en) * | 1995-06-16 | 2000-12-12 | Stmicroelectronics S.R.L. | Semiconductor electronic device with autoaligned polysilicon and silicide control terminal |
| US20150162431A1 (en) * | 2013-12-09 | 2015-06-11 | Micrel, Inc. | Planar vertical dmos transistor with reduced gate charge |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9985015B2 (en) | Semiconductor device having improved core and input/output device reliability | |
| JP5864784B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| WO2016015501A1 (en) | Tunneling transistor structure and manufacturing method therefor | |
| WO2013077068A1 (en) | Method for manufacturing semiconductor device | |
| CN103000534A (en) | Manufacture method of groove-type P-type metal oxide semiconductor power transistor | |
| CN105118857A (en) | Method for manufacturing trench type MOSFET (metal-oxide-semiconductor field-effect transistor) | |
| CN108109920A (en) | The production method of planar vertical bilateral diffusion metal oxide transistor | |
| CN108054211A (en) | Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof | |
| CN108010848A (en) | The production method of planar vertical bilateral diffusion metal oxide transistor | |
| JP2012004360A (en) | Method of manufacturing semiconductor device | |
| CN104347370A (en) | Method for improving negative bias temperature stability of grid of PMOS device | |
| CN108110056B (en) | Vertical double-diffused field effect transistor and manufacturing method thereof | |
| CN102931081B (en) | Manufacturing method for semiconductor device with field barrier layer | |
| CN108054210B (en) | Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof | |
| CN105097545A (en) | Trench type VDMOS device and manufacturing method thereof | |
| CN107919398A (en) | Half superjunction devices and its manufacture method | |
| CN108133894B (en) | Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof | |
| CN104981896A (en) | Semiconductor device and manufacturing method for same | |
| CN107316863A (en) | Transient Voltage Suppressor and preparation method thereof | |
| CN108054099B (en) | Method for manufacturing semiconductor power device | |
| CN108091575B (en) | Junction field effect transistor and manufacturing method thereof | |
| CN108110044A (en) | Semiconductor power device and preparation method thereof | |
| KR100779402B1 (en) | Method for manufacturing semiconductor device | |
| CN102956474B (en) | Manufacturing method of semiconductor devices | |
| CN108054205A (en) | Radio frequency triode and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180508 |