CN108109920A - The production method of planar vertical bilateral diffusion metal oxide transistor - Google Patents
The production method of planar vertical bilateral diffusion metal oxide transistor Download PDFInfo
- Publication number
- CN108109920A CN108109920A CN201711364932.4A CN201711364932A CN108109920A CN 108109920 A CN108109920 A CN 108109920A CN 201711364932 A CN201711364932 A CN 201711364932A CN 108109920 A CN108109920 A CN 108109920A
- Authority
- CN
- China
- Prior art keywords
- polysilicon layer
- type
- production method
- gate oxide
- planar vertical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000009792 diffusion process Methods 0.000 title claims abstract description 23
- 230000002146 bilateral effect Effects 0.000 title claims abstract description 22
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 22
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 8
- 230000003213 activating effect Effects 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 230000000717 retained effect Effects 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000010936 titanium Substances 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910018594 Si-Cu Inorganic materials 0.000 claims description 3
- 229910008465 Si—Cu Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229940090044 injection Drugs 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of production method of planar vertical bilateral diffusion metal oxide transistor comprises the following steps：N-type extension with N-type substrate is provided, gate oxide and polysilicon layer are formed in the N-type extension, the polysilicon layer is performed etching using photoresist to remove partial polysilicon layer, remaining another part polysilicon layer polysilicon layer associated with as grid and mutually；The photoresist is removed, thermal oxide is carried out to the remaining polysilicon layer so as to form thermal oxide layer on the polysilicon layer surface；P-type ion implanting is carried out in the N-type extension；Ion is injected to the p-type and forms PXing Ti areas into line activating and propulsion；By photoetching process, source region position is defined, and performs etching removal part gate oxide to the gate oxide using another photoresist, the gate oxide below the polysilicon layer is retained.The thermal oxide layer can protect the polysilicon layer, avoid damaging in etching technics of the polysilicon layer when defining source region position.
Description
【Technical field】
The present invention relates to semiconductor fabrication process technical fields, particularly, are related to a kind of planar vertical double diffused metal
The production method of oxide transistor.
【Background technology】
It is by source and body ion implanting in plane VDMOS (vertical DMOS transistor)
Transverse diffusion distance difference forms raceway groove, it is widely used in field of switch power.
In plane VDMOS techniques, gate oxide thickness generally between 800 angstroms~1200 angstroms, etching polysilicon it
Afterwards, the loss of gate oxide is also right in 100 Izods, so after etching polysilicon, also has dioxy at least 700 angstroms remaining in source region
SiClx layer.If source region injection ion is arsenic (symbol of element As), then 700 angstroms of oxidated layer thickness is undoubtedly blocked up, arsenic
Ion is difficult to penetrate so thick oxide layer and be injected into inside silicon and go.It, generally all can be so in plane VDMOS techniques
Increase the etching of a step silica before source region ion implanting, between thickness is etched into 200 angstroms~300 angstroms, in favor of source region
Ion implanting.In traditional handicraft, this step silica etching is generally placed upon after source region photoetching.In the design of VDMOS, in source region
After photoetching, the area of grid that source region closes polysilicon is all exposed.So in the etching of silica, unavoidably
Meeting be damaged to polysilicon layer, this is that we are unwilling to see.
From the above, it may be appreciated that in existing plane VDMOS techniques, after oxide layer etching, the surface of polysilicon layer may be same
When can be damaged in etching technics, after damage, the threshold voltage of semiconductor devices can fluctuate, and can also influence device
Reliability.
【The content of the invention】
One of purpose of the present invention, which is to solve above-mentioned at least one technical problem to provide a kind of plane, hangs down
The production method of straight bilateral diffusion metal oxide transistor.
A kind of production method of planar vertical bilateral diffusion metal oxide transistor comprises the following steps：
N-type extension with N-type substrate is provided, gate oxide and polysilicon layer are formed in the N-type extension, uses light
Photoresist performs etching the polysilicon layer to remove partial polysilicon layer, and remaining another part polysilicon layer is as grid
And mutually associated with polysilicon layer；
The photoresist is removed, thermal oxide is carried out so as in polysilicon layer surface shape to the remaining polysilicon layer
Into thermal oxide layer；
P-type ion implanting is carried out in the N-type extension；
Ion is injected to the p-type and forms PXing Ti areas into line activating and propulsion；
By photoetching process, source region position is defined, and the gate oxide is performed etching using another photoresist
Except part gate oxide, the gate oxide below the polysilicon layer is retained；
Another photoresist is removed, N-type region domain is formed as source region in the p-type body surface, on the polysilicon layer top
Gate oxide side wall below portion and side wall, the polysilicon layer forms dielectric layer；
Front metal is formed on the PXing Ti areas, the source region and the dielectric layer；
In the N-type substrate back metal is formed away from the N-type extension one side.
In one embodiment, the thickness of the gate oxide is in the range of 800 angstroms to 1200 angstroms.
In one embodiment, the temperature of the thermal oxide is in the range of 900 degrees Celsius to 1000 degrees Celsius.
In one embodiment, it is described to perform etching removal part grid oxygen to the gate oxide using another photoresist
In the step of changing layer, the thickness of the part gate oxide of removal is equal to the thickness of the thermal oxide layer.
In one embodiment, the thickness of the gate oxide is 1000 angstroms, and the thickness of the thermal oxide layer is 700
Angstrom.
In one embodiment, the p-type ion includes boron, and the dosage of the p-type ion implanting is every square centimeter 1
13 powers in the range of 15 powers every square centimeter gone, the energy of the p-type ion implanting is in 600KEV to 1000KEV
In the range of.
In one embodiment, to the p-type inject ion into line activating and promote form PXing Ti areas the step of temperature
Degree in the range of 900 degrees Celsius to 1200 degrees Celsius, the time in the range of 50 minutes to 200 minutes, the gas bag that is passed through
Nitrogen and oxygen are included, the flow of the nitrogen is in the range of per minute 8 are raised to 12 liters, and the flow of the oxygen is per minute
0.04 is raised in the range of 0.2 liter.
In one embodiment, the N-type substrate is the dense substrate of N-type, and extension is lightly doped for N-type in the N-type extension.
In one embodiment, the material of the front metal includes Al-Si-Cu alloy.
In one embodiment, the back metal includes titanium, nickel, the composite bed of silver.
Compared to the prior art, in the production method of planar vertical bilateral diffusion metal oxide transistor of the present invention, by
There is thermal oxide layer protection in polysilicon layer surface, to the damage problem of polysilicon when completely solving etching, avoid polysilicon layer
The problem of damaging the influence device reliability that may occur.
【Description of the drawings】
To describe the technical solutions in the embodiments of the present invention more clearly, used in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the flow chart of the production method of planar vertical bilateral diffusion metal oxide transistor of the present invention.
Fig. 2-Fig. 7 is each step of the production method of planar vertical bilateral diffusion metal oxide transistor shown in Fig. 1
Structure diagram.
Main element symbol description
N-type substrate 1；N-type extension 2；Gate oxide 3；Polysilicon layer 4；Thermal oxide layer 5；PXing Ti areas；Photoresist 7；Source region
8；Dielectric layer 9；Front metal 10；Back metal 11；Step S1-S8
【Specific embodiment】
The technical solution in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only the part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
All other embodiment that technical staff is obtained without making creative work belongs to the model that the present invention protects
It encloses.
- Fig. 7 is please referred to Fig.1, Fig. 1 is the production method of planar vertical bilateral diffusion metal oxide transistor of the present invention
Flow chart, Fig. 2-Fig. 7 are the knot of each step of the production method of planar vertical bilateral diffusion metal oxide transistor shown in Fig. 1
Structure schematic diagram.The production method of the planar vertical bilateral diffusion metal oxide transistor comprises the following steps S1-S8.
Referring to Fig. 2, providing the N-type extension 2 with N-type substrate 1, grid oxygen is formed in the N-type extension 2 by step S1
Change layer 3 and polysilicon layer 4, the polysilicon layer 4 is performed etching using photoresist 7 to remove partial polysilicon layer 4, it is remaining
Another part polysilicon layer 4 as grid and mutually associated with polysilicon layer.Specifically, the N-type substrate 1 is the dense substrate of N-type,
Extension is lightly doped for N-type in the N-type extension 2.The thickness of the gate oxide 3 is in the range of 800 angstroms to 1200 angstroms.
Step S2, referring to Fig. 3, remove the photoresist 7, the remaining polysilicon layer 4 is carried out thermal oxide so as to
Thermal oxide layer 5 is formed on 4 surface of polysilicon layer.Specifically, the temperature of the thermal oxide is Celsius to 1000 at 900 degrees Celsius
In the range of degree.The thickness of the gate oxide 3 can be 1000 angstroms, and the thickness of the thermal oxide layer 5 can be 700 angstroms.
Step S3, referring to Fig. 4, carrying out p-type ion implanting in the N-type extension 2.Specifically, the p-type ion includes
Boron, the dosage of the p-type ion implanting every square centimeter 1 13 powers in the range of 15 powers every square centimeter gone,
The energy of the p-type ion implanting is in the range of 600KEV to 1000KEV.
Step S4, referring to Fig. 5, inject ion to the p-type forms PXing Ti areas 6 into line activating and propulsion.Specifically,
Ion is injected to the p-type into line activating and promotes the temperature for the step of forming PXing Ti areas 6 Celsius to 1200 at 900 degrees Celsius
In the range of degree, the time, the gas being passed through included nitrogen and oxygen, the nitrogen in the range of 50 minutes to 200 minutes
In the range of per minute 8 are raised to 12 liters, the flow of the oxygen is raised to per minute 0.04 in the range of 0.2 liter flow.
Step S5 referring to Fig. 6, by photoetching process, defines source region position, and using another photoresist to the grid
Oxide layer 3 performs etching removal part gate oxide 3, and the gate oxide 3 of 4 lower section of polysilicon layer is retained.Specifically, go
The thickness of the part gate oxide 3 removed is equal to the thickness of the thermal oxide layer 5.
Step S6 referring to Fig. 7, removing another photoresist, forms N-type region domain on 6 surface of PXing Ti areas as source region
8,3 side wall of gate oxide below 4 top of polysilicon layer and side wall, the polysilicon layer 4 forms dielectric layer 9.
Step S7, referring to Fig. 7, forming front metal on the PXing Ti areas 6, the source region 8 and the dielectric layer
10.Specifically, the material of the front metal 10 includes Al-Si-Cu alloy.
Step S8, referring to Fig. 7, forming back metal 11 away from 2 one side of N-type extension in the N-type substrate 1.Tool
Body, the back metal 11 includes titanium, nickel, the composite bed of silver.
Compared to the prior art, in the production method of planar vertical bilateral diffusion metal oxide transistor of the present invention, by
There is thermal oxide layer 5 to protect in 4 surface of polysilicon layer, to the damage problem of polysilicon when completely solving etching, avoid more
Crystal silicon layer 4 damages the problem of influence device reliability that may occur.
Above-described is only embodiments of the present invention, it should be noted here that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
It encloses.
Claims (10)
1. a kind of production method of planar vertical bilateral diffusion metal oxide transistor, it is characterised in that：The production method
Comprise the following steps：
N-type extension with N-type substrate is provided, gate oxide and polysilicon layer are formed in the N-type extension, uses photoresist
The polysilicon layer is performed etching to remove partial polysilicon layer, remaining another part polysilicon layer is as grid and mutually
Associated with polysilicon layer；
The photoresist is removed, thermal oxide is carried out to the remaining polysilicon layer so as to form heat on the polysilicon layer surface
Oxide layer；
P-type ion implanting is carried out in the N-type extension；
Ion is injected to the p-type and forms PXing Ti areas into line activating and propulsion；
By photoetching process, source region position is defined, and removal portion is performed etching to the gate oxide using another photoresist
Point gate oxide, the gate oxide below the polysilicon layer are retained；
Remove another photoresist, N-type region domain formed as source region in the p-type body surface, at the top of the polysilicon layer and
Gate oxide side wall below side wall, the polysilicon layer forms dielectric layer；
Front metal is formed on the PXing Ti areas, the source region and the dielectric layer；
In the N-type substrate back metal is formed away from the N-type extension one side.
2. the production method of planar vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The thickness of the gate oxide is in the range of 800 angstroms to 1200 angstroms.
3. the production method of planar vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The temperature of the thermal oxide is in the range of 900 degrees Celsius to 1000 degrees Celsius.
4. the production method of planar vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
In described the step of performing etching removal part gate oxide to the gate oxide using another photoresist, the part grid of removal
The thickness of oxide layer is equal to the thickness of the thermal oxide layer.
5. the production method of planar vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The thickness of the gate oxide is 1000 angstroms, and the thickness of the thermal oxide layer is 700 angstroms.
6. the production method of planar vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The p-type ion includes boron, and the dosage of the p-type ion implanting is gone in every square centimeter 1 13 powers to every square centimeter
In the range of 15 powers, the energy of the p-type ion implanting is in the range of 600KEV to 1000KEV.
7. the production method of planar vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
Ion is injected to the p-type into line activating and promotes the temperature for the step of forming PXing Ti areas at 900 degrees Celsius to 1200 degrees Celsius
In the range of, the time, the gas being passed through included nitrogen and oxygen, the stream of the nitrogen in the range of 50 minutes to 200 minutes
In the range of per minute 8 are raised to 12 liters, the flow of the oxygen is raised to per minute 0.04 in the range of 0.2 liter amount.
8. the production method of planar vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The N-type substrate is the dense substrate of N-type, and extension is lightly doped for N-type in the N-type extension.
9. the production method of planar vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The material of the front metal includes Al-Si-Cu alloy.
10. the production method of planar vertical bilateral diffusion metal oxide transistor as described in claim 1, feature exist
In：The back metal includes titanium, nickel, the composite bed of silver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711364932.4A CN108109920A (en) | 2017-12-18 | 2017-12-18 | The production method of planar vertical bilateral diffusion metal oxide transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711364932.4A CN108109920A (en) | 2017-12-18 | 2017-12-18 | The production method of planar vertical bilateral diffusion metal oxide transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108109920A true CN108109920A (en) | 2018-06-01 |
Family
ID=62209786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711364932.4A Pending CN108109920A (en) | 2017-12-18 | 2017-12-18 | The production method of planar vertical bilateral diffusion metal oxide transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108109920A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113707545A (en) * | 2021-08-18 | 2021-11-26 | 深圳市美浦森半导体有限公司 | Method and device for improving avalanche characteristic of MOSFET (Metal-oxide-semiconductor field Effect transistor) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1897304A (en) * | 2006-06-16 | 2007-01-17 | 广州南科集成电子有限公司 | Planar mono-silicon double-metal layer power device and its production |
| US20150380541A1 (en) * | 2014-06-26 | 2015-12-31 | Renesas Electronics Corporation | Manufacturing method of semiconductor device and semiconductor device |
| CN105304492A (en) * | 2014-07-30 | 2016-02-03 | 北大方正集团有限公司 | Semiconductor device and manufacture method thereof |
-
2017
- 2017-12-18 CN CN201711364932.4A patent/CN108109920A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1897304A (en) * | 2006-06-16 | 2007-01-17 | 广州南科集成电子有限公司 | Planar mono-silicon double-metal layer power device and its production |
| US20150380541A1 (en) * | 2014-06-26 | 2015-12-31 | Renesas Electronics Corporation | Manufacturing method of semiconductor device and semiconductor device |
| CN105304492A (en) * | 2014-07-30 | 2016-02-03 | 北大方正集团有限公司 | Semiconductor device and manufacture method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113707545A (en) * | 2021-08-18 | 2021-11-26 | 深圳市美浦森半导体有限公司 | Method and device for improving avalanche characteristic of MOSFET (Metal-oxide-semiconductor field Effect transistor) |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109037208B (en) | Improve the two-way false grid deep trap electrostatic protection device and preparation method thereof of failure voltage | |
| JP5671867B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN105304696A (en) | Variation of lateral doping (VLD) junction termination structure for semiconductor devices and manufacturing method thereof | |
| JP2013110331A (en) | Semiconductor device manufacturing method | |
| CN108109920A (en) | The production method of planar vertical bilateral diffusion metal oxide transistor | |
| CN107316863B (en) | Transient Voltage Suppressor and preparation method thereof | |
| CN108054211A (en) | Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof | |
| JP2016086136A (en) | Method of manufacturing semiconductor device | |
| CN104599972B (en) | A kind of semiconductor devices and forming method thereof | |
| CN104347370A (en) | Method for improving negative bias temperature stability of grid of PMOS device | |
| CN108110056B (en) | Vertical double-diffused field effect transistor and manufacturing method thereof | |
| CN102931081B (en) | Manufacturing method for semiconductor device with field barrier layer | |
| CN106098561A (en) | The manufacture method of a kind of MOSFET element and device thereof | |
| CN108010848A (en) | The production method of planar vertical bilateral diffusion metal oxide transistor | |
| CN105097545A (en) | Trench type VDMOS device and manufacturing method thereof | |
| CN108133963A (en) | Field-effect tube and preparation method thereof | |
| CN107919398A (en) | Half superjunction devices and its manufacture method | |
| CN104981896A (en) | Semiconductor device and manufacturing method for same | |
| CN108054210B (en) | Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof | |
| CN108133894B (en) | Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof | |
| CN105551944A (en) | Manufacturing method for power transistor | |
| CN108110044A (en) | Semiconductor power device and preparation method thereof | |
| CN108054099A (en) | The production method of semiconductor power device | |
| CN105023831B (en) | The manufacturing method of polysilicon resistance in CMOS technology | |
| CN104681444B (en) | A kind of method for improving trench VDMOS device gate oxide breakdown voltage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180601 |