CN108010836A - Rf-ldmos短栅低方阻值栅硅化物的形成方法 - Google Patents
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- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 4
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Abstract
本发明公开了一种RF‑LDMOS短栅低方阻值栅硅化物的形成方法,使用硅化物低阻栅、增加隔离等工艺技术以及优化单元器件结构及多子管并联方式,最终设计成低寄生效应的大栅宽LDMOS高功率密度版图。在0.25微米栅长的栅条上,经过金属和硅的物理‑化学反应形成的化合态,使其导电特性介于金属和硅之间,从而大大减少多晶栅的连接电阻。其工艺制作概括为:主要措施是利用Spacer技术,使得在多晶硅栅上打开硅化物形成窗口成为可能,然后是利用二步快速热退火法,形成栅硅化物,将栅方块电阻降低到设计值每方块0.5欧姆左右,对于提高器件的特征频率有积极的意义。
Description
技术领域
本发明涉及一种RF-LDMOS短栅低方阻值栅硅化物的形成方法,涉及一种水平沟道LDMOS器件在进行版图优化的基础上,工艺过程中使用三明治结构进行的自对准形成硅化物的成形工艺,属于微电子技术领域。
背景技术
低电阻栅不仅可以提高LDMOS器件的高频性能,提高输出增益;也是实现大栅宽版图,提高单芯片输出功率,研制高功率器件的必要条件。低阻栅的制备技术是LDMOS晶体管芯片制造工艺过程中的最关键工艺技术之一。
LDMOS微波功率管的主要工作性能参数有:工作电压、工作频率、输出功率、工作带宽、带内增益、功率附加效率、脉冲宽度和占空比、输入插损、输出负载失配比(VSWR)等。
LDMOS微波功率管的主要性能参数取决于LDMOS芯片和封装(含匹配网络)的主要电学和热学参数。
除栅长Lg外,LDMOS芯片的主要电学参数有栅方块电阻Rg、导通电阻Rdson(或导通电压Vdson)、跨导Gm、漏极饱和电流Idsat、栅源电容Cgs、栅漏电容Cgd、漏源电容Cds以及版图结构产生的寄生效应;热学参数主要是温度分布的均匀性。
LDMOS微波功率管主要性能与LDMOS芯片性能的关联,如表格所示:
Lg | Rg | Rdson | Gm | Idsat | Cgs | Cgd | Cds | 版图结构 | |
工作电压 | + | ++ | ++ | ++ | + | ++ | + | ||
工作频率 | ++ | ++ | + | ++ | + | ++ | + | + | ++ |
输出功率 | + | ++ | + | ++ | + | + | + | ++ | |
工作带宽 | ++ | ++ | ++ | + | ++ | + | |||
带内增益 | ++ | ++ | + | ++ | + | ++ | ++ | + | ++ |
LDMOS芯片的各性能参数,与栅长、栅氧厚度、栅硅化物、场板、LDD区和版图结构的具体设计和它们的形成工艺紧密相关;其热学性能和寄生效应,则与版图结构、芯片厚度及其贴片方式密切相关。
发明内容
为了克服上述问题,本发明提供一种RF-LDMOS短栅低方阻值栅硅化物的形成方法。
本发明的技术方案是提供一种RF-LDMOS短栅低方阻值栅硅化物的形成方法,其特征在于:所述方法使用硅化物低阻栅、增加隔离工艺技术以及优化单元器件结构及多子管并联方式,最终设计成低寄生效应的大栅宽LDMOS高功率密度版图;
所述方法包括如下步骤:
(1)采用原位掺杂多晶硅的方式进行多晶硅栅的淀积;
(2)进行多晶硅的光刻与刻蚀;
(3)利用Spacer技术,在多晶硅栅上打开硅化物形成窗口,制作侧墙spacer;
(4)在多晶硅上淀积一定厚度的的金属钴;
(5)进行第一次快速退火,使得金属钴与硅进行反应,形成硅化钴CoSi;
(6)湿法刻蚀使用混合液清除氧化层上不需要的钴淀积层;
(7)采用原位掺杂多晶硅的方式进行多晶硅栅的淀积200-250纳米;
(8)进行第二次快速退火,使得硅化钴CoSi与硅进一步进行反应,形成二硅化钴CoSi2。
进一步的,所述步骤(1)中,多晶硅栅淀积290-310纳米。
进一步的,所述步骤(4)中,金属钴的厚度为60-70纳米。
进一步的,所述步骤(5)中,形成硅化钴CoSi的条件为快速退火560度30秒。
进一步的,所述步骤(6)中,混合液采用NH4OH/H2O2/H20的混合液。
进一步的,所述步骤(8)中,形成二硅化钴CoSi2的条件为快速退火850度60秒。
本发明的有益效果是:本发明在0.25微米栅长的栅条上,经过金属和硅的物理-化学反应形成的化合态,使其导电特性介于金属和硅之间,从而大大减少多晶栅的连接电阻。其主要措施是利用Spacer技术,使得在多晶硅栅上打开硅化物形成窗口成为可能,然后是利用二步快速热退火法,形成栅硅化物,将栅方块电阻降低到设计值每方块0.5欧姆左右。
本发明在设计上优化单元器件结构及其并联方式,设计短栅低方阻值栅的元胞结构来实现大栅宽LDMOS高功率密度版图;在工艺上,在完成多晶栅刻蚀及源漏注入后,进行隔离氧化层的淀积,刻蚀等工艺后,以溅射的方式在多晶栅上淀积金属钴(Co),再进行多晶硅的淀积,刻蚀等,然后进行第一次快速升温退火处理(RTA1),使多晶硅表面和淀积的金属发生反应,形成金属硅化物;根据对第一次RTA1的温度的设定,使得Co金属只与多晶硅及单晶硅进行反应形成硅化物,而不与作为隔离用的氧化层进行反应,可视其为一种自对准过程;再用选择性强的湿法刻蚀(NH4OH/H2O2/H20的混合液)清除氧化层上不需要的金属淀积层,只留下栅极及源漏区的硅化物;进行第二次快速升温退火处理(RTA2)使得硅化物的方块电阻达到工艺要求。
附图说明
图1是本发明的方法示意图;
图2是本发明的多晶硅栅的光刻示意图;
图3是本发明的多晶硅栅的刻蚀示意图;
图4是本发明的钴厚度与方块电阻的关系曲线示意图;
图5是本发明的硅化物示意图;
图6是本发明的短栅增加隔离工艺技术以及多子管并联方式示意图;
图7是本发明的硅化物形成示意见图。
具体实施方式
为了使本发明实现的技术手段、创作特征、达成目的与功效易于明白了解,下面结合具体实施例,进一步阐述本发明。
如图1至图7所示,本发明的一种RF-LDMOS短栅低方阻值栅硅化物的形成方法,其特征在于:所述方法使用硅化物低阻栅、增加隔离工艺技术以及优化单元器件结构及多子管并联方式,最终设计成低寄生效应的大栅宽LDMOS高功率密度版图。
本发明主要针对降低栅方块电阻Rg采取方案,以提高RF-LDMOS的射频参数。
低阻栅的制备技术研究:
影响多晶硅栅上形成低电阻值硅化物的因素很多,如多晶硅栅形成后的侧边斜度及其与光刻线型和干法刻蚀条件的关系、硅化物金属的溅射参数和溅射厚度、形成硅化物的RTP温度和时间等等。
围绕影响多晶硅栅上形成低电阻值多晶硅硅化物的主要工艺因素;
1、多晶硅栅的光刻:曝光强度分片实验、同一刻蚀条件下X-SEM观察多晶硅栅的侧边斜度,找出侧边斜度与曝光强度的关系,确定多晶硅栅的最佳光刻曝光强度;
经过多组的试验,确定了光刻的最佳参数,得到了形貌为88度以上的的光刻胶侧面轮廓(如图2所示)。
2、多晶硅栅的刻蚀:在此光刻条件下,经过一系列的刻蚀优化,得到了台阶大于86度的多晶硅栅(如图3所示);
3、 硅化物的形成:
使用了金属钴作为与多晶硅进行反应形成硅化物,经过试验,得到以下的试验数据:
500℃时a-Si + Co →CoSi过程中Si与Co消耗比为1.82:1
592 ℃时a-Si + Co →CoSi过程中Si与Co消耗比为2.5:1
800 ℃时a-Si + Co →CoSi2过程中Si与Co消耗比为3.64:1
并结合不同钴厚度(400A/650A/170A)得到的接触电阻与现有的的100A钴硅化物现有数据整理,可以得到的钴厚度与方块电阻的关系曲线(如图4所示)。
最终得到了硅化物SEM(如图5所示)。
详细的实现方式为:版图设计上采用短栅增加隔离工艺技术以及多子管并联方式(如图6所示)。
栅岛(tab)并联一组多晶硅短栅,栅岛与栅岛也使用连线并联成栅条,栅条之间再进行并联形成总栅连线。所有短栅多次并联,最终形成低寄生效应的大栅宽LDMOS高功率密度版图。
工艺上制作0.25微米栅长的方阻为0.5欧姆左右的硅化物栅的形成方法,包括如下步骤:
(1)采用原位掺杂多晶硅的方式进行多晶硅栅的淀积300纳米;
(2)进行多晶硅的光刻与刻蚀;
(3)利用Spacer技术,在多晶硅栅上打开硅化物形成窗口,制作侧墙spacer;
(4)在多晶硅上淀积65纳米厚度的的金属钴;
(5)进行第一次快速退火,使得金属钴与硅进行反应,形成硅化钴CoSi,形成硅化钴CoSi的条件为快速退火560度30秒;
(6)湿法刻蚀使用NH4OH/H2O2/H20的混合液清除氧化层上不需要的钴淀积层;
(7)采用原位掺杂多晶硅的方式进行多晶硅栅的淀积200-250纳米;
(8)进行第二次快速退火,使得硅化钴CoSi与硅进一步进行反应,形成二硅化钴CoSi2,形成二硅化钴CoSi2的条件为快速退火850度60秒。
硅化物形成示意见图如图7所示。
通过上述对低阻栅的制备技术研究,得到了可以满足5~6G频率波段的RF-LDMOS对于多晶硅栅硅化物方块电阻值的要求。
以上实施例仅为本发明其中的一种实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (6)
1.一种RF-LDMOS短栅低方阻值栅硅化物的形成方法,其特征在于:所述方法使用硅化物低阻栅、增加隔离工艺技术以及优化单元器件结构及多子管并联方式,最终设计成低寄生效应的大栅宽LDMOS高功率密度版图;
所述方法包括如下步骤:
(1)采用原位掺杂多晶硅的方式进行多晶硅栅的淀积;
(2)进行多晶硅的光刻与刻蚀;
(3)利用Spacer技术,在多晶硅栅上打开硅化物形成窗口,制作侧墙spacer;
(4)在多晶硅上淀积一定厚度的的金属钴;
(5)进行第一次快速退火,使得金属钴与硅进行反应,形成硅化钴CoSi;
(6)湿法刻蚀使用混合液清除氧化层上不需要的钴淀积层;
(7)采用原位掺杂多晶硅的方式进行多晶硅栅的淀积200-250纳米;
(8)进行第二次快速退火,使得硅化钴CoSi与硅进一步进行反应,形成二硅化钴CoSi2。
2.根据权利要求1所述的RF-LDMOS短栅低方阻值栅硅化物的形成方法,其特征在于:所述步骤(1)中,多晶硅栅淀积290-310纳米。
3.根据权利要求1所述的RF-LDMOS短栅低方阻值栅硅化物的形成方法,其特征在于:所述步骤(4)中,金属钴的厚度为60-70纳米。
4.根据权利要求1所述的RF-LDMOS短栅低方阻值栅硅化物的形成方法,其特征在于:所述步骤(5)中,形成硅化钴CoSi的条件为快速退火560度30秒。
5.根据权利要求1所述的RF-LDMOS短栅低方阻值栅硅化物的形成方法,其特征在于:所述步骤(6)中,混合液采用NH4OH/H2O2/H20的混合液。
6.根据权利要求1所述的RF-LDMOS短栅低方阻值栅硅化物的形成方法,其特征在于:所述步骤(8)中,形成二硅化钴CoSi2的条件为快速退火850度60秒。
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Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010003056A1 (en) * | 1999-12-03 | 2001-06-07 | Shin Hashimoto | Semiconductor device and method for fabricating the same |
US20080044989A1 (en) * | 2006-08-21 | 2008-02-21 | Samsung Electronics Co., Ltd. | Photomask and its method of manufacture |
KR20100066762A (ko) * | 2008-12-10 | 2010-06-18 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
US20110266597A1 (en) * | 2010-04-30 | 2011-11-03 | Hynix Semiconductor Inc. | Semiconductor device and method for manufacturing the same |
US20130037888A1 (en) * | 2011-08-10 | 2013-02-14 | Samsung Electronics Co., Ltd. | Semiconductor device |
CN104241112A (zh) * | 2013-06-09 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | 非晶半导体材料的形成方法及金属硅化物的形成方法 |
CN104347374A (zh) * | 2013-07-30 | 2015-02-11 | 北大方正集团有限公司 | 半导体器件制造方法 |
CN104465404A (zh) * | 2014-12-24 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | 射频ldmos器件的制造方法 |
CN104835728A (zh) * | 2014-02-12 | 2015-08-12 | 北大方正集团有限公司 | 在多晶硅上形成金属硅化物的方法和半导体器件 |
-
2017
- 2017-12-12 CN CN201711317527.7A patent/CN108010836A/zh active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010003056A1 (en) * | 1999-12-03 | 2001-06-07 | Shin Hashimoto | Semiconductor device and method for fabricating the same |
US20080044989A1 (en) * | 2006-08-21 | 2008-02-21 | Samsung Electronics Co., Ltd. | Photomask and its method of manufacture |
KR20100066762A (ko) * | 2008-12-10 | 2010-06-18 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
US20110266597A1 (en) * | 2010-04-30 | 2011-11-03 | Hynix Semiconductor Inc. | Semiconductor device and method for manufacturing the same |
US20130037888A1 (en) * | 2011-08-10 | 2013-02-14 | Samsung Electronics Co., Ltd. | Semiconductor device |
CN104241112A (zh) * | 2013-06-09 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | 非晶半导体材料的形成方法及金属硅化物的形成方法 |
CN104347374A (zh) * | 2013-07-30 | 2015-02-11 | 北大方正集团有限公司 | 半导体器件制造方法 |
CN104835728A (zh) * | 2014-02-12 | 2015-08-12 | 北大方正集团有限公司 | 在多晶硅上形成金属硅化物的方法和半导体器件 |
CN104465404A (zh) * | 2014-12-24 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | 射频ldmos器件的制造方法 |
Non-Patent Citations (1)
Title |
---|
张波等: "《功率半导体器件电场优化技术》", 31 December 2015, 电子科技大学出版社 * |
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