CN107978604B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
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Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, and forming a patterned top silicon-containing structure layer and an interlayer dielectric layer surrounding the patterned top silicon-containing structure layer on the semiconductor substrate; performing a first etch back to remove a certain amount of the interlayer dielectric layer and simultaneously form a polymer on the surface of the interlayer dielectric layer and the surface of the top silicon-containing structure layer; performing a second etch back on the interlayer dielectric layer by a remote plasma etch process; forming silicide on the exposed upper region of the patterned top silicon-containing structure layer. The manufacturing method can well realize the inter-layer dielectric layer etching back, simultaneously does not generate the problems of polysilicon damage, limited etching depth control capability and the like, and the inter-layer dielectric layer after etching back has good uniformity. The semiconductor device and the electronic device have improved performance and yield due to the manufacturing method.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
With the development of semiconductor process technology, flash memories (flash memories) with faster access speed have been developed for memory devices. Flash memory has the characteristics of being capable of storing, reading and erasing information for many times, and the stored information does not disappear after power failure, so flash memory has become a nonvolatile memory widely used in personal computers and electronic devices. NAND flash memory is widely used in the field where read/write requirements are high due to its large storage capacity and relatively high performance. Recently, the capacity of NAND flash memory chips has reached 2GB, and the size has rapidly increased. Solid state disks based on NAND flash memory chips have been developed and used as storage devices in portable computers. Therefore, in recent years, NAND flash memories are widely used as storage devices in embedded systems, and also as storage devices in personal computer systems.
For NAND flash memory, it is necessary to form silicide such as NiSi on Word Lines (WL) at technology nodes of 32nm and below. Etch back of the inter-layer dielectric (ILD) is a critical process prior to the word line silicidation process. In the etch back of the interlayer dielectric layer, it is very important to meet the requirements of the etching standard, such as the requirement of reducing plasma damage on the word line during the etch back process, and simultaneously realizing the required etching depth of the oxide recess (stress).
However, the current inter-layer dielectric etch back process does not satisfy the above requirements well, such as severe polysilicon damage, and oxide fence (fenge) defect and poor uniformity when the etch back process is performed using a continuous high density plasma etch process. While these problems may be ameliorated if the etch back is performed using a remote plasma etch process, the side effect of limited depth control capability is encountered.
Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to at least partially solve the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Aiming at the defects of the prior art, the invention provides a novel manufacturing method of a semiconductor device, which can well realize the inter-layer dielectric layer back etching, simultaneously does not generate the problems of polysilicon damage, limited etching depth control capability and the like, and the inter-layer dielectric layer after back etching has good uniformity.
In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, and forming a patterned top silicon-containing structure layer and an interlayer dielectric layer surrounding the patterned top silicon-containing structure layer on the semiconductor substrate; performing a first etch back on the interlayer dielectric layer by a high oxide-to-silicon selective etching process to remove a certain amount of the interlayer dielectric layer and simultaneously form a polymer on the surface of the interlayer dielectric layer and the surface of the top silicon-containing structure layer; performing a second etch-back process on the interlayer dielectric layer through a remote plasma etching process to further remove a certain amount of the interlayer dielectric layer, so that the etch-back depth meets the set requirement to expose the upper region of the patterned top silicon-containing structure layer; and forming silicide in the exposed upper region of the patterned top silicon-containing structure layer, wherein the thickness of the polymer on the surface of the top silicon-containing structure layer is larger than that of the polymer on the surface of the interlayer dielectric layer.
Further, the high oxide-to-silicon selective etching process is a synchronous pulse plasma etching process.
Further, CxFy based etching gases are used in the simultaneous pulsed plasma etch process.
Further, the oxide to silicon selectivity is 3: 1 or more.
Further, the remote plasma etch process employs a chemical downstream etch process or a SiCoNi etch process.
Further, the method also comprises the following steps: the etching residues are removed by a wet process or an ashing method.
Further, the ashing method employs N2, O2, or H2 plasma.
Further, the patterned top silicon-containing structure layer is a patterned word line polysilicon layer.
Further, the patterned top silicon-containing structure layer is a patterned silicon fin.
The manufacturing method of the semiconductor device provided by the invention divides the etching back of the interlayer dielectric layer into two steps, wherein in the first step, a high oxide is adopted to etch the silicon in a selective etching process to a certain depth, polymers are formed on the surface of the interlayer dielectric layer and the surface of the top silicon-containing structure layer in the etching process, and the thickness of the polymer on the surface of the top silicon-containing structure layer is larger than that of the polymer on the surface of the interlayer dielectric layer, so that the polymer can protect the silicon-containing structure layer from being damaged; the second step adopts a remote plasma etching process, can further etch a certain depth and remove the oxide fence defects and poor uniformity problems formed by the first etching process. The manufacturing method of the semiconductor device provided by the invention can well control the etching depth by adjusting the first etching process and the second etching process, so that the etching back depth of the interlayer dielectric layer meets the requirement.
In another aspect, the present invention provides a semiconductor device fabricated by the above method, the semiconductor device comprising: the semiconductor device comprises a semiconductor substrate, wherein a patterned top silicon-containing structure layer and an interlayer dielectric layer surrounding the patterned top silicon-containing structure layer are formed on the semiconductor substrate, the height of the interlayer dielectric layer is lower than that of the patterned top silicon-containing structure layer, and silicide is formed on the part, not surrounded by the interlayer dielectric layer, of the patterned top silicon-containing structure layer.
Further, the patterned top silicon-containing structure layer is a patterned word line polysilicon layer.
Further, the patterned top silicon-containing structure layer is a patterned silicon fin.
The semiconductor device provided by the invention has silicide with good performance.
A further aspect of the invention provides an electronic device comprising a semiconductor device as described above and an electronic component connected to the semiconductor device.
The electronic device provided by the invention has similar advantages due to the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1A-1C schematically illustrate a conventional inter-layer dielectric etch-back process for a NAND device;
FIG. 2 is a flow chart illustrating steps in a method of fabricating a semiconductor device according to an embodiment of the present invention;
fig. 3A to 3D are schematic cross-sectional views of a semiconductor device obtained by sequentially performing steps according to a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
As mentioned above, in the current inter-layer dielectric layer etch-back process, the requirement of the etching standard cannot be well met, and the performance of the final device is affected. In order to better understand the present invention, an etching back method of an interlayer dielectric layer of a NAND flash memory is first described with reference to fig. 1A to 1C.
Fig. 1A to 1C schematically illustrate a conventional inter-layer dielectric etch-back process of a NAND device. As shown in fig. 1A to fig. 1C, a gate stack and an interlayer dielectric layer 107 surrounding the gate stack are first formed on a semiconductor substrate 100, wherein the gate stack includes a tunnel oxide layer 101, a floating gate 102, an inter-gate dielectric layer 103, a control gate 104, a hard mask layer 105 and a spacer 106 located on a sidewall of the gate stack, which are sequentially formed from bottom to top; next, as shown in fig. 1B, an etch back of the interlayer dielectric layer 107 is performed by a continuous high density plasma etching to remove the hard mask layer 105 and a portion of the interlayer dielectric layer 107 and a portion of the spacer 106 to expose the top region of the control gate 104, so that a sub-line silicide can be formed on the top region of the control gate 104, however, as shown in fig. 1B and as described above, this method causes severe polysilicon damage (i.e., control gate damage), as well as oxide fence (the upper spacer is not removed, resulting in unexposed control chamber) defects and poor uniformity (the interlayer dielectric layer 107 becomes less uniform after etch back, thickness is not uniform throughout, not shown). Or as shown in fig. 1C, the etch back of the interlayer dielectric layer 107 is performed using a remote plasma etching process, although these problems can be improved, a side effect of limited depth control capability is encountered because the etch back of the interlayer dielectric layer 107 (oxide) using the remote plasma etching process encounters an etch saturation problem, and when etching to a certain depth, the etch depth cannot be increased even if the etching time is further increased, and thus the control gate exposure depth control and requirement cannot be easily satisfied.
In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, which is used to implement a good inter-layer dielectric layer etch-back, as shown in fig. 2, the method comprising: step 201, providing a semiconductor substrate, and forming a patterned top silicon-containing structure layer and an interlayer dielectric layer surrounding the patterned top silicon-containing structure layer on the semiconductor substrate; step 202, performing a first etch back on the interlayer dielectric layer by a high oxide to silicon selective etching process to remove a certain amount of the interlayer dielectric layer, and simultaneously forming a polymer on the surface of the interlayer dielectric layer and the surface of the top silicon-containing structure layer; step 203, performing a second etch-back on the interlayer dielectric layer through a remote plasma etching process to further remove a certain amount of the interlayer dielectric layer, so that the etch-back depth meets the set requirement to expose the upper region of the patterned top silicon-containing structure layer; step 204, forming silicide on the exposed upper region of the patterned top silicon-containing structure layer, wherein the thickness of the polymer on the surface of the top silicon-containing structure layer is greater than the thickness of the polymer on the surface of the interlayer dielectric layer.
According to the manufacturing method of the semiconductor device, the etching back of the interlayer dielectric layer is divided into two steps, the first step adopts a high-oxide to silicon selective etching process to etch a certain depth, polymers can be formed on the surface of the interlayer dielectric layer and the surface of the top silicon-containing structure layer in the etching process, and the thickness of the polymers on the surface of the top silicon-containing structure layer is larger than that of the polymers on the surface of the interlayer dielectric layer, so that the polymers can protect the silicon-containing structure layer from being damaged; the second step adopts a remote plasma etching process, can further etch a certain depth and remove the oxide fence defects and poor uniformity problems formed by the first etching process. The manufacturing method of the semiconductor device provided by the invention can well control the etching depth by adjusting the first etching process and the second etching process, so that the etching back depth of the interlayer dielectric layer meets the requirement.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 3A to 3D. In this embodiment, a method for manufacturing a semiconductor device according to the present invention is described by taking an example of etching back an interlayer dielectric layer of a NAND device.
First, as shown in fig. 3A, a semiconductor substrate 300 is provided, a gate stack is formed on the semiconductor substrate 300, and an interlayer dielectric layer 307 surrounding the gate stack.
Among them, the semiconductor substrate 300 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.
The gate stack includes a tunnel oxide layer 301, a floating gate 302, an inter-gate dielectric layer 303, a control gate 304, a hard mask layer 305, and a spacer 306 on the sidewall of the gate stack. The gate stack is fabricated using structures and formation methods commonly used in the art, for example, tunnel oxide layer 301 is illustratively a silicon oxide layer, which may be formed by methods such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), and the like. The floating gate 302 is illustratively formed of a semiconductor material such as polysilicon and is formed by one of selective Molecular Beam Epitaxy (MBE), metal organic chemical vapor deposition (MOCV), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG). The inter-gate dielectric layer 303 is a dielectric material such as oxide, nitride, etc., and preferably, in the present embodiment, the inter-gate dielectric layer 303 adopts an ONO structure (i.e., oxide-nitride-oxide), which has both good interface performance and good dielectric performance and a suitable thickness. The control gate 304 is illustratively made of a semiconductor material such as polysilicon, and is formed by one of selective Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG).
It may be formed by a thermal oxidation method, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.
The spacer 306 is made of a commonly used spacer material and formation method. Illustratively, an oxide is used for the spacer 306 in this embodiment.
The interlayer dielectric layer 307 is made of a conventional dielectric material such as USG, PSG, BPSG, etc., and is formed by FCVD (fluid chemical vapor deposition), spin coating, HARP (high aspect ratio process), etc.
Next, as shown in fig. 3B, a first etch back is performed on the interlayer dielectric layer 307 by a high oxide-to-silicon selective etching process to remove a certain amount of the interlayer dielectric layer, and a polymer 308 is formed on the surface of the interlayer dielectric layer 307 and the surface of the control gate 304.
The high oxide-to-silicon selective etching process can be various etching processes capable of realizing high oxide-to-silicon selectivity, and the high oxide-to-silicon selectivity is 3: 1 or more, for example, 40. And during the first etch back of the ild layer using a high oxide to silicon selective etch process, a byproduct, polymer 308, is deposited on the surface of the ild layer 307 and the surface of the top si-containing structure layer. The polymer 308 is highly selective to silicon due to the etch process, whereas the polymer formed on the top surface of the control gate 304 is thicker and the polymer formed on the surface of the interlayer dielectric 307 is thinner.
Illustratively, in the present embodiment, the first etch-back is performed by a synchronous pulse plasma etching process, by which a high oxide-to-silicon selectivity can be achieved, and a uniform thicker polymer 308A can be induced to form on the top surface of the control gate 304 as a protection layer, and a thinner polymer 308B can be induced to form on the surface of the interlayer dielectric layer 307 to facilitate the subsequent etching. The etching depth of the first etch back can be adjusted by controlling the thickness of the polymer in this step.
Illustratively, in this embodiment, a CxFy-based gas, such as one or more gases of C3F4, is used as the etching gas.
Next, as shown in fig. 3C, a second etch-back process is performed on the interlayer dielectric layer 307 by a remote plasma etching process to further remove a certain amount of the interlayer dielectric layer 307, so that the etch-back depth meets a set requirement to expose the upper region of the patterned control gate 304.
After the first etch back, the ild has been etched to a certain depth, a second etch back is then performed by a remote plasma etch process to further remove a certain amount of ild 307, such that the etch back depth meets a set requirement to expose an upper region of patterned control gate 304. Because the remote plasma etching process does not damage the polysilicon and is isotropic, the oxide fence defect and the interlayer dielectric layer non-uniform defect formed by the first etching process can be well removed.
Illustratively, in this embodiment, the remote plasma etch process employs a chemical downstream etch (chemical downstream etch), a SiCoNi etch, or other isotropic etch process. Chemical downstream etching is a commonly used remote plasma etching process that employs the principle of forming a plasma upstream and then introducing it into a downstream etch chamber to etch by reaction of the plasma with the layer being etched, thus achieving isotropy without damaging the polysilicon because there is no plasma bombardment.
The SiCoNi etching process is a commonly used cleaning process, and in this embodiment, the second etch-back is performed by using the SiCoNi etching process. The basic principle of the SiCoNi etching process is NF3/NH3 remote plasma etching and in-situ annealing, which are both completed in the same chamber. During the etching process, the wafer is placed on a pedestal with a temperature tightly controlled at 35 ℃, and the low power plasma converts NF3 and NH3 into ammonium fluoride (NH4F) and ammonium difluoride (equation 1). The fluoride condenses on the wafer surface and preferentially reacts with the oxide to form hexafluorosilicone ammonia ((NH4)2SiF6) (formula 2). The silicate can be sublimed in an environment above 70 ℃. During in situ annealing, the wafer is moved close to the heating element, the flowing hydrogen carries heat to the wafer, and the wafer is heated to above 100 ℃ in a short time, causing the hexafluoro-silicon ammonia to decompose into gaseous SiF4, NH3, and HF (equation 3) and be pumped away.
Generation of etchant: NF3+ NH3 → NH4F + NH4F.HF (1)
Etching process: NH4F or NH4F.HF + SiO2 → (NH4)2SiF6(solid) + H2O (2)
A sublimation process: (NH4)2SiF6(solid) → SiF4(g) + NH3(g) + HF (g) (3)
The high selectivity of oxide and silicon can be achieved by using a SiCoNi etching process to etch the inter-level dielectric layer 307 and the spacer 306 well, avoiding the occurrence of poor uniformity and oxide fence defects.
Finally, as shown in fig. 3D, the etching residues are removed and silicide is formed in the regions where the control gates 304 leak out.
Specifically, the etch residues, e.g., etch byproducts such as polymer 308, are first removed by a wet process (with a suitable solvent) or an ashing process (Ash).
Exemplarily, in the present embodiment, the etching residues are removed by an ashing method. Wherein the ashing process is performed using N2, O2, or Ar plasma (i.e., plasma formed by gases N2, O2, or Ar).
An over-silicidation process then forms silicide 309 in the exposed portions of the control gates 304, which is a process common in the art and not described further herein. Illustratively, in this embodiment, the silicide 309 is an NISi silicide.
Now that the process steps performed by the method according to the embodiment of the present invention are completed, it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps, but also other required steps before, during, or after the above steps, and a step of forming source/drain electrodes after or before forming the gate stack.
In the manufacturing method of the semiconductor device provided by the embodiment, the etching back of the interlayer dielectric layer is divided into two steps, the first step adopts a high-oxide to silicon selective etching process to etch a certain depth, and a polymer is formed on the surface of the interlayer dielectric layer and the top surface of the control gate in the etching process, and the thickness of the polymer on the top surface of the control gate is larger than that of the polymer on the surface of the interlayer dielectric layer, so that the polymer can protect the control gate from being damaged; the second step adopts a remote plasma etching process, can further etch a certain depth and remove the oxide fence defects and poor uniformity problems formed by the first etching process. According to the manufacturing method of the semiconductor device, the etching depth can be well controlled by adjusting the first etching process and the second etching process, so that the etching back depth of the interlayer dielectric layer meets the requirement.
It is to be understood that, although the present embodiment describes the method for manufacturing the semiconductor device according to the present invention by using the inter-layer dielectric layer etch-back of the NAND device, the method for manufacturing the semiconductor device according to the present invention is not limited thereto, and for example, the method for manufacturing the semiconductor device according to the present invention may be used for the inter-layer dielectric layer etch-back of the semiconductor device having the fin structure.
Example two
The present invention also provides a semiconductor device manufactured by the above method, as shown in fig. 3D, the semiconductor device including: the semiconductor device comprises a semiconductor substrate 300, wherein a gate stack and an interlayer dielectric layer 307 surrounding the gate stack are formed on the semiconductor substrate 300, the height of the interlayer dielectric layer 307 is lower than that of the gate stack, the gate stack comprises a tunneling oxide layer 301, a floating gate 302, an inter-gate dielectric layer 303, a control gate 304, a hard mask layer 305 and a gap wall 306 positioned on the side wall of the gate stack, which are sequentially formed from bottom to top, and silicide 309 is formed on the part, not surrounded by the interlayer dielectric layer 307, of the control gate 304.
The semiconductor device of the embodiment is formed with a control gate silicide which meets the requirements, so that good sub-line performance can be realized.
EXAMPLE III
Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: the semiconductor device comprises a semiconductor substrate, wherein a patterned top silicon-containing structure layer and an interlayer dielectric layer surrounding the patterned top silicon-containing structure layer are formed on the semiconductor substrate, the height of the interlayer dielectric layer is lower than that of the patterned top silicon-containing structure layer, and silicide is formed on the part, not surrounded by the interlayer dielectric layer, of the patterned top silicon-containing structure layer.
Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, may be formed in the semiconductor substrate. As an example, in the present embodiment, the constituent material of the semiconductor substrate is single crystal silicon.
Illustratively, the patterned top silicon-containing structure layer is a patterned word line polysilicon layer.
Illustratively, the patterned top silicon-containing structure layer is a patterned silicon fin.
The electronic component may be any electronic component such as a discrete device and an integrated circuit.
The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.
Wherein figure 4 shows an example of a handset. The exterior of the cellular phone 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.
The electronic device of the embodiment of the invention has better performance because the contained semiconductor device has the silicide meeting the requirement. The electronic device also has similar advantages.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (13)
1. A method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate, and forming a patterned top silicon-containing structure layer and an interlayer dielectric layer surrounding the patterned top silicon-containing structure layer on the semiconductor substrate;
performing a first etch back on the interlayer dielectric layer by a high oxide-to-silicon selective etching process to remove a certain amount of the interlayer dielectric layer and simultaneously form a polymer on the surface of the interlayer dielectric layer and the surface of the top silicon-containing structure layer;
performing a second etch-back process on the interlayer dielectric layer through a remote plasma etching process to further remove a certain amount of the interlayer dielectric layer, so that the etch-back depth meets the set requirement to expose the upper region of the patterned top silicon-containing structure layer;
forming silicide on the exposed upper region of the patterned top silicon-containing structure layer,
and the thickness of the polymer on the surface of the top silicon-containing structure layer is larger than that of the polymer on the surface of the interlayer dielectric layer.
2. The method of claim 1, wherein the high oxide-to-silicon selective etch process is a synchronous pulsed plasma etch process.
3. A method for manufacturing a semiconductor device according to claim 2, wherein a CxFy based etching gas is used in the simultaneous pulse plasma etching process.
4. The method of manufacturing a semiconductor device according to claim 2, wherein the selectivity of the oxide to silicon is 3: 1 or more.
5. The method of claim 2, wherein the remote plasma etching process is a chemical downstream etching process or a SiCoNi etching process.
6. The method for manufacturing a semiconductor device according to claim 1, further comprising the steps of:
the etching residues are removed by a wet process or an ashing method.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the ashing method uses N2, O2, or H2 plasma.
8. The method as claimed in any one of claims 1 to 7, wherein the patterned top silicon-containing structure layer is a patterned word line polysilicon layer.
9. The method as claimed in any one of claims 1 to 7, wherein the patterned top Si-containing structure layer is a patterned Si fin.
10. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 9, comprising: the semiconductor device comprises a semiconductor substrate, wherein a patterned top silicon-containing structure layer and an interlayer dielectric layer surrounding the patterned top silicon-containing structure layer are formed on the semiconductor substrate, the height of the interlayer dielectric layer is lower than that of the patterned top silicon-containing structure layer, and silicide is formed on the part, not surrounded by the interlayer dielectric layer, of the patterned top silicon-containing structure layer.
11. The semiconductor device of claim 10, wherein the patterned top silicon-containing structure layer is a patterned wordline polysilicon layer.
12. The semiconductor device of claim 10, wherein the patterned top silicon-containing structure layer is a patterned silicon fin.
13. An electronic device comprising a semiconductor device according to any one of claims 10 to 12 and an electronic component connected to the semiconductor device.
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| CN201610938708.0A CN107978604B (en) | 2016-10-24 | 2016-10-24 | Semiconductor device, manufacturing method thereof and electronic device |
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