CN107978604A - Semiconductor devices and preparation method thereof, electronic device - Google Patents
Semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN107978604A CN107978604A CN201610938708.0A CN201610938708A CN107978604A CN 107978604 A CN107978604 A CN 107978604A CN 201610938708 A CN201610938708 A CN 201610938708A CN 107978604 A CN107978604 A CN 107978604A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims abstract description 162
- 238000000034 method Methods 0.000 claims abstract description 85
- 239000011229 interlayer Substances 0.000 claims abstract description 81
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 77
- 239000010703 silicon Substances 0.000 claims abstract description 77
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 claims abstract description 33
- 229920000642 polymer Polymers 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 20
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000004380 ashing Methods 0.000 claims description 6
- 239000011469 building brick Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- 210000002381 plasma Anatomy 0.000 claims 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 13
- 230000007547 defect Effects 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007667 floating Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 229910019975 (NH4)2SiF6 Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910004014 SiF4 Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- -1 hexafluoro silicon ammonia Chemical compound 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000005915 ammonolysis reaction Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000001429 stepping effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic device, which includes：Semiconductor substrate is provided, patterned top is formed on the semiconductor substrate containing silicon structural layer and surrounds the interlayer dielectric layer of the patterned top containing silicon structural layer；The first etch-back is performed, to remove a certain amount of interlayer dielectric layer, while surface containing silicon structural layer forms polymer in interlayer dielectric layer surface and top；Second etch-back is performed to the interlayer dielectric layer by remote plasma etch technique；Silicide is formed in the upper area of the patterned top exposing containing silicon structural layer.The production method can realize interlayer dielectric layer etch-back very well, while the problems such as do not produce polysilicon damage and limited etch depth control ability, and interlayer dielectric layer uniformity is fine after etch-back.The semiconductor devices and electronic device cause performance and yield to improve due to above-mentioned production method.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
With the development of manufacture of semiconductor technology, the faster flash of access speed has been developed in terms of storage device
Device (flash memory).Flash memory has and can repeatedly be acted into deposit, reading and erasing of row information etc., and be stored in
The characteristic that information will not disappear after a loss of power, therefore, flash memory has become PC and electronic equipment is adopted extensively
A kind of nonvolatile memory.And NAND (NAND gate) fast storages are due to large storage capacity and relatively high property
Can, it is widely used in the more demanding field of read/write.Recently, the capacity of NAND quick-flash memory chip has reached 2GB, and
Size increases sharply.The solid state hard disc of NAND quick-flash memory chip has been developed based on, and has been used as in pocket computer
Storage device.Therefore, in recent years, NAND quick-flash memory is widely used as the storage device in embedded system, also serves as individual
Storage device in computer system.
For NAND quick-flash memory, in 32nm and following technology node in wordline (word line, abbreviation WL) shape
Silicide into such as NiSi is necessary.And the etch-back (etch back) of interlayer dielectric layer (ILD) is wordline silicification technics
A critical process before.In the etch-back of interlayer dielectric layer, meet that etching standard requirement is very important, such as
Require the damage of wordline upper plasma to reduce in etch-back process, while realize that required oxide depression (recess) etching is deep
Degree.
However, the etch back process of current interlayer dielectric layer cannot meet above-mentioned requirements well, such as when using company
When continuous high density plasma etch process performs etch-back, serious polysilicon can be caused to damage, and oxide fence
(fence) defect and very poor uniformity.And if performing the etch-back using remote plasma etch technique, although
These problems can be improved, but the side effect of limited deep-controlled ability can be run into.
It is, therefore, desirable to provide a kind of production method of new semiconductor devices, to solve the above problems at least in part.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention proposes a kind of production method of new semiconductor devices, can be real very well
The problems such as showing interlayer dielectric layer etch-back, while not producing polysilicon damage and limited etch depth control ability, and be etched back
Interlayer dielectric layer uniformity is fine after quarter.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of production method of semiconductor devices, it is wrapped
Include following step：Semiconductor substrate is provided, patterned top is formed on the semiconductor substrate and contains silicon structural layer and bag
Enclose the interlayer dielectric layer of the patterned top containing silicon structural layer；By high oxide to silicon selective etch technique to described
Interlayer dielectric layer performs the first etch-back, to remove a certain amount of interlayer dielectric layer, while at interlayer dielectric layer surface and top
Surface containing silicon structural layer forms polymer；Second eatch-back performs the interlayer dielectric layer by remote plasma etch technique
Carve, further to remove a certain amount of interlayer dielectric layer, so that etch-back depth meets sets requirement, it is patterned to expose
Upper area of the top containing silicon structural layer；Silication is formed in the upper area of the patterned top exposing containing silicon structural layer
Thing, wherein, the polymer thickness on top surface containing silicon structural layer is more than the thickness of the polymer of interlayer dielectric layer surface.
Further, the high oxide is lock-out pulse plasma etching process to silicon selective etch technique.
Further, the etching gas based on CxFy is used in lock-out pulse plasma etching process.
Further, the oxide is 3 to the selectivity of silicon：More than 1.
Further, remote plasma etch technique uses chemical downstream etch process or SiCoNi etch process.
Further, following step is further included：Etch residue is removed by wet processing or ashing method.
Further, the ashing method uses N2, O2 or H2 plasma.
Further, the patterned top is patterned word line polysilicon layer containing silicon structural layer.
Further, the patterned top is patterned silicon fin containing silicon structural layer.
The etch-back of interlayer dielectric layer is divided into two steps and carried out by the production method of semiconductor devices proposed by the present invention, and first
Step so etches silicon selective etch technique certain depth using high oxide, and can be situated between in etching process in interlayer
Electric layer surface and top surface containing silicon structural layer form polymer, and the polymer thickness on top surface containing silicon structural layer is big
In the thickness of the polymer of interlayer dielectric layer surface, such polymer can be protected containing silicon structural layer from damage；Second step is adopted
With remote plasma etch technique, certain depth can be further etched, and removes the oxidation of first step etch process formation
Thing fence defect and very poor homogeneity question.The production method of semiconductor devices proposed by the present invention, by adjusting first
Step etching technique and the second etch process can control etch depth well, make the etch-back depth of interlayer dielectric layer meet to want
Ask.
Another aspect of the invention provides a kind of semiconductor devices made of the above method, which includes：
Semiconductor substrate, containing silicon structural layer and surrounds the patterned top in the Semiconductor substrate formed with patterned top
Interlayer dielectric layer of the portion containing silicon structural layer, the height of the interlayer dielectric layer are less than the patterned top containing silicon structural layer
Highly, the patterned top is not formed in part with silicide containing silicon structural layer by what the interlayer dielectric layer surrounded.
Further, the patterned top is patterned word line polysilicon layer containing silicon structural layer.
Further, the patterned top is patterned silicon fin containing silicon structural layer.
Semiconductor devices proposed by the present invention has silicide of good performance.
Further aspect of the present invention provides a kind of electronic device, it include semiconductor devices as described above and with it is described partly
The electronic building brick that conductor device is connected.
Electronic device proposed by the present invention, due to above-mentioned semiconductor device, thus has the advantages that similar.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A~Fig. 1 C schematically show a kind of interlayer dielectric layer etch-back process schematic diagram of current NAND device；
Fig. 2 shows the step flow chart of the production method of semiconductor devices according to an embodiment of the present invention；
Fig. 3 A~Fig. 3 D show that the production method of semiconductor devices according to an embodiment of the present invention is implemented respectively successively
Step obtains the diagrammatic cross-section of semiconductor devices；
Fig. 4 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated phase from beginning to end
The identical element with reference numeral expression.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, component, area, floor and/or part, these elements, component, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, component, area, floor or part and another
Element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, component, area,
Floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to further include using and
The different orientation of device in operation.For example, if the device upset in attached drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
As it was previously stated, in the etch back process of current interlayer dielectric layer, it is impossible to meet etching standard requirement very well, into
And influence final device performance.Figure 1A~Fig. 1 C are combined first below to a kind of current NAND quick-flash memory interlayer dielectric layer
Eatch-back carving method illustrate, to more fully understand the present invention.
Figure 1A~Fig. 1 C schematically show a kind of interlayer dielectric layer etch-back process schematic diagram of current NAND device.Such as figure
Shown in 1A~Fig. 1 C, gate stack is formed on a semiconductor substrate 100 first, and surround the interlayer dielectric layer of gate stack
107, wherein, tunnel oxide 101 that gate stack includes sequentially forming from bottom to top, floating boom 102, dielectric layer 103 between grid,
Control gate 104, hard mask layer 105 and the clearance wall 106 positioned at gate stack sidewall；Then, as shown in Figure 1B, by continuous
High-density plasma etching perform interlayer dielectric layer 107 etch-back, to remove hard mask layer 105 and part interlayer dielectric
Layer 107 and portion gap wall 106, so that the top area of control gate 104 is exposed, so as at the top of control gate 104
Region forms sub-line silicide, but as shown in Figure 1B and as it was previously stated, this method can cause serious polysilicon to damage
(i.e. control gate damages), and oxide fence (fence, the clearance wall on top is not removed, and causes control room not expose)
Defect and very poor uniformity (107 uniformity of interlayer dielectric layer is deteriorated after etch-back, and thickness is inconsistent everywhere, not shown).
Or as shown in Figure 1 C, the etch-back of interlayer dielectric layer 107 is performed using remote plasma etch technique, although can improve
These problems, but the side effect of limited deep-controlled ability can be run into, this is because being lost using using remote plasma
The etch-back that carving technology performs interlayer dielectric layer 107 (oxide) can run into etching saturation problem, when etching into certain depth,
Even if etch depth can not be increased by being further added by etching period, thus be not easy to meet that control gate exposes the control of depth and wants
Ask.
To solve the above problems, the present invention proposes a kind of production method of semiconductor devices, good layer is used for realization
Between dielectric layer reetching, as shown in Fig. 2, the production method includes：Step 201, there is provided Semiconductor substrate, serves as a contrast in the semiconductor
Patterned top is formed on bottom containing silicon structural layer and surrounds the interlayer dielectric layer of the patterned top containing silicon structural layer；
Step 202, the first etch-back is performed to the interlayer dielectric layer to silicon selective etch technique by high oxide, to remove one
Quantitative interlayer dielectric layer, while surface containing silicon structural layer forms polymer in interlayer dielectric layer surface and top；Step 203,
Second etch-back is performed to the interlayer dielectric layer by remote plasma etch technique, further to remove a certain amount of layer
Between dielectric layer so that etch-back depth meets sets requirement, to expose upper area of the patterned top containing silicon structural layer；
Step 204, at the patterned top, the upper area exposed containing silicon structural layer forms silicide, wherein, the top
The polymer thickness on the surface containing silicon structural layer is more than the thickness of the polymer of interlayer dielectric layer surface.
The production method of semiconductor devices proposed by the present invention, by the way that the etch-back of interlayer dielectric layer is divided into two steppings
OK, the first step so etches silicon selective etch technique certain depth using high oxide, and meeting exists in etching process
In interlayer dielectric layer surface and top, surface containing silicon structural layer forms polymer, and the polymerization on top surface containing silicon structural layer
Thing thickness is more than the thickness of the polymer of interlayer dielectric layer surface, and such polymer can be protected containing silicon structural layer from damage；
Second step uses remote plasma etch technique, can further etch certain depth, and removes first step etch process shape
Into oxide fence defect and very poor homogeneity question.The production method of semiconductor devices proposed by the present invention, passes through
Etch depth can be controlled well by adjusting first step etch process and the second etch process, make the etch-back of interlayer dielectric layer deep
Degree is met the requirements.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
The production method of the semiconductor devices of an embodiment of the present invention is done below with reference to Fig. 3 A~Fig. 3 D and is retouched in detail
State.In the present embodiment, the semiconductor device of the present invention is illustrated exemplified by carrying out etch-back to the interlayer dielectric layer of NAND device
The production method of part.
First, as shown in Figure 3A, there is provided Semiconductor substrate 300, forms gate stack in Semiconductor substrate 300, and
Surround the interlayer dielectric layer 307 of gate stack.
Wherein, Semiconductor substrate 300 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, further include sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, Semiconductor substrate 300
Constituent material select monocrystalline silicon.
Tunnel oxide 301 that gate stack includes sequentially forming from bottom to top, floating boom 302, dielectric layer 303 between grid,
Control gate 304, hard mask layer 305 and the clearance wall 306 positioned at gate stack sidewall.Gate stack is using commonly used in the art
Structure and forming method make, such as tunnel oxide 301 is illustratively silicon oxide layer, it can pass through such as thermal oxide
The methods of method, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (atomic layer deposition), is formed.302 example of floating boom
Property use the semi-conducting material such as polysilicon, and by selecting molecular beam epitaxy (MBE), metal organic chemical vapor deposition
(MOCV), one kind in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG)
Formed.Dielectric layer 303 is such as the dielectric materials such as oxide, nitride between grid, it is preferable that in the present embodiment, between grid
Dielectric layer 303 so both has good interface performance using ONO structure (that is, oxidenitride oxide), it may have
Good dielectric properties and suitable thickness.Control gate 304 exemplarily uses the semi-conducting material such as polysilicon, and passes through
Select molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser
A kind of formation in ablation deposition (LAD) and selective epitaxy growth (SEG).
It can pass through thermal oxidation method, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (atomic layer depositions
Product) the methods of formed.
Clearance wall 306 is made of common spacer material and forming method.Exemplarily, gap in the present embodiment
Wall 306 uses oxide.
Interlayer dielectric layer 307 uses common dielectric material, such as USG, PSG, BPSG etc., and passes through FCVD (mobility
Chemical vapor deposition), spin-coating method, the technique such as HARP (high-aspect-ratio processing procedure) formed.
Then, as shown in Figure 3B, silicon selective etch technique performs the interlayer dielectric layer 307 by high oxide
First etch-back, to remove a certain amount of interlayer dielectric layer, while in 304 surface shape of 307 surface of interlayer dielectric layer and control gate
Into polymer 308.
The high oxide can realize oxide to silicon high selectivity silicon selective etch technique to be various
Etch process, so-called high oxide are selectively 3 to silicon：More than 1, it is, for example, 40.And silicon is being selected using high oxide
, can be at 307 surface of interlayer dielectric layer and top during selecting property etch process performs the first etch-back to interlayer dielectric layer
The deposition by-products of surface containing silicon structural layer, i.e. polymer 308.Polymer 308 is since the etch process oxide is to silicon selectivity
Height, and it is thicker in the polymer that 304 top surface of control gate is formed, it is relatively thin in the polymer that 307 surface of interlayer dielectric layer is formed.
Exemplarily, in the present embodiment, which is performed using lock-out pulse plasma etching process, passed through
Lock-out pulse plasma etching process can realize high selectivity of the oxide to silicon, and can induce and be pushed up in control gate 304
Surface is formed uniformly compared with thick polymer 308A as protective layer, and forms relatively thin polymer on 307 surface of interlayer dielectric layer
308B is in favor of the progress of subsequent etch.In this step by the erosion for i.e. adjustable first etch-back of thickness for controlling polymer
Carve depth.
Exemplarily, in the present embodiment, using the gas based on CxFy as etching gas, such as the one kind such as C3F4
Or multiple gases.
Then, as shown in Figure 3 C, the interlayer dielectric layer 307 is performed second time by remote plasma etch technique
Etching, further to remove a certain amount of interlayer dielectric layer 307, so that etch-back depth meets sets requirement, to expose figure
The upper area of the control gate 304 of shape.
After the first etch-back, interlayer dielectric layer has completed the etching of certain depth, then, by remotely wait from
Daughter etch process performs the second etch-back, further to remove a certain amount of interlayer dielectric layer 307, so that etch-back depth
Meet sets requirement, to expose the upper area of patterned control gate 304.Since remote plasma etch process will not damage
Polysilicon, and isotropism, since the oxide fence defect and interlayer of the formation of the first etch process can be removed well
The uneven defect of dielectric layer.
Exemplarily, in the present embodiment, remote plasma etch technique uses chemical downstream etch (chemistry
Downtown etch), SiCoNi etching or other isotropic etchings.Chemical downstream etch is common remote plasma
Body etch process, its principle are to form plasma in upstream, are then introduced into downstream etch chamber using plasma with being eclipsed
The reaction for carving layer is etched, thus can realize isotropism and because not have ion bombardment without damaging polysilicon.
SiCoNi etch process is common cleaning, in the present embodiment, is completed using SiCoNi etch process
Second etch-back.The basic principle of SiCoNi etch process is the long-range plasma etch of NF3/NH3 and in-situ annealing, this two step all exists
Completed in same cavity.In etching process, wafer is placed on temperature and is strictly controlled on 35 DEG C of base, low-power
NF3 and NH3 are transformed into ammonium fluoride (NH4F) and bifluoride ammonia (formula 1) by plasma-based.Fluoride crystal column surface condense, and preferentially with
Oxide reacts, and forms hexafluoro silicon ammonia ((NH4) 2SiF6) (formula 2).This silicate can rise in more than 70 DEG C environment
China.During in-situ annealing, wafer is moved to takes heat to wafer close to the position of heating element, the hydrogen of flowing
On, wafer is heated to more than 100 DEG C in a short period of time, and it is gaseous SiF4, NH3 and HF to make hexafluoro silicon ammonolysis craft
(equation 3), and be pumped away.
Etching agent generates：NF3+NH3→NH4F+NH4F.HF (1)
Etching process：NH4F or NH4F.HF+SiO2→(NH4)2SiF6(solid)+H2O (2)
Sublimation process：(NH4)2SiF6(solid)→SiF4(g)+NH3(g)+HF(g) (3)
The high selectivity of oxide and silicon can be realized using SiCoNi etch process, so as to etch interlayer dielectric layer very well
307 and clearance wall 306, avoid the occurrence of lack of homogeneity and oxide fence defect.
Finally, as shown in Figure 3D, etch residue is removed, and silicide is formed in the region that control gate 304 leaks out.
Specifically, etch residue is removed by wet processing (using suitable solvent) or ashing method (Ash) first,
Such as such as etch byproducts of polymer 308.
Exemplarily, in the present embodiment, etch residue is removed by ashing method.Wherein, using N2, O2 or Ar etc.
Gas ions (that is, the plasma formed by gas N2, O2 or Ar) perform the cineration technics.
Then, cross silicification technics and silicide 309 is formed in the part that control gate 304 exposes, silicification technics is this area
Details are not described herein for conventional process.Exemplarily, in the present embodiment, silicide 309 is NISi silicides.
So far, the processing step implemented according to the method for the embodiment of the present invention is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include other needs afterwards
The step of, further include the step of forming source/drain after or before gate stack is formed.
The production method for the semiconductor devices that the present embodiment proposes, is divided into two steps by the etch-back of interlayer dielectric layer and carries out,
The first step so etches silicon selective etch technique certain depth using high oxide, and can be in layer in etching process
Between dielectric layer surface and control gate top surface form polymer, and the polymer thickness of control gate top surface is more than interlayer dielectric layer
The thickness of the polymer on surface, such polymer can protect control gate from damage；Second step is lost using remote plasma
Carving technology, can further etch certain depth, and remove the oxide fence defect and very of first step etch process formation
The homogeneity question of difference.The production method for the semiconductor devices that the present embodiment proposes, by adjusting first step etch process and the
Two etch process can control etch depth well, meet the requirements the etch-back depth of interlayer dielectric layer.
It is understood that although the present embodiment illustrates the half of the present invention with the interlayer dielectric layer etch-back of NAND device
The production method of conductor device, but the production method not limited to this of the semiconductor devices of the present invention, such as fin structure
Semiconductor devices interlayer dielectric layer etch-back can also use semiconductor devices proposed by the present invention production method.
Embodiment two
The present invention also provides a kind of semiconductor devices made of the above method, as shown in Figure 3D, the semiconductor devices
Including：Semiconductor substrate 300, formed with gate stack and surrounds the layer of the gate stack in the Semiconductor substrate 300
Between dielectric layer 307, the height of the interlayer dielectric layer 307 is less than the height of the gate stack, under the gate stack includes
Dielectric layer 303 between the tunnel oxide 301 that is sequentially formed on and, floating boom 302, grid, control gate 304, hard mask layer 305 and
Positioned at the clearance wall 306 of gate stack sidewall, the control gate 304 is not formed by the part that the interlayer dielectric layer 307 surrounds
There is silicide 309.
The semiconductor devices of the present embodiment can realize good son formed with satisfactory control gate silicide
Linear energy.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic device, including semiconductor devices and with the semiconductor device
The electronic building brick that part is connected.Wherein, which includes：Semiconductor substrate, formed with figure in the Semiconductor substrate
The top of change is containing silicon structural layer and surrounds the interlayer dielectric layer of the patterned top containing silicon structural layer, the interlayer dielectric
The height of layer is less than the height of the patterned top containing silicon structural layer, and the patterned top is containing silicon structural layer not by institute
That states interlayer dielectric layer encirclement is formed in part with silicide.
Wherein, Semiconductor substrate can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, further include sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in Semiconductor substrate
And/or PMOS etc..Equally, in Semiconductor substrate can also formed with conductive member, conductive member can be transistor grid,
Source electrode or drain electrode or the metal interconnection structure that is electrically connected with transistor, etc..In addition, may be used also in the semiconductor substrate
To isolate (STI) structure or selective oxidation silicon (LOCOS) isolation junction formed with isolation structure, the isolation structure for shallow trench
Structure.As an example, in the present embodiment, the constituent material of Semiconductor substrate selects monocrystalline silicon.
Exemplarily, the patterned top is patterned word line polysilicon layer containing silicon structural layer.
Exemplarily, the patterned top is patterned silicon fin containing silicon structural layer.
Wherein, the electronic building brick, can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment, can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products including the semiconductor devices.
Wherein, Fig. 4 shows the example of mobile phone.The outside of mobile phone 400 is provided with the display portion being included in shell 401
402nd, operation button 403, external connection port 404, raise 405, microphone 406 etc..
The electronic device of the embodiment of the present invention, since the semiconductor devices included has satisfactory silicide, because
And there is better performance.Therefore the electronic device equally has the advantages that similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of production method of semiconductor devices, it is characterised in that comprise the following steps：
Semiconductor substrate is provided, patterned top is formed on the semiconductor substrate containing silicon structural layer and surrounds the figure
Interlayer dielectric layer of the top of shape containing silicon structural layer；
First etch-back is performed to the interlayer dielectric layer to silicon selective etch technique by high oxide, it is a certain amount of to remove
Interlayer dielectric layer, while in interlayer dielectric layer surface and top surface containing silicon structural layer formed polymer；
Second etch-back is performed to the interlayer dielectric layer by remote plasma etch technique, it is a certain amount of further to remove
Interlayer dielectric layer so that etch-back depth meets sets requirement, to expose top of the patterned top containing silicon structural layer
Region；
Silicide is formed in the upper area of the patterned top exposing containing silicon structural layer,
Wherein, the polymer thickness on top surface containing silicon structural layer is more than the thickness of the polymer of interlayer dielectric layer surface.
2. the production method of semiconductor devices according to claim 1, it is characterised in that the high oxide selects silicon
Property etch process is lock-out pulse plasma etching process.
3. the production method of semiconductor devices according to claim 2, it is characterised in that in lock-out pulse plasma etching
The etching gas based on CxFy is used in technique.
4. the production method of semiconductor devices according to claim 2, it is characterised in that selection of the oxide to silicon
Property is 3：More than 1.
5. the production method of semiconductor devices according to claim 2, it is characterised in that remote plasma etch technique
Using chemical downstream etch process or SiCoNi etch process.
6. the production method of semiconductor devices according to claim 1, it is characterised in that further include following step：
Etch residue is removed by wet processing or ashing method.
7. the production method of semiconductor devices according to claim 6, it is characterised in that the ashing method using N2,
O2 or H2 plasmas.
8. the production method of the semiconductor devices described in any one in claim 1-7, it is characterised in that the figure
The top of shape is patterned word line polysilicon layer containing silicon structural layer.
9. the production method of the semiconductor devices described in any one in claim 1-7, it is characterised in that the figure
The top of shape is patterned silicon fin containing silicon structural layer.
10. the semiconductor devices that a kind of production method using as described in any one in claim 1-9 makes, its feature exist
In, including：Semiconductor substrate, containing silicon structural layer and surrounds the figure in the Semiconductor substrate formed with patterned top
Interlayer dielectric layer of the top of shape containing silicon structural layer, the height of the interlayer dielectric layer are siliceous less than the patterned top
The height of structure sheaf, the patterned top are not formed in part with silication containing silicon structural layer by what the interlayer dielectric layer surrounded
Thing.
11. semiconductor devices according to claim 10, it is characterised in that the patterned top is containing silicon structural layer
Patterned word line polysilicon layer.
12. the production method of semiconductor devices according to claim 10, it is characterised in that the patterned top contains
Silicon structural layer is patterned silicon fin.
13. a kind of electronic device, it is characterised in that including the semiconductor device as described in any one in claim 10-12
Part and the electronic building brick being connected with the semiconductor devices.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194284B1 (en) * | 1999-08-30 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Method for forming residue free etched silicon layer |
| US20110195578A1 (en) * | 2010-02-10 | 2011-08-11 | Spansion Llc | Planar cell on cut using in-situ polymer deposition and etch |
| CN105390389A (en) * | 2014-08-29 | 2016-03-09 | 朗姆研究公司 | Contact clean in high-aspect ratio structures |
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2016
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194284B1 (en) * | 1999-08-30 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Method for forming residue free etched silicon layer |
| US20110195578A1 (en) * | 2010-02-10 | 2011-08-11 | Spansion Llc | Planar cell on cut using in-situ polymer deposition and etch |
| CN105390389A (en) * | 2014-08-29 | 2016-03-09 | 朗姆研究公司 | Contact clean in high-aspect ratio structures |
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