CN107978562A - A kind of manufacture method of semiconductor devices - Google Patents

A kind of manufacture method of semiconductor devices Download PDF

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Publication number
CN107978562A
CN107978562A CN201610937649.5A CN201610937649A CN107978562A CN 107978562 A CN107978562 A CN 107978562A CN 201610937649 A CN201610937649 A CN 201610937649A CN 107978562 A CN107978562 A CN 107978562A
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CN
China
Prior art keywords
mandrel
material layer
clearance wall
layer
manufacture method
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CN201610937649.5A
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Chinese (zh)
Inventor
王彦
张城龙
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201610937649.5A priority Critical patent/CN107978562A/en
Publication of CN107978562A publication Critical patent/CN107978562A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology

Abstract

The present invention provides a kind of manufacture method of semiconductor devices, is related to technical field of semiconductors.This method includes:Semiconductor substrate is provided, on the semiconductor substrate formed with target material layer, formed with several spaced first mandrels in the target material layer;The first clearance wall is formed on the side wall of first mandrel, and adjacent first clearance wall is isolated by the first opening;The second mandrel is filled in the described first opening;The first corona treatment is carried out, to form the first mandrel material layer being modified at the top of first mandrel and second mandrel;Remove the described first mandrel material layer being modified and first clearance wall.The method of the present invention, without using complicated material, cost is low, and process is simple, and the regular shape of the figure formed, and the transfer precision of figure is high, and then improves the performance and stability of device.

Description

A kind of manufacture method of semiconductor devices
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor devices.
Background technology
With the increasingly increase of the semiconductor storage demand to high power capacity, the integration density of semiconductor storage by To the concern of people, in order to increase the integration density of semiconductor storage, many different methods are employed in the prior art, Double patterning technology (Double-Patterning, DP) is just as a kind of solution route in the semiconductor devices less than 32nm nodes Widely received and applied in preparation process.
Double patterning technology (Double-Patterning, DP) is overcome by pitch fragment (pitch fragmentation) K1 limitations, so as to be widely used in the preparation of semiconductor devices.At present in double patterning technology (Double- Patterning, DP) have in technology self-aligned double patterning case (Self-aligned double patterning, SADP), photoetching- Etching-photoetching-etching (Litho-Etch-Litho-Etch, LELE) and freeze coating etching (Litho-Freeze- Litho, LFL).
Due to being limited be subject to photoetching technique, it is necessary to use self aligned four figures (Self aligned Quadruple patterning, abbreviation SAQP) photoetching technique prepares the device of 10nm nodes.Four times traditional figure photoetching Technology must be introduced into complicated film layer lamination to realize the transfer of pattern, it on the mandrel positioned at upper strata by forming gap Wall, the profile of the mandrel (mandrel) positioned at lower floor is defined with the clearance wall, and needs to ensure that what is formed is located in this process The mandrel of lower floor is square pattern (square pattern).It can be seen from the above that traditional handicraft is repeatedly heavy there are process complexity, needs The surface roughness for the clearance wall that integrated membrane layer, process costs are high, are formed is poor, and pattern transfer is of poor quality, robustness to device is made Into the problems such as negative effect.
Therefore, it is necessary to propose a kind of manufacture method of semiconductor devices, to improve SAQP photoetching techniques, above-mentioned skill is solved Art problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, a kind of manufacture method of semiconductor devices is provided in the embodiment of the present invention one, including:
Semiconductor substrate is provided, on the semiconductor substrate formed with target material layer, shape in the target material layer Into there is several spaced first mandrels;
The first clearance wall is formed on the side wall of first mandrel, and adjacent described first is isolated by the first opening Clearance wall;
The second mandrel is filled in the described first opening;
The first corona treatment is carried out, is modified with forming first at the top of first mandrel and second mandrel Mandrel material layer;
Remove the described first mandrel material layer being modified and first clearance wall.
Further, after the step of removing the described first mandrel material layer being modified and first clearance wall, also Comprise the following steps:
The second clearance wall is formed on the side wall of remaining first mandrel and second mandrel, and is opened by second Mouth isolates adjacent second clearance wall;
The 3rd mandrel is filled in the described second opening;
The second corona treatment is carried out, with the top of first mandrel, second mandrel and the 3rd mandrel Portion forms the second mandrel material layer being modified;
Remove the described second mandrel material layer being modified and second clearance wall;
Using remaining first mandrel, second mandrel and the 3rd mandrel as mask, the target material is etched The bed of material.
Further, the method for forming first clearance wall comprises the following steps:
Conformal deposited the first spacer material layer, to cover first mandrel and the part semiconductor substrate surface;
Etch-back is removed between described first on the first mandrel top surface and on the semiconductor substrate surface of part The gap wall material bed of material, to form first clearance wall and first opening.
Further, after first clearance wall is formed, formed before second mandrel, further included using ion beam The step of handling the surface that first clearance wall exposes, and/or, after second clearance wall is formed, form described the Before three mandrels, the step of further including the surface exposed using the second clearance wall described in Ion Beam Treatment.
Further, plasma includes H used in first corona treatment2And/or the plasma of He, institute Stating plasma used in the second corona treatment includes H2And/or the plasma of He.
Further, the method for forming second clearance wall comprises the following steps:
Conformal deposited the second spacer material layer, to cover first mandrel, second mandrel and part described half Conductor substrate surface;
Etch-back removes on first mandrel and the second mandrel top surface and the part semiconductor substrate surface On the second spacer material layer, with formed second clearance wall and it is described second opening.
Further, the material of first clearance wall includes non-crystalline silicon, and the material of second clearance wall includes non-crystalline silicon.
Further, the material of first mandrel includes silicon nitride, and the material of second mandrel includes silicon nitride, described The material of 3rd mandrel includes silicon nitride.
Further, the described first mandrel material layer being modified and the described second core being modified are removed using diluted hydrofluoric acid The axial wood bed of material.
Further, it is also formed with stacking gradually from bottom to top between first mandrel and the target material layer hard Mask layer and etching stopping layer.
In conclusion the manufacturing method of the present invention and is changed by directly forming mandrel in the opening by plasma treatment Property mandrel at the top of have irregular pattern part, to form modified mandrel material layer at the top of mandrel, the mandrel of the modification The mandrel that material layer is not modified relatively has high etching selectivity, and then realizes and remove modified mandrel material layer, obtains Square mandrel pattern of the shape for rule is obtained, and then realizes the progressively transfer of figure, mesh is finally formed in target material layer To mark on a map case, method of the invention is without using complicated material, and cost is low, and process is simple, and the regular shape of the figure formed, The transfer precision of figure is high, and then improves the performance and stability of device.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
The correlation step that Figure 1A-Fig. 1 E prepare device by self aligned four figures (SAQP) technology of existing one kind obtains The structure diagram obtained;
Fig. 2A-Fig. 2 L are obtained by the correlation step of the manufacture method of the semiconductor devices according to one embodiment of the present invention The structure diagram of the device obtained;
Fig. 3 is the process flow chart according to the manufacture method of the semiconductor devices of one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly It is connected to " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although it can make Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/ Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion Part, area, floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to further include to make With the different orientation with the device in operation.For example, if the device upset in attached drawing, then, is described as " under other elements Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation, The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore, The embodiment of the present invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape Shape deviation.For example, it is shown as that the injection region of rectangle usually has circle at its edge or bending features and/or implantation concentration ladder Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic , their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can be with With other embodiment.
The correlation step that Figure 1A-Fig. 1 E prepare device by self aligned four figures (SAQP) technology of existing one kind obtains The structure diagram obtained, in the following, being briefly described with reference to figure 1A- Fig. 1 E to a kind of existing correlation step of SAQP technologies.
First, as shown in Figure 1A, there is provided Semiconductor substrate 100, on the semiconductor substrate formed with target material layer 101, the first hard mask layer 102, the first etching stopping layer 103, the first mandrel material are sequentially formed in the target material layer 101 Bed of material 104a, the second hard mask layer 105, the second etching stopping layer 106 and the second mandrel material layer, to the second mandrel material The bed of material is patterned, to form the second mandrel 107 isolated by opening.
Then, as shown in Figure 1B, deposition forms the first spacer material layer 108, to cover second mandrel 107 and institute State 100 surface of Semiconductor substrate, and etch remove the first spacer material layer 108 be located on 107 top surface of the second mandrel with And the part on 100 surface of Semiconductor substrate of part, to form the first gap on the side wall of the second mandrel 107 Wall, and remove second mandrel 107.
Then, as shown in Figure 1 C, the second etching stopping layer 106, second is etched successively using first clearance wall as mask Hard mask layer 105 and the first mandrel material layer 104a, stop in first etching stopping layer 103, so as to form figure First mandrel 104 of case, then removes the second etching stopping layer 106 and the second hard mask layer on 104 top surface of the first mandrel 105。
Then, as shown in figure iD, deposition forms the second spacer material layer 109, to cover first mandrel 104 and institute State 100 surface of Semiconductor substrate, and etch remove the second spacer material layer 109 be located on 104 top surface of the first mandrel with And the part on 100 surface of Semiconductor substrate of part, to form the second gap on the side wall of the first mandrel 104 Wall, then removes first mandrel 104.
Then, as referring to figure 1E, using second clearance wall as mask, etch successively first etching stopping layer 103, First hard mask layer 102 and the target material layer 101, stop on the surface of the Semiconductor substrate 100, then remove One etching stopping layer 103 and the first hard mask layer 102, to ultimately form patterned target material layer 101.Existing SAQP skills Art usually requires to make the lamination for including at least two layers of mandrel material layer, etching stopping layer and hard mask layer, those film layers For complex manufacturing process, it is necessary to Multiple depositions, process costs are high, and in pattern transfer, it is also necessary to by spacer material twice The process of layer deposition, by being etched to form the second clearance wall to the second spacer material layer, position is defined with the second clearance wall In the profile of the first mandrel 104 (mandrel) of lower floor, and the first mandrel 104 for needing to ensure to be formed in this process is side Shape pattern (square pattern), the process complexity are not easily controlled, but the deposition of the clearance wall and etched at present Journey makes the reduction of line width roughness (line width roughness, LWR) performance, and then influences pattern transfer quality, to device Robustness adversely affect.
Embodiment one
In order to solve foregoing technical problem, the present invention provides a kind of manufacture method of semiconductor devices, such as Fig. 3 institutes Show, it is mainly included the following steps that:
Step S301, there is provided Semiconductor substrate, on the semiconductor substrate formed with target material layer, the target material Formed with several spaced first mandrels on the bed of material;
Step S302, forms the first clearance wall on the side wall of first mandrel, and adjacent by the first opening isolation First clearance wall;
Step S303, the second mandrel is filled in the described first opening;
Step S304, carries out the first corona treatment, with the top shape of first mandrel and second mandrel The mandrel material layer being modified into first;
Step S305, removes the described first mandrel material layer being modified and first clearance wall;
Step S306, the second clearance wall is formed on the side wall of remaining first mandrel and second mandrel, and Adjacent second clearance wall is isolated by the second opening;
Step S307, the 3rd mandrel is filled in the described second opening;
Step S308, carries out the second corona treatment, with first mandrel, second mandrel and the described 3rd The second mandrel material layer being modified is formed on the top of mandrel;
Step S309, removes the described second mandrel material layer being modified and second clearance wall;
Step S310, using remaining first mandrel, the second mandrel and the 3rd mandrel as mask, etches the target material Layer.
In conclusion the manufacturing method of the present invention, by directly forming mandrel in the opening, and is changed by plasma treatment Property mandrel at the top of have irregular pattern part, to form modified mandrel material layer at the top of mandrel, the mandrel of the modification The mandrel that material layer is not modified relatively has high etching selectivity, and then realizes and remove modified mandrel material layer, obtains Square mandrel pattern of the shape for rule is obtained, and then realizes the progressively transfer of figure, mesh is finally formed in target material layer Mark on a map case, method of the invention, without using complicated material, cost is low, and process is simple, and the shape rule of the figure formed Then, the transfer precision of figure is high, and improves the line width roughness of figure by the method for Ion Beam Treatment, and then improves device The performance and robustness of part.
In the following, the manufacture method of the semiconductor devices of the present invention is described in detail with reference to figure 2A- Fig. 2 L, wherein, Fig. 2A- The knot for the device that Fig. 2 L are obtained for the correlation step of the manufacture method of the semiconductor devices according to one embodiment of the present invention Structure schematic diagram.
First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, formed with target material in the Semiconductor substrate 200 Layer 201, formed with several spaced first mandrels 204 in the target material layer 201.
The Semiconductor substrate 200 can be at least one of following material being previously mentioned:Silicon, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator (SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the constituent material of Semiconductor substrate 200 Select monocrystalline silicon.
The target material layer 201 can be formed in interconnection wiring layer on substrate, interlayer dielectric layer, gate material layers or Person's hard mask layer.The constituent material of the interconnection wiring layer is selected from least one of tungsten, tungsten silicide, aluminium, titanium and titanium nitride.Institute Low-k (k) material or ultralow-k material film can be selected from by stating the constituent material of interlayer dielectric layer.The structure of the gate material layers Into the one kind of material in polysilicon and aluminium.The constituent material of the hard mask layer is selected from oxide, undoped silicon glass, glass At least one of silicon on glass, SiON, SiN, SiBN, BN and high-g value.It should be noted that target material layer be it is optional and Optionally, can be accepted or rejected according to actual conditions.
In one example, the method for forming first mandrel 204 comprises the following steps A1 to A2:
First, step A1 is carried out, hard mask layer 202, etching stopping layer are sequentially formed in the target material layer 201 203 and the first mandrel material layer.
The material of hard mask layer 202 can be any commonly employed material as hard mask in this area, include but not limited to SiO2, SiCN, SiN, SiC, SiOF, SiON, SiBN, BN etc., hard mask layer 202 can also be advanced patterned film (APF, Advanced Patterning Film) material composition.Wherein, APF materials can be from the application material of the holy santa clara of California Company obtains, such as Advanced Patterning FilmTM.This APF materials'uses bilayer patterned film is laminated, will Peelable CVD carbon hardmasks technology is combined with dielectric anti-reflective coating (DRAC) technology, to realize the contact of large ratio of height to width Etching.The further data of APF materials and it be patterned can be found in application to make it have the process of pattern Number be 200810132400.2 Chinese patent application, this is had a detailed description in the publication.Chemical vapor deposition can be used The methods of product, physical vapour deposition (PVD), atomic layer deposition, forms hard mask layer 202.
Etching stopping layer 203 may include a dielectric material, such as material, nitrogenous material, carbonaceous material or homologue, For example, SiCN, SiN, SiC, SiOF, SiON etc..
First mandrel material layer can be any suitable material for being beneficial to shaping and removing, in the present embodiment, the first core The material of the axial wood bed of material includes nitride, especially silicon nitride (SiN) but is not limited to the material.Wherein, the first mandrel material The bed of material selects the methods of chemical vapor deposition or atomic layer deposition (ALD) to be formed.The thickness of first mandrel material layer can basis It can be any appropriate thickness, be not specifically limited herein.
Then, step A2 is carried out, by photoetching process, the first mandrel material layer is patterned, to form described first Mandrel 204.
Specifically, can be by the spin coating photoresist layer in the first mandrel material layer, then development is exposed to photoresist layer, To form patterned photoresist layer, then using photoresist layer as the first mandrel material layer described in mask etch, stop at the erosion Carve in stop-layer 203, to form several first mandrels 204.Finally remove photoresist layer.
Alternatively, first mandrel 204 can be of the same size.
Then, as shown in Figure 2 B, the first spacer material of conformal deposited layer 205a, to cover 204 He of the first mandrel Part 200 surface of Semiconductor substrate.
Exemplarily, when formed with etching stopping layer 203, the first spacer material layer 205a covers the etching The surface that stop-layer 203 exposes.
The material of the first spacer material layer 205a can select non-crystalline silicon (a-Si) but be not limited in this step The material.Wherein, the first spacer material layer 205a can use low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid heat chemical One kind in vapour deposition (RTCVD) and molecular beam epitaxy (MBE).
Alternatively, the thickness of the first spacer material layer 205a is not limited to a certain number range.
Then, as shown in Figure 2 C, etch-back is removed on 204 top surface of the first mandrel and the part Semiconductor substrate The first spacer material layer on 200 surfaces, to form the opening of the first clearance wall 205 and first 2061, wherein, Form the first clearance wall 205 on the side wall of first mandrel 204, and by 2061 isolation of the first opening it is adjacent described the One clearance wall 205.
First spacer material layer described in selecting dry etching in this step, in this step can in the dry etching To select CF4、CHF3In addition N is added2、CO2、O2In it is a kind of as etching atmosphere, wherein gas flow is CF4 10- 200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-150mTorr, during etching Between be 5-120s.
The size of first opening 2061 can be by the thickness of the first spacer material layer deposited in abovementioned steps Reasonably adjusted, its size corresponds to the size of the pattern of predetermined transfer, for example, the size of first opening 2061 can be with The size of first mandrel is identical, namely has identical width.
The first opening 2061 is formd while etching forms the first clearance wall 205, and the etch stop is in described In etching stopping layer 203.
In one example, after first clearance wall 205 is formed, further include what the first clearance wall 205 was exposed Surface carries out the step of Ion Beam Treatment (ion beam treatment), to improve the roughness of the first gap wall surface, into And improve the line width roughness of the pattern of predetermined transfer, there is provided the precision of pattern transfer.
Ion used in Ion Beam Treatment may include the ion that intert-gas atoms produce, and intert-gas atoms are, for example, Ar or Xe etc..The surface that Ion Beam Treatment exposes the first clearance wall is acted on bombardment, can make the surface of the first clearance wall It is more smooth, reduce its surface roughness.
Then, as shown in Figure 2 D, the second mandrel 206 is filled in the described first opening.
In one example, forming the method for second mandrel includes:Second mandrel material can be formed by deposition process The bed of material, full first opening of filling, and the top surface of first clearance wall is covered, then chemistry is carried out to the second mandrel material layer The planarisation steps such as mechanical lapping, stop on the top surface of first clearance wall 205, to form second mandrel 206.
Wherein, the shape at the top of first opening 2061 may be irregular shape, such as section is inverted trapezoidal Shape or other shape, therefore, the cross sectional shape at the top of the second mandrel 206 formed in this step accordingly is similar For inverted trapezoidal.
Then, as shown in Figure 2 E, the first corona treatment is carried out, with the first mandrel 204 and second mandrel 206 Top formed first be modified mandrel material layer 207.
Wherein, mandrel material of first corona treatment to be modified at the top of the first mandrel and second mandrel, and then Form the first mandrel material layer 207 being modified.
Exemplarily, plasma includes H used in first corona treatment2And/or the plasma of He, Can also be other any plasmas that can make the first mandrel and the generation modification of the second mandrel material.
Further, the H2Or the production method of He plasmas can select method commonly used in the art, such as at this H is selected in one embodiment of invention2Or then He gases carry out plasma as working gas in the plasma source Change, select H2Or the pressure of the gas ions processing is 1-7torr during chamber described in He corona treatments, is chosen as 2- 5torr, the H2Or the flow velocity of He is 300-4000sccm, 500-800sccm is chosen as, the power is 100-2000w, example HFRF power is arranged to more than 100w as will be described, produces plasma to handle the chamber.
In this step processing time for 0.5-5 it is small when, be chosen as 0.5-1 it is small when, those skilled in the art can basis Actual needs makes choice, wherein, the part that the top of the second mandrel 204 has irregular shape is all changed as long as can control Property.
Then, as shown in Figure 2 F, the described first mandrel material layer 207 being modified and first clearance wall 205 are removed.
Using diluted hydrofluoric acid DHF (wherein comprising HF and H in the step2O) selective etch removes described first Modified mandrel material layer 207, wherein, the concentration of the DHF does not limit strictly, in the present invention HF:H2The volume ratio of O It may range from 1:1000~1:2.
First mandrel, 204 and second mandrel 206 that the described first mandrel material layer 207 being modified is not modified relatively With high etching selectivity, for example, etching selectivity can be 1:4~1:In the range of 100, therefore, described the is removed in etching During modified mandrel material layer 207, overetch will not be caused to the first mandrel 204 and the second mandrel 206, made at least most of The first mandrel 204 and the second mandrel 206 remain, and due in abovementioned steps, the top of the second mandrel 206 is had not The part of regular shape is all modified as the mandrel material layer 207 of the first modification, and in this step, etching removes the second mandrel top The mandrel material layer 207 that the first of portion is modified, then remaining second mandrel 206 then have well-regulated square contour, it is and remaining First mandrel 204 and the second mandrel 206 then have identical height.
And then there is high etching selectivity using the first clearance wall 205 opposite first mandrel 204 and the second mandrel 206 Wet etch process remove first clearance wall 205.
Specifically, the etchant being adapted to according to the material selection of the first clearance wall 205, for example, the material of the first clearance wall 205 Expect for non-crystalline silicon (a-Si) when, using inorganic base or organic alkali solution as etchant, inorganic base can be KOH, NaOH, NH4OH etc., organic base can be tetramethylammonium hydroxide (TMAH) solution or EDP (including ethylenediamine, hydroquinone and water) etc., In the present embodiment, the first clearance wall 205 is removed preferably using tetramethylammonium hydroxide (TMAH) solution.
Then, as shown in Figure 2 G, the second spacer material of conformal deposited layer 208a, to cover first mandrel 204, institute State the second mandrel 206 and part 200 surface of Semiconductor substrate.
Wherein, the second spacer material layer 208a can use the material identical with the first foregoing spacer material layer 205a Material.
Exemplarily, the material of the second spacer material layer 208a includes non-crystalline silicon (a-Si) or other suitable materials.
Wherein, the second spacer material layer 208a can use low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid heat chemical One kind in vapour deposition (RTCVD) and molecular beam epitaxy (MBE).
Alternatively, the thickness of the second spacer material layer 208a is not limited to a certain number range.
Then, as illustrated in figure 2h, etch-back remove on first mandrel 204 and 206 top surface of the second mandrel and The second spacer material layer on 200 surface of Semiconductor substrate of part, with formed second clearance wall 208 and Second opening 2091, wherein, the is formed on the side wall of remaining first mandrel 204 and second mandrel 206 Two clearance walls 208, and pass through adjacent second clearance wall 208 of 2091 isolation of the second opening.
Wherein, for the etching step of the second spacer material layer on 200 surface of Semiconductor substrate, the erosion is stopped at Carve in stop-layer 203.
Second spacer material layer described in selecting dry etching in this step, in this step can in the dry etching To select CF4、CHF3In addition N is added2、CO2、O2In it is a kind of as etching atmosphere, wherein gas flow is CF4 10- 200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-150mTorr, during etching Between be 5-120s.
The size of second opening 2091 can be by the thickness of the second spacer material layer deposited in abovementioned steps Reasonably adjusted, its size corresponds to the size of the pattern of predetermined transfer, for example, the size of second opening 2091 can be with The size of first mandrel and the second mandrel is identical, namely has identical width.
The second opening 2091 is formd while etching forms the second clearance wall 208, and the etch stop is in described In etching stopping layer 203.
In one example, after second clearance wall 208 is formed, further include what the second clearance wall 208 was exposed Surface carries out the step of Ion Beam Treatment (ion beam treatment), to improve the roughness of the second gap wall surface, into And improve the line width roughness of the pattern of predetermined transfer, improve the precision of pattern transfer.
Ion used in Ion Beam Treatment may include the ion that intert-gas atoms produce, and intert-gas atoms are, for example, Ar or Xe etc..The surface that Ion Beam Treatment exposes the second clearance wall is acted on bombardment, can make the surface of the second clearance wall It is more smooth, reduce its surface roughness.
Then, as shown in figure 2i, the 3rd mandrel 209 is formed in the described second opening.
In one example, forming the method for the 3rd mandrel 209 includes:Mandrel material can be formed by deposition process Layer, full first opening of filling, and the top surface of first clearance wall is covered, then chemical machinery is carried out to mandrel material layer and is ground The planarisation steps such as mill, stop on the top surface of second clearance wall 208, to form the 3rd mandrel 209.
Wherein, the shape at the top of second opening 2091 may be irregular shape, such as section is inverted trapezoidal Shape or other shape, therefore, the cross sectional shape at the top of the 3rd mandrel 209 formed in this step accordingly is similar For inverted trapezoidal.
Then, as shown in fig. 2j, the second corona treatment is carried out, with first mandrel 204, second mandrel 206 and the 3rd mandrel 209 top formed second be modified mandrel material layer 210.
Wherein, the second corona treatment is with the mandrel at the top of modified first mandrel, second mandrel and the 3rd mandrel Material, and then form the second mandrel material layer 210 being modified.
Exemplarily, plasma includes H used in second corona treatment2And/or the plasma of He, Can also be that modified plasma occurs for other any materials that can make the first mandrel, second mandrel and the 3rd mandrel Body.
Further, the H2Or the production method of He plasmas can select method commonly used in the art, such as at this H is selected in one embodiment of invention2Or then He gases carry out plasma as working gas in the plasma source Change, select H2Or the pressure of the gas ions processing is 1-7torr during chamber described in He corona treatments, is chosen as 2- 5torr, the H2Or the flow velocity of He is 300-4000sccm, 500-800sccm is chosen as, the power is 100-2000w, example HFRF power is arranged to more than 100w as will be described, produces plasma to handle the chamber.
In this step processing time for 0.5-5 it is small when, be chosen as 0.5-1 it is small when, those skilled in the art can basis Actual needs makes choice, wherein, the part that the top of the 3rd mandrel 209 has irregular shape is all changed as long as can control Property.
Then, as shown in figure 2k, the described second mandrel material layer 210 being modified and second clearance wall 208 are removed.
Using diluted hydrofluoric acid DHF (wherein comprising HF and H in the step2O) selective etch removes described second Modified mandrel material layer 210, wherein, the concentration of the DHF does not limit strictly, in the present invention HF:H2The volume ratio of O It may range from 1:1000~1:2.
First mandrel 204, the second mandrel 206 that the described second mandrel material layer 210 being modified is not modified relatively There is high etching selectivity with the 3rd mandrel 209, for example, etching selectivity can be 1:4~1:In the range of 100, therefore, losing , will not be to the first mandrel 204, the second mandrel 206 and the 3rd mandrel when carving the mandrel material layer 210 for removing second modification 209 cause overetch, remain at least most of first mandrel 204, the second mandrel 206 and the 3rd mandrel 209, and by In in abovementioned steps, the core of the second modification will be all modified as with part of the top of the 3rd mandrel 209 with irregular shape The axial wood bed of material 210, in this step, etching removes and the second mandrel material layer 210 being modified at the top of the 3rd mandrel 209, then Remaining 3rd mandrel 209 then has well-regulated square contour, and remaining first mandrel 204, the second mandrel 206 and the 3rd core Axis 209 then has identical height.
And then had using the second clearance wall 208 opposite first mandrel 204, the second mandrel 206 and the 3rd mandrel 209 The wet etch process of high etching selectivity removes second clearance wall 208.
Specifically, the etchant being adapted to according to the material selection of the second clearance wall 208, for example, the material of the second clearance wall 208 Expect for non-crystalline silicon (a-Si) when, using inorganic base or organic alkali solution as etchant, inorganic base can be KOH, NaOH, NH4OH etc., organic base can be tetramethylammonium hydroxide (TMAH) solution or EDP (including ethylenediamine, hydroquinone and water) etc., In the present embodiment, the second clearance wall 208 is removed preferably using tetramethylammonium hydroxide (TMAH) solution.
Foregoing the first mandrel of formation, the first clearance wall, deposition shape are performed it is noted that can also further circulate Into the second mandrel, the step for forming the first mandrel material layer being modified, removing the first clearance wall and the first mandrel material layer being modified Suddenly several times, form the mandrel pattern with more fine pith, and then can realize and be transferred to the mandrel pattern of more fine pith Target material layer.
Then, as shown in figure 2l, with remaining first mandrel 204, the second mandrel 206 and the 3rd mandrel 209 for mask, erosion The target material layer 201 is carved, the pattern of the first mandrel 204, the second mandrel 206 and the 3rd mandrel 209 is transferred to target Material layer 201.
In one example, the etching stopping layer 203, the hard mask layer 202 and the target material are etched successively Layer 201.
Specifically, technique is it is known in the art that including but not limited to dry etching or wet method lose used by etching The methods of quarter, carries out above-mentioned etching, wherein, dry etching process can be reactive ion etching, ion beam milling, plasma etching, Any combination of laser ablation or these methods.Single engraving method can also be used, or can also use and be more than one A engraving method.
Here, need to be understood, through the above way can target material layer 201 formed grid structures, bit line and/ Or active area, the part as the semiconductor devices being subsequently formed., will be in target material layer 201 as an example Grid structure plan is formed, in this case, target material layer 201 can be conductive layer (for example, polysilicon layer) or metal layer (for example, tungsten layer or tungsten silicide layer).As another example, bit line pattern will be formed in target material layer 201, in this feelings In condition, target material layer 201 can be metal layer (for example, tungsten or aluminium lamination).Need to draw attention to, can also utilize the present invention's Hard mask layer forms active area pattern in target material layer 201, and in this case, target material layer 201 can be semiconductor Substrate, masking layer when hard mask layer 202 is as active area ion implanting at this time.Alternatively, it is also possible to be covered using the hard of the present invention The masking layer of the alternatively property epitaxial growth of film layer 202, and can also use it for occurring in the future needs appointing for masking layer What technique.
Finally, the etching stopping layer 203 and hard mask layer 202 are removed by etching, can specifically passes through wet etching Method, this will not be repeated here.
So far, the introduction of the committed step of the manufacture method of the semiconductor devices of the present embodiment is completed.For complete Prepared by device can also include other steps, not be defined herein.
In conclusion the manufacturing method of the present invention, by directly forming mandrel in the opening, and is changed by plasma treatment Property mandrel at the top of have irregular pattern part, to form modified mandrel material layer at the top of mandrel, the mandrel of the modification The mandrel that material layer is not modified relatively has high etching selectivity, and then realizes and remove modified mandrel material layer, obtains Square mandrel pattern of the shape for rule is obtained, and then realizes the progressively transfer of figure, mesh is finally formed in target material layer Mark on a map case, method of the invention, without using complicated material, cost is low, and process is simple, and the shape rule of the figure formed Then, the transfer precision of figure is high, and improves the line width roughness of figure by the method for Ion Beam Treatment, and then improves device The performance and robustness of part.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Claims (10)

  1. A kind of 1. manufacture method of semiconductor devices, it is characterised in that the described method includes:
    Semiconductor substrate is provided, on the semiconductor substrate formed with target material layer, in the target material layer formed with Several spaced first mandrels;
    The first clearance wall is formed on the side wall of first mandrel, and adjacent first gap is isolated by the first opening Wall;
    The second mandrel is filled in the described first opening;
    The first corona treatment is carried out, to form the first core being modified at the top of first mandrel and second mandrel The axial wood bed of material;
    Remove the described first mandrel material layer being modified and first clearance wall.
  2. 2. manufacture method as claimed in claim 1, it is characterised in that remove it is described first be modified mandrel material layer and It is further comprising the steps of after the step of first clearance wall:
    Form the second clearance wall on the side wall of remaining first mandrel and second mandrel, and by the second opening every From adjacent second clearance wall;
    The 3rd mandrel is filled in the described second opening;
    The second corona treatment is carried out, with the top shape of first mandrel, second mandrel and the 3rd mandrel The mandrel material layer being modified into second;
    Remove the described second mandrel material layer being modified and second clearance wall;
    Using remaining first mandrel, second mandrel and the 3rd mandrel as mask, the target material layer is etched.
  3. 3. manufacture method as claimed in claim 1, it is characterised in that forming the method for first clearance wall includes following step Suddenly:
    Conformal deposited the first spacer material layer, to cover first mandrel and the part semiconductor substrate surface;
    Etch-back removes first clearance wall on the first mandrel top surface and on the semiconductor substrate surface of part Material layer, to form first clearance wall and first opening.
  4. 4. manufacture method as claimed in claim 2, it is characterised in that after first clearance wall is formed, described in formation Before second mandrel, the step of further including the surface exposed using the first clearance wall described in Ion Beam Treatment, and/or, formed After second clearance wall, formed before the 3rd mandrel, further include and revealed using the second clearance wall described in Ion Beam Treatment The step of surface gone out.
  5. 5. manufacture method as claimed in claim 2, it is characterised in that plasma used in first corona treatment Body includes H2And/or the plasma of He, plasma includes H used in second corona treatment2And/or He Plasma.
  6. 6. manufacture method as claimed in claim 2, it is characterised in that forming the method for second clearance wall includes following step Suddenly:
    Conformal deposited the second spacer material layer, to cover first mandrel, second mandrel and the part semiconductor Substrate surface;
    Etch-back is removed on first mandrel and the second mandrel top surface and on the semiconductor substrate surface of part The second spacer material layer, to form second clearance wall and second opening.
  7. 7. manufacture method as claimed in claim 2, it is characterised in that the material of first clearance wall includes non-crystalline silicon, institute Stating the material of the second clearance wall includes non-crystalline silicon.
  8. 8. manufacture method as claimed in claim 2, it is characterised in that the material of first mandrel includes silicon nitride, described The material of second mandrel includes silicon nitride, and the material of the 3rd mandrel includes silicon nitride.
  9. 9. manufacture method as claimed in claim 2, it is characterised in that remove first modification using diluted hydrofluoric acid Mandrel material layer and the described second mandrel material layer being modified.
  10. 10. manufacture method as claimed in claim 1, it is characterised in that first mandrel and the target material layer it Between be also formed with the hard mask layer and etching stopping layer that stack gradually from bottom to top.
CN201610937649.5A 2016-10-24 2016-10-24 A kind of manufacture method of semiconductor devices Pending CN107978562A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1938858A (en) * 2004-03-31 2007-03-28 英特尔公司 Semiconductor device having a laterally modulated gate workfunction and method of fabrication
CN102013431A (en) * 2008-07-22 2011-04-13 旺宏电子股份有限公司 Mushroom type memory cell having self-aligned bottom electrode and diode access device
CN104779146A (en) * 2014-01-09 2015-07-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device manufacturing method
CN104952706A (en) * 2014-03-26 2015-09-30 中芯国际集成电路制造(上海)有限公司 Method for preparing semiconductor device
CN105097534A (en) * 2014-05-12 2015-11-25 中芯国际集成电路制造(上海)有限公司 Method of manufacturing semiconductor device
TW201610207A (en) * 2014-08-08 2016-03-16 應用材料股份有限公司 Multi materials and selective removal enabled reverse tone process

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1938858A (en) * 2004-03-31 2007-03-28 英特尔公司 Semiconductor device having a laterally modulated gate workfunction and method of fabrication
CN102013431A (en) * 2008-07-22 2011-04-13 旺宏电子股份有限公司 Mushroom type memory cell having self-aligned bottom electrode and diode access device
CN104779146A (en) * 2014-01-09 2015-07-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device manufacturing method
CN104952706A (en) * 2014-03-26 2015-09-30 中芯国际集成电路制造(上海)有限公司 Method for preparing semiconductor device
CN105097534A (en) * 2014-05-12 2015-11-25 中芯国际集成电路制造(上海)有限公司 Method of manufacturing semiconductor device
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Application publication date: 20180501