CN104952706B - A kind of preparation method of semiconductor devices - Google Patents
A kind of preparation method of semiconductor devices Download PDFInfo
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- CN104952706B CN104952706B CN201410116748.8A CN201410116748A CN104952706B CN 104952706 B CN104952706 B CN 104952706B CN 201410116748 A CN201410116748 A CN 201410116748A CN 104952706 B CN104952706 B CN 104952706B
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Abstract
The present invention relates to a kind of preparation method of semiconductor devices, methods described includes providing Semiconductor substrate, formed with self-aligned double patterning case mask stack in the Semiconductor substrate, the self-aligned double patterning case mask stack includes the hard mask layer, stop-layer, virtual core material layer sequentially formed；The virtual core material layer is patterned, to form multiple virtual cores being isolated from each other；Clearance wall is formed in the side wall of the virtual core；The virtual core is removed, retains the clearance wall；Using the clearance wall as mask, the stop-layer, the hard mask layer are etched, to transfer a pattern to the hard mask layer；Using the hard mask layer as Semiconductor substrate described in mask etch part, to form multiple fins in the Semiconductor substrate.It is the advantage of the invention is that state-of-the-art by being prepared from simplified autoregistration mask stack and simple technical process（state‑of the‑art）Fin structure.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of preparation method of semiconductor devices.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
The size of device is to improve its speed to realize.At present, due in high device density, high-performance and low cost is pursued half
Conductor industry has advanced to nanometer technology process node, and the preparation of semiconductor devices receives the limitation of various physics limits.
As challenge of the continuous diminution of cmos device from manufacture and design aspect promotes three dimensional design such as fin field to imitate
Answer transistor (FinFET) development.Relative to existing planar transistor, the FinFET is controlled and dropped in raceway groove
Low shallow ridges channel effect etc. has more superior performance；Planar gate is arranged above the raceway groove, and
Grid described in FinFET is set around the fin, therefore can control electrostatic from three faces, the property in terms of Electrostatic Control
Can be also more prominent, but there is also many challenges and potential technology barrier in finfet technology.
Due to the limit ultraviolet lithography in batch production（Extreme-ultra-violet, EUV）The delay of technology
（delayed deployment）, self-aligned double patterning case technology（Self-aligned double patterning, SADP）Skill
Art turns into the mask plate solution accepted extensively in the technology node that device size constantly reduces, therefore self-aligned double patterning case skill
Art（Self-aligned double patterning, SADP）Technology turns into a kind of choosing for preparing the less fin structure of size
Select.
In SADP technologies, complicated mask stack is widely studied, but many problems, example also occurs
Pre- fin structure conformability how is kept afterwards in virtual core etching such as in fin preparation process（conformality）, and
The morphotropism of the gap wall layer formed on pre- fin structure, the fin profile that the serious influence of above-mentioned factor is prepared with
And the uniformity of fin structure spacing.
Thus while the preparation of fin device and SADP technologies are widely used in the prior art, but apply
SADP technologies preparation FinFET, which also has many problems, to be needed to solve, to ensure that the fin being prepared is provided with good property
Energy.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
The present invention is in order to solve problems of the prior art, there is provided a kind of preparation method of semiconductor devices, bag
Include：
Semiconductor substrate is provided, formed with self-aligned double patterning case mask stack, the autoregistration in the Semiconductor substrate
Double patterning mask stack includes the hard mask layer, stop-layer, virtual core material layer sequentially formed；
The virtual core material layer is patterned, to form multiple virtual cores being isolated from each other；
Clearance wall is formed in the side wall of the virtual core；
The virtual core is removed, retains the clearance wall；
Using the clearance wall as mask, the stop-layer, the hard mask layer are etched, described is covered firmly with transferring a pattern to
Film layer；
It is more to be formed in the Semiconductor substrate using the hard mask layer as Semiconductor substrate described in mask etch part
Individual fin.
Preferably, the clearance wall selects SiCN layers.
Preferably, the stop-layer selects SiOCN layers.
Preferably, the virtual core material layer selects polysilicon layer.
Preferably, oxide skin(coating), advanced patterned masking layer and antireflection are also sequentially formed with the polysilicon layer
Dielectric layer.
Preferably, the method for forming the virtual core is：
The bottom anti-reflection layer and photoresist layer of patterning, wherein institute are formed on the self-aligned double patterning case mask stack
State on bottom anti-reflection layer and the photoresist layer formed with virtual core pattern；
The virtual core material layer is etched as mask layer using the bottom anti-reflection layer and the photoresist layer, by described in
Virtual core pattern is transferred in the virtual core material layer；
Remove the bottom anti-reflection layer and the photoresist layer.
Preferably, the method for forming the clearance wall is：
Spacer material layer is formed on the stop-layer and the virtual core；
Etching removes the spacer material layer above the stop-layer and above the virtual core, with the void
Clearance wall is formed in the side wall of nucleoid.
The remaining stop-layer is removed preferably, being still further comprised after pattern is transferred to the hard mask layer
Step.
Preferably, using the hard mask layer as Semiconductor substrate described in mask etch part after, methods described is also entered
One step includes：
Depositing isolation material layer, to cover the hard mask layer and the fin；
Planarisation step is performed, to remove the part hard mask layer；
Etching removes the part spacer material layer while removing the remaining hard mask layer, with described in exposed portion
Fin.
Preferably, the spacer material layer selects oxide skin(coating).
Preferably, from H3PO4Etching removes the remaining hard mask layer, while etches and remove the part isolation
Material layer.
Preferably, remove the virtual core from HF and TMAH.
Preferably, the hard mask layer includes the nitride layer and oxide skin(coating) sequentially formed.
The present invention provides a kind of self-aligned double patterning case lamination and technique to solve problems of the prior art
Preparation process, the technique can reduce the complexity of existing fin preparation technology, can be prepared state-of-the-art
（state-of the-art）Fin structure.
Selected polysilicon is used as and forms pre- fin in the present invention（pre-fin）Material, it is both described virtual for being formed
Core, the technique that etching forms virtual core may be referred to the etch process of virtual polysilicon, wherein, the line width of the virtual core is institute
State twice of clearance wall width even more than, therefore can be preferably in photoetching and etching process in current technology node
The virtual core is etched, further improves technique enough and to spare.
From SiCN as spacer material in we, while select SiCN/SiOCN/SIN/SiO2As hard mask
Mask of the layer as etching fin, to ensure the quality and uniformity during the fin etch.
The advantage of the invention is that：
（1）The present invention is most advanced by being prepared from simplified autoregistration mask stack and simple technical process
's（state-of the-art）Fin structure.
（2）The virtual core material layer selects polysilicon layer to make, and the virtual core etch process is simple and easy, and formation has
The virtual core profile of high unity.
（3）From etching stopping layers of the SiOCN as virtual core, the SiOCN has high etching selectivity and low
Wet etch rate, be more prone to control.
（4）The clearance wall selects SiN material layers, using the teaching of the invention it is possible to provide enough hardness is to ensure the clearance wall to be formed
With homogeneous profile, and there is relatively low wet etch rate, to ensure to be more prone to control in technical process.
（5）The hard mask layer selects SiN/SiO2, there is provided simpler technical process and integrated approach.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-1j are the process schematic that semiconductor devices is prepared in the embodiment of the invention；
Fig. 2 is to prepare semiconductor device technology schematic flow sheet in the embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present invention half
Conductor device and preparation method thereof.Obviously, execution of the invention is not limited to the spy that the technical staff of semiconductor applications is familiar with
Different details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have
Other embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in this manual
When, it, which is indicated, has the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or more
Individual other features, entirety, step, operation, element, component and/or combinations thereof.
Now, the exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Understand be to provide these embodiments be in order that disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated
Degree, and make identical element is presented with like reference characters, thus description of them will be omitted.
The present invention is in order to solve problems of the prior art, there is provided a kind of preparation method of semiconductor devices, bag
Include：
Semiconductor substrate is provided, formed with self-aligned double patterning case mask stack, the autoregistration in the Semiconductor substrate
Double patterning mask stack includes the hard mask layer, stop-layer, virtual core material layer sequentially formed；
The virtual core material layer is patterned, to form the virtual core being isolated in the virtual core material layer；
Clearance wall is formed in the side wall of the virtual core；
Remove the virtual core, the remaining clearance wall；
Using the clearance wall as mask, the stop-layer, the hard mask layer are etched, described is covered firmly with transferring a pattern to
Film layer；
Using the hard mask layer as Semiconductor substrate described in mask etch part, to form fin in the Semiconductor substrate
Piece.
The preparation method of semiconductor devices of the present invention is described further with reference to Fig. 1 a-1j.
First, step 201 is performed, there is provided Semiconductor substrate, form autoregistration mask stack on the semiconductor substrate.
Specifically, as shown in Figure 1a, there is provided Semiconductor substrate 201, the Semiconductor substrate following can be previously mentioned
At least one of material：Silicon-on-insulator（SOI）, be laminated silicon on insulator（SSOI）, be laminated SiGe on insulator（S-
SiGeOI）, germanium on insulator SiClx（SiGeOI）And germanium on insulator（GeOI）Deng in the semiconductor substrate can be with shape
Into other active devices.
With continued reference to Fig. 1 a, hard mask layer is formed over the substrate；Hard mask layer includes the nitride layer sequentially formed
202 and oxide skin(coating) 203, the nitride can include
The hard mask layer includes one kind in SiN and SiON, or selects other nitride commonly used in the art, not
Cited example is confined to, the oxide can also select conventional oxide including Si oxide etc..
Hard mask layer selects SiN and SiO described in the embodiment of the present invention2, the hard mask layer offer
Simpler technical process and integrated approach, specifically, SiO are deposited in the Semiconductor substrate 2012, Ran Houzai
SiN is deposited, the deposition process can select chemical vapor deposition
（CVD）Method, physical vapour deposition (PVD)（PVD）Method or ald（ALD）The low pressure chemical phase of the formation such as method sinks
One kind in product (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG).
Alternatively embodiment, in the present invention the hard mask layer can also select SiCN/SiOCN/SIN/
SiO2The lamination of formation.
Then stop-layer 204 is formed on the hard mask layer, the stop-layer 204 is as the etching virtual nuclear process
In etching stopping layer, the stop-layer 204 from and virtual core material layer there is the material of high etch selection ratio, it is described to stop
Only layer 204 should have relatively low wet etch rate, and stop-layer 204 is selected described in the embodiment of the present invention
SiOCN, SiOCN have high etching selectivity and low wet etch rate, are more prone to control.
Then virtual core material layer is formed on the stop-layer 204, the virtual core material layer should select etching work
The simple and easy material of skill, while ensure to form the virtual core profile with high unity after etching, in the tool of the present invention
In body embodiment into virtual core material layer include sequentially form polysilicon layer 205, oxide skin(coating) 206, advanced patterned mask
Layer 207 and antireflection dielectric layer 208（stack poly silicon/oxide/APF/DARC）The lamination of formation.
Selected polysilicon is used as and forms pre- fin in the present invention（pre-fin）Material, it is both described virtual for being formed
Core, the technique that etching forms virtual core may be referred to the etch process of virtual polysilicon, wherein, the line width of the virtual core is institute
State twice of clearance wall width even more than, therefore can be preferably in photoetching and etching process in current technology node
The virtual core is etched, further improves technique enough and to spare.
Step 202 is performed, the bottom anti-reflection layer and light of patterning are formed on the self-aligned double patterning case mask stack
Photoresist layer.
Specifically, as shown in Figure 1 b, wherein formed with virtual core figure on the bottom anti-reflection layer and the photoresist layer
Case, the virtual core pattern are the virtual core isolated each other, wherein, the height and number of the virtual core can roots
Set according to being actually needed, it is not limited to a certain number range, wherein, patterning can also be only formed in this step
Photoresist layer.
Step 203 is performed, the virtual core material is etched as mask layer using the bottom anti-reflection layer and the photoresist layer
The bed of material, the virtual core pattern is transferred in the virtual core material layer.
Specifically, as illustrated in figure 1 c, in this step from virtual core material layer described in wet method or dry etching, etching
Polysilicon layer 205, oxide skin(coating) 206, advanced patterned masking layer 207 and antireflection dielectric layer 208（stack poly
silicon/oxide/APF/DARC）The lamination of formation.
Preferably, the purpose is realized from dry etching in the embodiment of the present invention, and dry
CF can be selected in method etching4、CHF3Add N in addition2、CO2、O2In a kind of as etching atmosphere, wherein gas flow be
CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-150mTorr, erosion
Time at quarter is 5-120s, preferably 5-60s, more preferably 5-30s.
Etching removes the part virtual core material layer after forming the virtual core, such as removes remaining advanced pattern
Mask layer 207 and antireflection dielectric layer 208, only retain polysilicon layer 205, oxide skin(coating) 206.
Etching stopping layer of the stop-layer 204 as the virtual core in this step, the stop-layer 204 and described
Crystal silicon layer 205 should have larger etching selectivity.Form the virtual core and remove the photoresist layer and the bottom afterwards
Portion's anti-reflecting layer.
Step 204 is performed, spacer material layer is formed on the stop-layer 204 and the virtual core.
Specifically, as shown in Figure 1 d, the spacer material layer is required to provide enough hardness to be formed to ensure
The clearance wall there is homogeneous profile, and there is relatively low wet etch rate, to ensure more to hold in technical process
It is easy to control.
The spacer material layer should also have larger etching selectivity with the virtual core material layer, to go
The clearance wall will not be caused to damage during except the virtual core.
Preferably, preferred SiN material layers in the present invention.
Step 205 is performed, etching removes the gap wall material above the top of stop-layer 204 and the virtual core
The bed of material, to form clearance wall 209 in the side wall of the virtual core.
Specifically, as shown in fig. le, the method for selecting overall etch in the step, etches the spacer material, to go
Except the spacer material layer above the stop-layer 204 and above the virtual core, and retain the side of the virtual core
The spacer material layer on wall, to form the clearance wall 209.
Specific engraving method can select method commonly used in the art, will not be repeated here.
Perform step 206 and remove the virtual core, the remaining clearance wall 209.
Specifically, as shown in Figure 1 f, remove the virtual core from wet etching in this step, from the gap
The method that wall 209 and the stop-layer 204 have larger etching selectivity removes the virtual core.
Wherein, the clearance wall 209 and the stop-layer 204 are respectively provided with relatively low wet etching speed in this step
Rate, to ensure that the clearance wall has good profile and good homogeneity.
Specifically, in this step from HF and TMAH（TMAH）The virtual core is removed, in the step
It is middle to etch the virtual core from HF and TMAH solution, preferably, the mass fraction of the TMAH solution is 0.1%-10%, institute
Wet etching temperature is stated as 25-90 DEG C, the wet etch time is 10s-1000s.
Step 207 is performed, is mask with the clearance wall 209, etches the stop-layer 204, the hard mask layer, will
Pattern is transferred to the hard mask layer, using the hard mask layer as Semiconductor substrate 201 described in mask etch part, with described
Fin is formed in Semiconductor substrate 201.
Specifically, as shown in Figure 1 g, it is mask with the clearance wall 209, etches the stop-layer 204, the hard mask
Layer, to transfer a pattern to the hard mask layer, then removes the stop-layer 204, in this step from dry etching or
Person's wet etching, it is not limited to a certain.
It can be selected in the dry etching from dry method with to form fin in the embodiment of the present invention
Use CF4、CHF3, in addition plus N2、CO2、O2In it is a kind of as etching atmosphere, wherein gas flow is CF410-200sccm,
CHF310-300sccm, N2Or CO2Or O210-300sccm, the etching pressure are 30-250mTorr, etching period 5-
180s, preferably 5-60s, more preferably 5-30s, the dry etching can also select Ar as diluent gas.
Perform step 208, depositing isolation material layer 210, to cover the hard mask layer and the fin.
Specifically, as shown in figure 1h, in this step deposited oxide layer as the separation layer, the height of the separation layer
Degree is more than the hard mask layer, so that the hard mask layer and the fin is completely covered.
Preferably, the spacer material layer 210 selects oxide skin(coating) commonly used in the art, preferably SiO2, it is described heavy
Product method can select chemical vapor deposition（CVD）Method, physical vapour deposition (PVD)（PVD）Method or ald（ALD）The shapes such as method
Into low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG) in one kind.
Step 209 is performed, planarisation step is performed, to remove the part hard mask layer.
Specifically, as shown in figure 1i, perform planarisation step in this step, with remove the part spacer material layer and
Oxide skin(coating) in the hard mask layer of part.
The flat of surface can be realized using flattening method conventional in field of semiconductor manufacture in this embodiment
Change.The non-limiting examples of the flattening method include mechanical planarization method and chemically mechanical polishing flattening method.
Step 210 is performed, etching removal part spacer material layer while removing the remaining hard mask layer
210, with fin described in exposed portion.
Specifically, as shown in fig. ij, in this step, there is larger etching selectivity from the Semiconductor substrate
Method removes the part spacer material layer 210, with fin described in exposed portion.
The remaining hard mask layer is removed from H3PO4 etchings in the embodiment of the present invention, is lost simultaneously
Carve and remove the part spacer material layer 210, with fin described in exposed portion, form the mutually isolated fin structure in bottom.
Hot H is selected in this step3PO4It is etched, in order to obtain more preferable etch effect, is lost from hot phosphoric acid
Carve, the temperature of the hot phosphoric acid is 20-60 DEG C, preferably, the temperature of the hot phosphoric acid is 40-50 DEG C, its concentration can be selected
With normal concentration, it is not limited to a certain scope, while other etching solutions can also be selected in this step.
Preferably, methods described may further include the step of all around gate is formed on the fin, further,
The step of forming source and drain is can further include after forming grid, wherein the grid and source and drain, which are formed, can select this
Field common method.The fin of different height is used for forming more channel FinFETs in the method for the invention, also
It can be used for forming multiple different FinFETs.
The present invention provides a kind of self-aligned double patterning case lamination and technique to solve problems of the prior art
Preparation process, the technique can reduce the complexity of existing fin preparation technology, can be prepared state-of-the-art
（state-of the-art）Fin structure.
Selected polysilicon is used as and forms pre- fin in the present invention（pre-fin）Material, it is both described virtual for being formed
Core, the technique that etching forms virtual core may be referred to the etch process of virtual polysilicon, wherein, the line width of the virtual core is institute
State twice of clearance wall width even more than, therefore can be preferably in photoetching and etching process in current technology node
The virtual core is etched, further improves technique enough and to spare.
From SiCN as spacer material in we, while select SiCN/SiOCN/SIN/SiO2As hard mask
Mask of the layer as etching fin, to ensure the quality and uniformity during the fin etch.
The advantage of the invention is that：
（1）The present invention is most advanced by being prepared from simplified autoregistration mask stack and simple technical process
's（state-of the-art）Fin structure.
（2）The virtual core material layer selects polysilicon layer to make, and the virtual core etch process is simple and easy, and formation has
The virtual core profile of high unity.
（3）From etching stopping layers of the SiOCN as virtual core, the SiOCN has high etching selectivity and low
Wet etch rate, be more prone to control.
（4）The hard mask layer selects SiN/SiO2, there is provided simpler technical process and integrated approach.
Fig. 2 is the process chart that the present invention prepares semiconductor devices, is comprised the following steps：
Step 201 provides Semiconductor substrate, described formed with self-aligned double patterning case mask stack in the Semiconductor substrate
Self-aligned double patterning case mask stack includes the hard mask layer, stop-layer, virtual core material layer sequentially formed；
Step 202 patterns the virtual core material layer, to form multiple virtual cores being isolated from each other；
Step 203 forms clearance wall in the side wall of the virtual core；
Step 204 removes the virtual core, retains the clearance wall；
Step 205 etches the stop-layer, the hard mask layer, to transfer a pattern to using the clearance wall as mask
The hard mask layer；
Step 206 is using the hard mask layer as Semiconductor substrate described in mask etch part, with the Semiconductor substrate
It is middle to form multiple fins.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided, formed with self-aligned double patterning case mask stack, the self-aligned double patterning in the Semiconductor substrate
Case mask stack includes the hard mask layer, stop-layer, virtual core material layer sequentially formed；
The virtual core material layer is patterned, to form multiple virtual cores being isolated from each other；
Clearance wall is formed in the side wall of the virtual core；
The virtual core is removed, retains the clearance wall；
Using the clearance wall as mask, the stop-layer, the hard mask layer are etched, to transfer a pattern to the hard mask
Layer；
Using the hard mask layer as Semiconductor substrate described in mask etch part, to form multiple fins in the Semiconductor substrate
Piece；
Wherein, the stop-layer selects SiOCN layers, and the virtual core material layer selects polysilicon layer.
2. according to the method for claim 1, it is characterised in that the clearance wall selects SiCN layers.
3. according to the method for claim 1, it is characterised in that be also sequentially formed with the polysilicon layer oxide skin(coating),
Advanced patterned masking layer and antireflection dielectric layer.
4. according to the method for claim 1, it is characterised in that the method for forming the virtual core is：
The bottom anti-reflection layer and photoresist layer of patterning are formed on the self-aligned double patterning case mask stack, wherein the bottom
Formed with virtual core pattern on portion's anti-reflecting layer and the photoresist layer；
The virtual core material layer is etched as mask layer using the bottom anti-reflection layer and the photoresist layer, will be described virtual
Core pattern is transferred in the virtual core material layer；
Remove the bottom anti-reflection layer and the photoresist layer.
5. according to the method for claim 1, it is characterised in that the method for forming the clearance wall is：
Spacer material layer is formed on the stop-layer and the virtual core；
Etching removes the spacer material layer above the stop-layer and above the virtual core, with the virtual core
Side wall on form clearance wall.
6. according to the method for claim 1, it is characterised in that also further after pattern is transferred to the hard mask layer
The step of including removing the remaining stop-layer.
7. the method according to claim 1 or 6, it is characterised in that using the hard mask layer as described in mask etch part
After Semiconductor substrate, methods described still further comprises：
Depositing isolation material layer, to cover the hard mask layer and the fin；
Planarisation step is performed, to remove the part hard mask layer；
Etching removes the part spacer material layer while removing the remaining hard mask layer, with fin described in exposed portion
Piece.
8. according to the method for claim 7, it is characterised in that the spacer material layer selects oxide skin(coating).
9. according to the method for claim 7, it is characterised in that from H3PO4Etching removes the remaining hard mask layer,
Etch simultaneously and remove the part spacer material layer.
10. according to the method for claim 1, it is characterised in that remove the virtual core from HF and TMAH.
11. according to the method for claim 1, it is characterised in that the hard mask layer includes the nitride layer sequentially formed
And oxide skin(coating).
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| CN107978562A (en) * | 2016-10-24 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN108735711B (en) * | 2017-04-13 | 2021-04-23 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device, preparation method thereof and electronic device |
| CN109585279B (en) * | 2018-11-30 | 2020-11-20 | 上海华力微电子有限公司 | Method for forming self-aligned double-layer pattern |
| CN112530804A (en) * | 2019-09-17 | 2021-03-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113284954B (en) * | 2021-07-22 | 2021-09-24 | 成都蓉矽半导体有限公司 | Silicon carbide MOSFET with high channel density and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101542390A (en) * | 2006-11-14 | 2009-09-23 | Nxp股份有限公司 | Double patterning for lithography to increase feature spatial density |
| CN102347217A (en) * | 2010-07-27 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for making fine pattern on semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101871748B1 (en) * | 2011-12-06 | 2018-06-28 | 삼성전자주식회사 | Method for forming pattern of semiconductor device |
-
2014
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Patent Citations (2)
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| CN101542390A (en) * | 2006-11-14 | 2009-09-23 | Nxp股份有限公司 | Double patterning for lithography to increase feature spatial density |
| CN102347217A (en) * | 2010-07-27 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for making fine pattern on semiconductor device |
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