CN103794497B - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
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- CN103794497B CN103794497B CN201210422103.8A CN201210422103A CN103794497B CN 103794497 B CN103794497 B CN 103794497B CN 201210422103 A CN201210422103 A CN 201210422103A CN 103794497 B CN103794497 B CN 103794497B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 96
- 239000000463 material Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 150000004767 nitrides Chemical group 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 239000012212 insulator Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, methods described includes：Semiconductor substrate is provided, the substrate includes the support substrate stacked gradually, oxide insulating layer, semiconductor material layer；The first hard mask layer is formed over the substrate；First hard mask layer, the semiconductor material layer, the oxide insulating layer and the part support substrate are patterned, the stairstepping substrate with high area and low area is formed；Clearance wall is formed on the side wall in the high area；In low area's Epitaxial growth semiconductor material layer, peel off remaining first hard mask layer and planarize, form mixed substrates；The second hard mask layer is formed in mixed substrates；High area and low area are etched, the high area is etched to the oxide insulating layer, to form the first fin, etches below the low area to the oxide insulating layer, to form the second fin.The method of the invention is simpler, accurate, further improves efficiency and yield prepared by device.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor devices and preparation method thereof.
Background technology
The raising of performance of integrated circuits, which mainly passes through, constantly to be reduced the size of IC-components to improve its speed
Come what is realized.At present, due in high device density, high-performance and low cost is pursued semi-conductor industry have advanced to a nanometer skill
Art process node, the challenge from manufacture and design aspect has resulted in three dimensional design such as FinFET
(FinFET) development.Using from extended by the substrate as formed by etching away a part of silicon layer thin vertical " fin " (or
Fin structure) the typical FinFET of manufacture.By FinFET raceway groove formation in the vertical fin, in the upper of the fin
It is square to control raceway groove from both sides into all around gate, and by grid.In addition, in FinFET recess source/drain electrode (S/D) part
In, it can be used for improving carrier mobility using selective growth strain gauge material.
Relative to existing planar transistor, the FinFET has more superior property in terms of Electrostatic Control
Can, therefore be widely used.Fin all has identical described in FinFET transistors in the equipment of conventional FinFET
Highly.In order to further improve FinFET performance, the fin with different height can be prepared, in the prior art in order to obtain
The field-effect transistor for obtaining the different fins of height uses following methods：As shown in figure 1, forming oxygen over the semiconductor substrate 10 first
Compound layer 11, then 12 such as silicon or polysilicon of deposited semiconductor material layer, are finally formed on the semiconductor material layer
The mask layer of silicon nitride layer 13 and patterning, etches above-mentioned lamination formation opening and exposes the semiconductor material layer, to being revealed
The semiconductor material layer gone out is aoxidized, and is formed silicon dioxide layer 14, as shown in Fig. 2 removing the mask layer, is re-formed fin
Mask layer 15, as shown in figure 3, then using fin mask layer described in mask etch nitride layer 13, semiconductor material layer 12, such as
Shown in Fig. 4, the fin mask layer 14 is removed, fin is obtained, as shown in figure 5, eventually forming grid and source and drain such as Fig. 6 institutes
Show, by carrying out the height that oxidation changes semiconductor material layer to semiconductor material layer in the technical scheme, as substrate
Highly different fins are formed, change the performance of the FinFET and the width of transistor overall channel, still
The ratio between the height of the fin, the fin height and the channel width that is formed all are not easily controlled in the process, shadow
The performance of FinFET and the yield of product are rung.
Fin height is difficult control described in the current FinFET preparation process, and existing preparation method is also
The problem is not can solve, have impact on the performance of the FinFET.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in embodiment part
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
The invention provides a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided, the substrate includes the support substrate stacked gradually, oxide insulating layer, semi-conducting material
Layer；
The first hard mask layer is formed over the substrate；
Pattern first hard mask layer, the semiconductor material layer, the oxide insulating layer and the part branch
Substrate is supportted, to remove part first hard mask layer, the semiconductor material layer, the oxide insulating layer and the support
Substrate, forms the stairstepping substrate with high area and low area；
Clearance wall is formed on the side wall in the high area, to protect the support substrate；
In low area's Epitaxial growth semiconductor material layer, remaining first hard mask layer is then peeled off and flat
Change, so that the low area is concordant with the high area, form mixed substrates；
The second hard mask layer is formed in the mixed substrates；
The high area and the low area are etched, the high area is etched to the oxide insulating layer, to form the first fin,
Etch below the low area to the oxide insulating layer, to form second fins different from first fin height.
Preferably, methods described is further comprising the steps of：
Clearance wall is formed on the side wall of first fin and second fin, to protect first fin and institute
State the second fin；
Etching removes the support substrate in the part low area, to expose the support substrate of the second fin bottom；
The support substrate of the second fin bottom is aoxidized, to form oxide, the dielectric layer of second fin is used as；
The clearance wall on the side wall of first fin and second fin is peeled off, to form highly different fins.
Preferably, below the etching low area to the upper surface of the oxide insulating layer, to be formed and described first
The second different fin of fin height.
Preferably, forming conformal clearance wall on the side wall of first fin and second fin.
Preferably, first hard mask layer is nitride layer.
Preferably, first hard mask layer is SiN layer.
Preferably, second hard mask layer is SiON layers, BN layers or SiCN layers.
Preferably, the patterning method is the mask that patterning is formed on first hard mask layer, Ran Houjin
Row reactive ion etching.
Preferably, the method that clearance wall is formed on the side wall in the high area is：
In the high area and low area's deposition spacer material floor, overall etch is then carried out, with the side in the high area
Clearance wall is formed on wall.
Preferably, being Si material layers in low area's Epitaxial growth semiconductor material layer.
Preferably, from high area described in reactive ion etching and the low area, to form first fin and described
Second fin.
Preferably, the support substrate in the part low area is removed from reactive ion etching, to expose second fin
The support substrate of piece bottom.
Preferably, the support substrate and the semiconductor material layer are Si layers.
Present invention also offers the semiconductor devices that a kind of above method is prepared.
Semiconductor devices of the present invention is the fin field effect transistor with different height fin based on mixed substrates
Pipe（FinFETs）, part is removed by forming etching after the first hard mask layer over the substrate in the present invention, to expose
Semiconductor substrate is stated, then in the Semiconductor substrate Epitaxial growth semiconductor epitaxial layers exposed, by the step in the lining
The semiconductor material layer of different-thickness is provided with bottom, then etching ultimately forms the fin of different height, the height of the fin
The thickness difference of semiconductor material layer in Du Chaweigao areas and low area, by controlling high area and low Qu Zhongban during device is prepared
The thickness of conductor material layer just can control the difference in height of the fin so that the height of fin is more prone to control, institute of the present invention
State that method is simpler, accurate, further improve efficiency and yield prepared by device.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the device and principle of the present invention.In the accompanying drawings,
Fig. 1-6 is prepares the process schematic of semiconductor devices in the present invention；
Fig. 7-15 is prepares the process schematic of semiconductor devices in the present invention；
Figure 16 for the present invention in prepare semiconductor device technology schematic flow sheet.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present invention half
Conductor device and preparation method thereof.Obviously, execution of the invention is not limited to the spy that the technical staff of semiconductor applications is familiar with
Different details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have
Other embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that, when in this manual use term "comprising" and/or " comprising "
When, it indicates there is the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or many
Other individual features, entirety, step, operation, element, component and/or combinations thereof.
Now, the exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Understand be to provide these embodiments be in order that disclosure of the invention is thoroughly and complete, and these exemplary are implemented
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated
Degree, and make identical element is presented with like reference characters, thus description of them will be omitted.
It is described further with reference to the preparation method of Fig. 7-15 pairs of semiconductor devices of the present invention, institute of the present invention
Semiconductor devices is stated for the FinFET with different height fin based on mixed substrates（FinFETs）：
Reference picture 7 is there is provided Semiconductor substrate, and the Semiconductor substrate can be at least one in the following material being previously mentioned
Kind：Silicon-on-insulator（SOI）, be laminated silicon on insulator（SSOI）, be laminated SiGe on insulator（S-SiGeOI）, on insulator
SiGe（SiGeOI）And germanium on insulator（GeOI）Deng other active devices can also be formed in the semiconductor substrate.
Preferred silicon-on-insulator in the present invention（SOI）, the silicon-on-insulator（SOI）Including being followed successively by support substrate from the bottom up
201st, oxide insulating layer 202 and semiconductor material layer 203, wherein the semiconductor material layer at the top be monocrystalline silicon layer,
Polysilicon layer, SiC or SiGe.The SOI substrate passes through direct wafer bonding in the present invention（direct wafer
bonding）Formed.
Because SOI is made into below device active region having oxide insulating layer 202, the oxide insulating layer 202 is embedding
In semiconductor base layer, so that device has more excellent performance, but above-mentioned example is not limited to.
As further preferably, the support substrate and the semiconductor material layer are Si layers in the present invention.
With continued reference to Fig. 7, the first hard mask layer is formed over the substrate；
Specifically, in the silicon-on-insulator（SOI）Upper to deposit the first hard mask layer 204, first hard mask layer is
Nitride layer, preferably SiN, the deposition process of first hard mask layer can select chemical vapor deposition（CVD）Method, physics
Vapour deposition（PVD）Method or ald（ALD）Low-pressure chemical vapor deposition (LPCVD), the laser ablation of the formation such as method sink
One kind in product (LAD) and selective epitaxy growth (SEG).
Reference picture 8, patterns first hard mask layer, the semiconductor material layer, the oxide insulating layer and portion
Point support substrate, with remove part first hard mask layer, the semiconductor material layer, the oxide insulating layer and
The support substrate, forms the stairstepping substrate with high area and low area；
Specifically, the mask layer of patterning is formed in the mixed substrates, then using described in reactive ion etching
One hard mask layer, the semiconductor material layer, the oxide insulating layer and the part support substrate, are etched in this process
To the support substrate and the part support substrate is removed, to form high area II and low area I in the mixed substrates, wherein
The thickness of the support substrate of removal can be the 1/5-1/2 of the support substrate thickness, but be not limited to the thickness.
Formed in this step after step-like substrate, different zones form partly leading for different-thickness on a semiconductor substrate
Body material layer, to form the fin of different height in subsequent technique.
Reference picture 9, clearance wall is formed on the side wall in the high area, to protect the support substrate；
Specifically, in the high area and low area's deposition spacer material floor, overall etch is then carried out（Blanket
etch）, only retain the spacer material layer being located on the wall of the Gao Qu sides, to form clearance wall on the side wall in the high area.
The clearance wall can be a kind of or their combination compositions in silica, silicon nitride, silicon oxynitride.It is used as this reality
An optimal enforcement mode of example is applied, the clearance wall is silica, silicon nitride is collectively constituted, and concrete technology is：In semiconductor
The first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer are formed on substrate, then using overall etch（Blanket
etch）Method formation clearance wall.
Reference picture 10, in low area's Epitaxial growth semiconductor material layer, then peels off the remaining first hard mask
Layer is simultaneously planarized, so that the low area is concordant with the high area, obtains mixed substrates；
Specifically, the support substrate Epitaxial growth semiconductor material layer exposed in the low area, is formed outside semiconductor
Prolong layer, preferably, the semiconductor epitaxial layers selection and the semiconductor material layer identical material, for example silicon, polysilicon,
SiC or SiGe, the semiconductor epitaxial layers can be from reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, heterogeneous outer
Prolong and molecular beam epitaxy, extension preferably selected in the present invention, carry out epitaxial process described in silicon material layer or
Polysilicon material layer grows only on the semiconductor material layer, without the extension on the mask layer, makes the process more
Simply, it is to avoid outer to delay material layer on removal mask layer.
After semiconductor material layer described in epitaxial growth, in addition to the step of stripping first hard mask layer, remove described
First hard mask layer, exposes the semiconductor material layer in the high area and then performs a planarisation step, to ensure the extension
Semiconductor material layer and the high area in semiconductor material layer there is same height, to obtain even curface, in this hair
Preferred chemical-mechanical planarization in bright.
With continued reference to Figure 10, the second hard mask layer 208 is formed in the mixed substrates；
Specifically, the second hard mask layer 208 is formed in the mixed substrates, second hard mask layer is preferably difference
In SiN material, one or more preferably in BN, SiCN and SiON in the present invention, second hard mask layer
Deposition process can select chemical vapor deposition（CVD）Method, physical vapour deposition (PVD)（PVD）Method or ald（ALD）Method etc.
One kind in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selective epitaxy growth (SEG) of formation.
Reference picture 11, etches the high area and the low area, the high area is etched to the oxide insulating layer, to be formed
First fin, is etched below the low area to the oxide insulating layer, to form different from first fin height the
Two fins.
Specifically, second hard mask layer is patterned, is covered with forming fin pattern in the high area and the low area
Film, as the etch mask layer for forming fin in subsequent step, in the embodiment of the present invention, first described the
Formed on two hard mask layers and define to be formed fin shapes on the photoresist layer of patterning, the photoresist layer, then with
The photoresist layer is mask patterning second hard mask layer, finally removes photoresist.
The second hard mask layer using the patterning is mask, from high area described in reactive ion etching and the low area,
To be formed respectively in the high area and low area to form first fin 20 and the ˊ of the second fin 20.Wherein described
The ˊ of two fin 20 height is more than the height of first fin 20, and the difference in height is the difference in height in the high area and low area.
Etch below the low area to the upper surface of the oxide insulating layer, be more preferably etched to described in the present invention
Position between the upper and lower surface of oxide insulating layer, to form second fins different from first fin height
Piece.
Reference picture 12, clearance wall is formed on the side wall of first fin and second fin, to protect described
One fin and second fin；
Specifically, conformal clearance wall 206, the gap are formed on the side wall of first fin and second fin
Wall can be a kind of or their combination compositions in silica, silicon nitride, silicon oxynitride.It is real as an optimization of the present embodiment
Mode is applied, the clearance wall is silica, silicon nitride is collectively constituted, and concrete technology is：The first oxygen is formed on a semiconductor substrate
SiClx layer, the first silicon nitride layer and the second silicon oxide layer, it is described in the present invention then using engraving method formation clearance wall
Conformal clearance wall act as protection first fin and second fin on the side wall of first fin and second fin
Piece is not oxidized in high-temperature oxidising step below, therefore, and the material of the clearance wall does not limit to above-mentioned material, as long as can
First fin and second fin are surrounded and played a protective role.
Reference picture 13, etching removes the support substrate in the part low area, to expose the support of the second fin bottom
Substrate；
Specifically, the support substrate in the part low area is removed from reactive ion etching in the present invention, to expose
State the support substrate of the second fin bottom, wherein using second fin pattern containing clearance wall described in mask etch low area
In support substrate, to remove part support substrate, under second fin formed with same widths extension fin.Institute
Extension fin is stated to be oxidized to be formed through barrier dielectric layer in technique below（punch stop dielectric
layer）.
In this step preferably, etch below the support substrate to the lower surface of the oxide insulating layer, to ensure
The high area is connected with the oxide insulating layer in low area after oxidation step is performed.
Reference picture 14, aoxidizes the support substrate of the second fin bottom, to form oxide, is used as second fin
Dielectric layer；
Specifically, in the present invention from the support substrate under the second fin described in high-temperature oxydation and the second fin bottom
The extension fin in portion, forms oxide skin(coating), to run through barrier dielectric layer as the second fin（punch stop
dielectric layer）.The oxidizing temperature is more than 1200 DEG C in the present invention, to ensure to form the dielectric layer
（punch stop dielectric layer）Thickness, it is ensured that the performance of device.
Reference picture 15, peels off the clearance wall on the side wall of first fin and second fin, to form height not
Same fin.
Preferably, methods described may further include the step of forming all around gate on the fin, further,
The step of forming source and drain is can further include after forming grid, wherein the grid and source and drain, which are formed, can select this
Field common method.The fin of different height is used for forming many channel FinFETs in the method for the invention, also
Can be for the multiple different FinFETs of formation.
Part is removed by forming etching after the first hard mask layer in the mixed substrates in the present invention, to expose
Semiconductor substrate is stated, then in the Semiconductor substrate Epitaxial growth semiconductor epitaxial layers exposed, by the step in the lining
The semiconductor material layer of different-thickness is provided with bottom, then etching ultimately forms the fin of different height, the height of the fin
The thickness difference of semiconductor material layer in Du Chaweigao areas and low area, by controlling high area and low Qu Zhongban during device is prepared
The thickness of conductor material layer just can control the difference in height of the fin so that the height of fin is more prone to control, institute of the present invention
State that method is simpler, accurate, further improve efficiency and yield prepared by device.
Figure 16 prepares the process chart of semiconductor devices for the present invention, comprises the following steps：
Step 201 provides Semiconductor substrate, and the substrate includes the support substrate stacked gradually, oxide insulating layer, half
Conductor material layer；
Step 202 forms the first hard mask layer over the substrate；
Step 203 patterns first hard mask layer, the semiconductor material layer, the oxide insulating layer and part
The support substrate, to remove part first hard mask layer, the semiconductor material layer, the oxide insulating layer and institute
Support substrate is stated, the stairstepping substrate with high area and low area is formed；
Step 204 forms clearance wall on the side wall in the high area, to protect the support substrate；
Then step 205 peels off the remaining first hard mask in low area's Epitaxial growth semiconductor material layer
Layer is simultaneously planarized, so that the low area is concordant with the high area, forms mixed substrates；
Step 206 forms the second hard mask layer in the mixed substrates；
Step 207 etches the high area and the low area, etches the high area to the oxide insulating layer, to form the
One fin, is etched below the low area to the oxide insulating layer, to form second different from first fin height
Fin；
Step 208 forms clearance wall on the side wall of first fin and second fin, to protect described first
Fin and second fin；
Step 209 etching removes the support substrate in the part low area, is served as a contrast with the support for exposing the second fin bottom
Bottom；
Step 210 aoxidizes the support substrate of the second fin bottom, to form oxide, is used as second fin
Dielectric layer；
Step 211 peels off the clearance wall on the side wall of first fin and second fin, different to form height
Fin.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member according to the teachings of the present invention it is understood that the invention is not limited in above-described embodiment, can also make more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided, the substrate includes the support substrate stacked gradually, oxide insulating layer, semiconductor material layer；
The first hard mask layer is formed over the substrate；
Pattern first hard mask layer, the semiconductor material layer, the oxide insulating layer and part the support lining
Bottom, is served as a contrast with removing part first hard mask layer, the semiconductor material layer, the oxide insulating layer and the support
Bottom, forms the stairstepping substrate with high area and low area；
Clearance wall is formed on the side wall in the high area, to protect the support substrate；
In low area's Epitaxial growth semiconductor material layer, then peel off remaining first hard mask layer and planarize,
So that the low area is concordant with the high area, mixed substrates are formed；
The second hard mask layer is formed in the mixed substrates；
The high area and the low area are etched, the high area is etched to the oxide insulating layer, to form the first fin, etching
Below the low area to the oxide insulating layer, to form second fins different from first fin height；
Clearance wall is formed on the side wall of first fin and second fin, to protect first fin and described
Two fins；
Etching removes the support substrate in the part low area, to expose the support substrate of the second fin bottom；
The support substrate of the second fin bottom is aoxidized, to form oxide, the dielectric layer of second fin is used as；
The clearance wall on the side wall of first fin and second fin is peeled off, to form highly different fins.
2. according to the method described in claim 1, it is characterised in that the upper table in the etching low area to the oxide insulating layer
Below face, to form second fins different from first fin height.
3. according to the method described in claim 1, it is characterised in that on the side wall of first fin and second fin
Form conformal clearance wall.
4. according to the method described in claim 1, it is characterised in that first hard mask layer is nitride layer.
5. method according to claim 4, it is characterised in that first hard mask layer is SiN layer.
6. according to the method described in claim 1, it is characterised in that second hard mask layer is SiON layers, BN layers or SiCN
Layer.
7. according to the method described in claim 1, it is characterised in that the patterning method is on first hard mask layer
The mask of patterning is formed, reactive ion etching is then carried out.
8. according to the method described in claim 1, it is characterised in that the method that clearance wall is formed on the side wall in the high area
For：
In the high area and low area's deposition spacer material floor, overall etch is then carried out, with the side wall in the high area
Form clearance wall.
9. according to the method described in claim 1, it is characterised in that in low area's Epitaxial growth semiconductor material layer be Si
Material layer.
10. according to the method described in claim 1, it is characterised in that from high area and the low area described in reactive ion etching,
To form first fin and second fin.
11. according to the method described in claim 1, it is characterised in that remove the part low area from reactive ion etching
Support substrate, to expose the support substrate of the second fin bottom.
12. according to the method described in claim 1, it is characterised in that the support substrate and the semiconductor material layer are Si
Layer.
13. the semiconductor devices that a kind of one of claim 1 to 12 methods described is prepared.
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| CN102024743A (en) * | 2009-09-18 | 2011-04-20 | 格罗方德半导体公司 | Semiconductor structures and methods for forming isolation between fin structures of finfet devices |
| CN102468121A (en) * | 2010-10-29 | 2012-05-23 | 中国科学院微电子研究所 | Preparation method for fin |
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| JP2008227026A (en) * | 2007-03-12 | 2008-09-25 | Toshiba Corp | Manufacturing method of semiconductor device |
| CN102651305B (en) * | 2011-02-25 | 2015-09-30 | 中国科学院微电子研究所 | A kind of preparation method of Ω shape fin |
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| CN102024743A (en) * | 2009-09-18 | 2011-04-20 | 格罗方德半导体公司 | Semiconductor structures and methods for forming isolation between fin structures of finfet devices |
| CN102468121A (en) * | 2010-10-29 | 2012-05-23 | 中国科学院微电子研究所 | Preparation method for fin |
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