CN102468121A - Preparation method for fin - Google Patents
Preparation method for fin Download PDFInfo
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- CN102468121A CN102468121A CN201010531980XA CN201010531980A CN102468121A CN 102468121 A CN102468121 A CN 102468121A CN 201010531980X A CN201010531980X A CN 201010531980XA CN 201010531980 A CN201010531980 A CN 201010531980A CN 102468121 A CN102468121 A CN 102468121A
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- fin
- groove
- semiconductor substrate
- side wall
- etching
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Abstract
The invention discloses a preparation method for a fin. The preparation method for the fin comprises the following steps of: forming a dielectric layer on a semiconductor substrate; etching the dielectric layer so as to embed into the semiconductor substrate to form at least two grooves and forming the fin between the grooves; forming a side wall on the side wall of the fin; forming an isolating oxidation layer below the fin and the grooves; and removing the side wall and the dielectric layer from the fin. Compared with a complementary metal oxide semiconductor (CMOS) planar technology, the method adopts the traditional directrix plane-based top-down technology, has high compatibility and is easy to integrate.
Description
Technical field
The invention belongs to technical field of semiconductors, relate in particular to a kind of preparation method of fin.
Background technology
Along with IC industry continues to advance according to the Moore law, the size of cmos device continues to dwindle.The plane body silicon CMOS structure device that continues to dwindle has run into stern challenge, such as: leakage current is sewed in serious short-channel effect (SCE), source, leakage causes potential barrier and reduces effect (DIBL) etc.In order to overcome above problem, various new construction devices arise at the historic moment, the grid structure of device from initial single grid develop into double grid (FinFET, fin transistor), multiple-grid up to surround fully raceway groove around the grid structure.Be illustrated in figure 1 as the structural representation of existing SOI double grid (FinFET) and multi-gate structure device, the left side is depicted as the double-gate structure transistor among the figure, and the right side is depicted as the multi-gate structure transistor.The grid-control ability constantly strengthens along with the increasing of number of grid with the ability that suppresses short-channel effect.But consider the difficulty and the cost of device actual fabrication, double grid and multi-gate structure device become the device architecture of most possible acquisition large-scale application, become the focus of research in the world.
Mainly adopt the SOI substrate to prepare double grid and multi-gate structure device at present in the world.Adopt the SOI substrate to prepare the new construction device following advantage is arranged: because there is natural BOX oxide layer in the SOI substrate, be easy to realize the isolation between the device latch-up of having avoided the body silicon substrate to exist; Preparation technology is simple; Be easy to suppress the parasitic transistor of bottom; Parasitic capacitance is little; Speed is high; Antiradiation effect is good.But adopt the SOI substrate to prepare the multi-gate structure device and also have problems; For example: the SOI substrate exists self-heating effect and floater effect; Need complicated source to leak engineering in the mill and omit living resistance with the reduction source, in general the SOI substrate is more many than costing an arm and a leg of common aspect silicon substrate.
Because the semiconductor fabrication process of main flow remains and adopts the body silicon substrate at present, how to realize on the body silicon substrate that therefore the new construction preparation of devices becomes the focus of a research.For double grid and multi-gate structure device; In order device to be prepared on the body silicon substrate; The problem that at first will consider is the fin channel structure of fabricate devices core on the body silicon substrate how, and this development for the large-scale promotion of new construction device and application and semiconductor industry is significant.
Summary of the invention
The object of the invention be to provide a kind of new, be easy to integrated, good with the planar CMOS processing compatibility preparation method that can on the body silicon substrate, realize preparing fin channel structure in double grid (FinFET) and the multiple-grid new construction device.
To achieve these goals, key step of the present invention comprises: on Semiconductor substrate, form dielectric layer; The said dielectric layer of etching forms at least two grooves to embed said Semiconductor substrate, forms fin between the said groove; Sidewall at said fin forms side wall; Below said fin and groove, form isolating oxide layer; Remove said side wall and the dielectric layer above the said fin.
Preferably, the step of said formation dielectric layer can comprise: on said Semiconductor substrate, form first resilient coating; On said first resilient coating, form first protective layer.Wherein, said first resilient coating comprises SiO
2Or TEOS, said first protective layer comprises Si
3N
4Or SiN.
Preferably, the width of said fin is 10-60nm.
Preferably, said sidewall at the said fin step that forms side wall can comprise: form second resilient coating; On said second resilient coating, form second protective layer; Said second resilient coating of etching and said second protective layer are to form side wall.
Preferably, form can step comprising of isolating oxide layer in the said Semiconductor substrate below said fin and groove: further the said groove of etching is so that said groove further extends in the said Semiconductor substrate, and the part that said groove extends increases; The said Semiconductor substrate of dry-oxygen oxidation is to form isolating oxide layer in said groove.Wherein, the method for the said groove of said further etching preferably adopts isotropic methods.Wherein, the thickness of said isolating oxide layer is preferably 50-300nm.
Preferably, said Semiconductor substrate is the body silicon substrate.
Can find out that from technique scheme the present invention has following beneficial effect:
1, this method for preparing the fin channel structure provided by the invention has realized the preparation of fin channel structure on the body silicon substrate, helps being implemented in preparing double grid (FinFET) and multi-gate structure device on the body silicon substrate;
2, this method for preparing the fin channel structure provided by the invention, preparation technology's simple possible, be easy to integrated, good with the planar CMOS processing compatibility;
3, this method for preparing the fin channel structure provided by the invention, bottom adopt oxide layer to form isolation structure, help suppressing the bottom parasitic transistor, eliminate the leakage current passage of bottom, improve the performance of device.
Description of drawings
With reference to the description of accompanying drawing to the embodiment of the invention, above-mentioned and other purposes of the present invention, feature and advantage will be more clear through following, in the accompanying drawings:
Fig. 1 shows the structural representation of SOI double grid (FinFET) and multi-gate structure device;
Fig. 2-8 shows each corresponding section of structure in the flow process that method according to the embodiment of the invention prepares fin structure.
Description of reference numerals:
201, the Si substrate; 202, STI isolates; 203, buffer Si O
2Oxide layer; 204, Si
3N
4Dielectric layer; 205, groove structure; 206, buffer Si O
2Oxide layer; 207, the Si of deposit
3N
4Dielectric layer; 208, the bottom portion of groove isolating oxide layer; 209, fin.
Should be noted in the discussion above that this Figure of description is not proportionally to draw, and be merely schematic purpose, therefore, should not be understood that any limitation and restriction the scope of the invention.In the accompanying drawings, similar part is with similar drawing reference numeral sign.
Embodiment
Below, through the specific embodiment shown in the accompanying drawing the present invention is described.But should be appreciated that these descriptions are exemplary, and do not really want to limit scope of the present invention.In addition, in following explanation, omitted to the description of known configurations, to avoid unnecessarily obscuring notion of the present invention with technology.
Layer structural representation according to the embodiment of the invention shown in the drawings.These figure draw in proportion, wherein for purpose clearly, have amplified some details, and possibly omit some details.The shape of the various zones shown in the figure, layer and the relative size between them, position relation only are exemplary; Maybe be because manufacturing tolerance or technical limitations and deviation to some extent in the reality, and those skilled in the art according to reality required can design in addition have difformity, the regions/layers of size, relative position.
Fig. 2～8 show in detail the corresponding section of structure of each step for preparing fin structure according to the embodiment of the invention.Below, will come each step according to the embodiment of the invention is specified with reference to these accompanying drawings.
At first, on Semiconductor substrate 201, form dielectric layer with reference to figure 2.Particularly, Semiconductor substrate can be a backing material commonly used in the field of semiconductor manufacture, for embodiments of the invention, preferably adopts body Si substrate.Can comprise isolation structure 202 in the said substrate 201, for example shallow trench isolation from (STI, ShallowTrenchIsolation).Said dielectric layer preferably includes first resilient coating 203 and first protective layer 204.Said first resilient coating 203 can comprise: SiO
2, TEOS or other dielectric materials, be preferably SiO in an embodiment of the present invention
2, can form through the heat growth, thickness is about 15-20nm, and this first resilient coating 203 can reduce the stress between said first protective layer 204 and the substrate 201, improves substrate performance.Said first protective layer 204 can comprise SiN, Si
3N
4Or other dielectric materials, be preferably Si in an embodiment of the present invention
3N
4, can pass through chemical vapor deposition (CVD) and form, thickness is about 40-60nm, in follow-up etching and oxidizing process, can protect the fin of follow-up formation effectively.
Then, as shown in Figure 3, said substrate 201 is carried out etching form at least two grooves 205 in the Semiconductor substrate 201 to embed.Two grooves only are shown among the figure, and for the person of ordinary skill of the art, can know to have many arbitrarily grooves.The method that etching forms said groove 205 for example can be: adopt electron beam exposure positive corrosion-resisting agent and reactive ion etching to form that steep width is about 400nm*400nm, spacing is two adjacent grooves 205 of 10-60nm.The shape of groove is an example, and the present invention does not limit this.Between groove, formed fin 209, said fin 209 is also referred to as silicon island (SiliconIsland), and width can be selected according to actual needs, for example 10-60nm.
Then, like Fig. 4, shown in Figure 5, form side wall in the both sides of said fin 209.The structure of said side wall can be a single or multiple lift, can be the side wall of " D " type side wall or " I " type side wall or other shapes, and the present invention does not limit this.Being formed with of side wall is beneficial to protection fin 209 and in follow-up etching and oxidizing process, is not destroyed.At first, as shown in Figure 4, on whole semiconductor structure, cover one deck second resilient coating 206, for example can be: SiO
2, TEOS, be preferably SiO in an embodiment of the present invention
2, can pass through chemical vapor deposition, heat growth or additive method and form, thickness is about 20-60nm.Then on said second resilient coating, form second protective layer 207, for example can comprise: SiN, Si
3N
4, embodiments of the invention are preferably Si
3N
4, for example can form through chemical vapor deposition or additive method, thickness is about 20-60nm.As shown in Figure 5, at last said second resilient coating and second dielectric layer are carried out etching, (RIE ReactiveIonEtch), thereby has formed double- deck side wall 206 and 207 for example to adopt reactive ion etching.
Then, with reference to figure 6, Fig. 7, form isolating oxide layer 208 in the substrate 201 below said fin 209 and groove 205.Particularly, at first as shown in Figure 6, further the said groove 205 of etching is so that said groove 205 further extends in the said Semiconductor substrate 201, and the part that said groove 205 extends increases, and has so just formed groove 205 '.Further the method for etched recesses 205 can adopt isotropic dry method or wet etching; Preferably can adopt the said groove of the further etching of dry method to enter into the degree of depth of substrate 201 80-120nm of place, fin 209 bottoms under, perhaps also can adopt the method for wet etching to carry out etching.Should all do not eroded with the silicon substrate that guarantees fin bottom in the corrosion process according to the speed and the time of the THICKNESS CONTROL wet etching of said fin 209 in the etching process.Adopt the said Semiconductor substrate 201 of dry-oxygen oxidation in said groove 205 ', to form isolating oxide layer 208 then.This isolating oxide layer can play buffer action, eliminates the leakage current path between fin and the substrate.The thickness of said isolating oxide layer 208 can be 50-300nm.The thickness of said isolating oxide layer 208 can be optimized and select according to actual needs; For example can decide according to the degree of depth of the groove that is positioned at remaining backing material in said fin 209 belows and isotropic etch behind the isotropic etch, fully oxidized with the remaining backing material 201 of fin 209 bottoms behind the assurance isolation oxidation to form good isolation.In addition, the thickness of isolating oxide layer can not be too thick and since in the oxidizing process volume of oxide layer can increase cause oxide layer upwards structures such as growth and then fin above the extruding and side wall cause bigger stress and distortion.
As shown in Figure 8, at last first resilient coating 203 and first protective layer 204 of first side wall 206, second side wall 207 and the top of fin 209 both sides are removed.Preferably, adopt the method for wet etching that the dielectric layer around the fin 209 is removed to form fin 209, the solution of corrosion can be SPA (H
3PO
4).
So just formed the fin structure that obtains according to embodiments of the invention.In structure shown in Figure 8, the Semiconductor substrate of below, fin bottom adopts oxide layer to form isolation structure, helps suppressing the bottom parasitic transistor, eliminates the leakage current passage of bottom, improves the performance of device.
In addition, embodiments of the invention can have been realized the preparation of fin channel structure on the body silicon substrate, help being implemented in preparing double grid (FinFET) and multi-gate structure device on the body silicon substrate.This method adopts traditional top-down technology based on directrix plane, and preparation technology's simple possible has favorable compatibility with the CMOS planar technique, and is easy to integrated.
In above description, do not make detailed explanation for ins and outs such as the composition of each layer, etchings.Can be but it will be appreciated by those skilled in the art that through various means of the prior art, form layer, zone of required form etc.In addition, in order to form same structure, those skilled in the art can also design and the not identical method of the method for above description.
Abovely the present invention has been given explanation with reference to embodiments of the invention.But these embodiment only are for illustrative purposes, and are not in order to limit scope of the present invention.Scope of the present invention is limited accompanying claims and equivalent thereof.Do not depart from the scope of the present invention, those skilled in the art can make multiple replacement and modification, and these replacements and modification all should drop within the scope of the present invention.
Claims (9)
1. the preparation method of a fin comprises:
On Semiconductor substrate, form dielectric layer;
The said dielectric layer of etching forms at least two grooves to embed said Semiconductor substrate, forms fin between the said groove;
Sidewall at said fin forms side wall;
Below said fin and groove, form isolating oxide layer;
Remove said side wall and the dielectric layer above the said fin.
2. method according to claim 1, wherein, the step of said formation dielectric layer comprises:
On said Semiconductor substrate, form first resilient coating;
On said first resilient coating, form first protective layer.
3. method according to claim 2, wherein, said first resilient coating comprises SiO
2Or TEOS, said first protective layer comprises Si
3N
4Or SiN.
4. method according to claim 1, wherein, the width of said fin is 10-60nm.
5. method according to claim 1, wherein, the step that said sidewall at said fin forms side wall comprises:
Form second resilient coating;
On said second resilient coating, form second protective layer;
Said second resilient coating of etching and said second protective layer are to form side wall.
6. method according to claim 1, wherein, the step that forms isolating oxide layer in the said Semiconductor substrate below said fin and groove comprises:
Further the said groove of etching is so that said groove further extends in the said Semiconductor substrate, and the part that said groove extends increases;
The said Semiconductor substrate of dry-oxygen oxidation is to form isolating oxide layer in said groove.
7. method according to claim 6, wherein, the said groove of said further etching comprises:
Adopt the said groove of the further etching of isotropic methods.
8. method according to claim 6, wherein, the thickness of said isolating oxide layer is 50-300nm.
9. according to each described method in the claim 1 to 8, wherein, said Semiconductor substrate is the body silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010531980XA CN102468121A (en) | 2010-10-29 | 2010-10-29 | Preparation method for fin |
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|---|---|---|---|
| CN201010531980XA CN102468121A (en) | 2010-10-29 | 2010-10-29 | Preparation method for fin |
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|---|---|
| CN102468121A true CN102468121A (en) | 2012-05-23 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103794497A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for preparing same |
| WO2015000203A1 (en) * | 2013-07-03 | 2015-01-08 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method therefor |
| TWI553858B (en) * | 2012-07-11 | 2016-10-11 | 聯華電子股份有限公司 | Multi-gate mosfet and process thereof |
| CN110752156A (en) * | 2019-10-28 | 2020-02-04 | 中国科学院微电子研究所 | Preparation method of fin-shaped structure and preparation method of semiconductor device |
| EP4310898A1 (en) * | 2022-07-21 | 2024-01-24 | Invention And Collaboration Laboratory Pte. Ltd. | Bulk semiconductor substrate with fully isolated single-crystalline silicon islands and the method for forming the same |
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2010
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| US20100276739A1 (en) * | 2006-04-14 | 2010-11-04 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating the same |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI553858B (en) * | 2012-07-11 | 2016-10-11 | 聯華電子股份有限公司 | Multi-gate mosfet and process thereof |
| CN103794497A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for preparing same |
| CN103794497B (en) * | 2012-10-29 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| WO2015000203A1 (en) * | 2013-07-03 | 2015-01-08 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method therefor |
| CN110752156A (en) * | 2019-10-28 | 2020-02-04 | 中国科学院微电子研究所 | Preparation method of fin-shaped structure and preparation method of semiconductor device |
| EP4310898A1 (en) * | 2022-07-21 | 2024-01-24 | Invention And Collaboration Laboratory Pte. Ltd. | Bulk semiconductor substrate with fully isolated single-crystalline silicon islands and the method for forming the same |
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Application publication date: 20120523 |