CN102468161A - Preparation method of field effect transistor - Google Patents
Preparation method of field effect transistor Download PDFInfo
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- CN102468161A CN102468161A CN2010105319829A CN201010531982A CN102468161A CN 102468161 A CN102468161 A CN 102468161A CN 2010105319829 A CN2010105319829 A CN 2010105319829A CN 201010531982 A CN201010531982 A CN 201010531982A CN 102468161 A CN102468161 A CN 102468161A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 37
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Abstract
The application discloses a manufacturing method of a field effect transistor, which comprises the following steps: forming a fin on a semiconductor substrate; forming a gate stack structure on the top and the side of the fin; forming source/drain structures in the fins on two sides of the gate stack structure; and the semiconductor substrate below the fins comprises an isolation dielectric layer. The field effect transistor is prepared on the bulk silicon substrate, the self-heating effect and the floating body effect of the SOI device are eliminated, the cost is lower, the traditional quasi-plane-based top-down process is adopted to realize good compatibility with the CMOS planar process, the integration is easy, the short channel effect is favorably inhibited, and the development of the sizes of the MOSFETs towards the small size direction is promoted.
Description
Technical field
The invention belongs to technical field of semiconductors, relate in particular to a kind of preparation method of body silicon multi gate fet.
Background technology
Along with IC industry continues to advance according to the Moore law, the characteristic size of cmos device continues to dwindle.Plane body silicon CMOS structure device has run into stern challenge, such as: leakage current is sewed in serious short-channel effect (SCE), source, leakage causes potential barrier and reduces effect (DIBL) etc.In order to overcome above problem, various new construction devices arise at the historic moment, the grid structure of device from initial single grid develop into double grid (FinFET, fin transistor), multiple-grid up to surround fully raceway groove around the grid structure.The grid-control ability constantly strengthens along with the increasing of number of grid with the ability that suppresses short-channel effect.But consider the difficulty and the cost of device actual fabrication, the multi-gate structure device becomes the device architecture of most possible acquisition large-scale application, becomes the focus of research in the world.
Mainly adopt the SOI substrate to prepare the multi-gate structure device at present in the world.Adopt the SOI substrate to prepare the new construction device following advantage is arranged: because there is natural BOX oxide layer in the SOI substrate, be easy to realize the isolation between the device latch-up of having avoided the body silicon substrate to exist; Preparation technology is simple; Be easy to suppress the parasitic transistor of bottom; Parasitic capacitance is little; Speed is high; Antiradiation effect is good.But adopt the SOI substrate to prepare the multi-gate structure device and also have problems; For example: the SOI substrate exists self-heating effect and floater effect; Need complicated source to leak engineering in the mill and omit living resistance with the reduction source, in general the SOI substrate is more many than costing an arm and a leg of common aspect silicon substrate.
Because the semiconductor fabrication process of main flow remains and adopts the body silicon substrate at present; Therefore how realize on the body silicon substrate that the multi-gate structure preparation of devices becomes the focus of a research, this development for the application of multi-gate structure device and semiconductor industry is significant.
Summary of the invention
The object of the invention be to provide a kind of new, be easy to integrated, with the preparation method of the good body silicon multi gate fet of planar CMOS processing compatibility.
To achieve these goals, key step of the present invention comprises: on Semiconductor substrate, form fin; Top and side at said fin form the grid stacked structure; Formation source/drain structure in the fin of said grid stacked structure both sides; Wherein, comprise the spacer medium layer in the Semiconductor substrate below the said fin.
Preferably, said step at formation fin on the Semiconductor substrate comprises: on Semiconductor substrate, form dielectric layer; The said dielectric layer of etching forms at least two grooves to embed said Semiconductor substrate, forms fin between the said groove; Sidewall at said fin forms side wall; Below said fin and groove, form the spacer medium layer; Remove said side wall and the dielectric layer above the said fin.
Preferably, the step of said formation dielectric layer can comprise: on said Semiconductor substrate, form first resilient coating; On said first resilient coating, form first protective layer.Wherein, said first resilient coating comprises SiO
2Or TEOS, said first protective layer comprises Si
3N
4Or SiN.
Preferably, the width of said fin is 10-60nm.
Preferably, said sidewall at the said fin step that forms side wall can comprise: form second resilient coating; On said second resilient coating, form second protective layer; Said second resilient coating of etching and said second protective layer are to form side wall.
Preferably; Said spacer medium layer comprises isolating oxide layer; Then form can step comprising of spacer medium layer in the Semiconductor substrate below said fin and groove: further the said groove of etching is so that said groove further extends in the said Semiconductor substrate, and the part that said groove extends increases; The said Semiconductor substrate of dry-oxygen oxidation is to form isolating oxide layer in said groove.Wherein, the method for the said groove of said further etching preferably adopts isotropic methods.Wherein, the thickness of said isolating oxide layer is preferably 50-300nm.
In a preferred embodiment of the invention, said in the fin of said grid stacked structure both sides before formation source/drain structure, said method further comprises: carry out the inclination angle ion and inject, with formation source/drain extension region in said fin.Perhaps can also comprise: carry out the inclination angle ion and inject, in said fin, to form the halo injection region.
In a preferred embodiment of the invention, said Semiconductor substrate is the body silicon substrate.
Can find out that from technique scheme the present invention has following beneficial effect:
1, this method for preparing the multi-gate structure device provided by the invention has realized the multi-gate structure preparation of devices on the body silicon substrate, has overcome self-heating effect and floater effect that the SOI substrate exists, has reduced preparation cost;
2, this method for preparing the multi-gate structure device provided by the invention, preparation technology's simple possible, be easy to integrated, good with the planar CMOS processing compatibility;
3, this method for preparing the multi-gate structure device provided by the invention can avoid adopting SOI device institute employing source to leak the serial resistance that method such as selective epitaxial comes the reduction source to leak, and helps further reducing the dependence to equipment, is easy to realize.
Description of drawings
With reference to the description of accompanying drawing to the embodiment of the invention, above-mentioned and other purposes of the present invention, feature and advantage will be more clear through following, in the accompanying drawings:
Each corresponding section of structure during Fig. 1-10D shows in the flow process that method according to the embodiment of the invention prepares body silicon multi gate fet;
Figure 11 is the output characteristic curve and the transfer characteristic curve of the body silicon multi gate fet of employing this method preparation.
Description of reference numerals:
101, the Si substrate; 102, trap; 103, STI isolates; 104, buffer Si O
2Oxide layer; 105, Si
3N
4Dielectric layer; 106, groove structure; 107, fin; 108, buffer Si O
2Oxide layer; 109, the Si of deposit
3N
4Dielectric layer; 110, the bottom portion of groove isolating oxide layer; 111, gate dielectric layer; 112, gate electrode.
Should be noted in the discussion above that this Figure of description is not proportionally to draw, and be merely schematic purpose, therefore, should not be understood that any limitation and restriction the scope of the invention.In the accompanying drawings, similar part is with similar drawing reference numeral sign.
Embodiment
Below, through the specific embodiment shown in the accompanying drawing the present invention is described.But should be appreciated that these descriptions are exemplary, and do not really want to limit scope of the present invention.In addition, in following explanation, omitted to the description of known configurations, to avoid unnecessarily obscuring notion of the present invention with technology.
Layer structural representation according to the embodiment of the invention shown in the drawings.These figure draw in proportion, wherein for purpose clearly, have amplified some details, and possibly omit some details.The shape of the various zones shown in the figure, layer and the relative size between them, position relation only are exemplary; Maybe be because manufacturing tolerance or technical limitations and deviation to some extent in the reality, and those skilled in the art according to reality required can design in addition have difformity, the regions/layers of size, relative position.
To be example below, the present invention will be elaborated with preparation body silicon multi gate fet.Fig. 1～10D shows in detail according to the embodiment of the invention and prepares the corresponding section of structure of each step of body silicon multi gate fet.Below, will come each step according to the embodiment of the invention is specified with reference to these accompanying drawings.
At first, on Semiconductor substrate 101, form trap 102 with reference to figure 1.Particularly, said Semiconductor substrate 101 can be a backing material commonly used in the field of semiconductor manufacture, can carry out p type or n type and mix, and can comprise epitaxial loayer.For embodiments of the invention, preferably adopt body Si substrate.Can comprise isolation structure 103 in the said substrate 101, for example shallow trench isolation from (STI, ShallowTrenchIsolation).
Then as shown in Figure 2, on Semiconductor substrate 101, form dielectric layer.Said dielectric layer preferably includes first resilient coating 104 and first protective layer 105.Said first resilient coating 104 can comprise: SiO
2, TEOS or other dielectric materials, be preferably SiO in an embodiment of the present invention
2, can form through the heat growth, thickness is about 15-20nm, and this first resilient coating 104 can reduce the stress between said first protective layer 105 and the substrate 101, improves substrate performance.Said first protective layer 105 can comprise SiN, Si
3N
4Or other dielectric materials, be preferably Si in an embodiment of the present invention
3N
4, can pass through chemical vapor deposition (CVD) and form, thickness is about 40-60nm, in follow-up etching and oxidizing process, can protect the fin of follow-up formation effectively.
Fig. 3 A shows along the sketch map on Semiconductor substrate 101 surfaces, and Fig. 3 B is the cutaway view of AA ' direction among Fig. 3 A.Shown in Fig. 3 A, 3B, said substrate 101 is carried out etching form at least two grooves 106 in the Semiconductor substrate 101 to embed.Two grooves only are shown among the figure, and for the person of ordinary skill of the art, can know to have many arbitrarily grooves.The method that etching forms said groove 106 for example can be: adopt electron beam exposure positive corrosion-resisting agent and reactive ion etching to form that steep width is about 400nm*400nm, spacing is two adjacent grooves 106 of 10-60nm.The shape of groove is an example, and the present invention does not limit this.Between groove, formed fin 107, said fin 107 is also referred to as silicon island (SiliconIsland), and the width of fin can be selected according to actual needs, for example 10-60nm.
Fig. 5 A is the sketch map of structure after forming side wall of direction shown in Fig. 3 A, and Fig. 5 B is the cutaway view along AA ' direction among Fig. 5 A.Shown in Fig. 4, Fig. 5 A and Fig. 5 B, form side wall in the both sides of said fin 107.The structure of said side wall can be a single or multiple lift, can be the side wall of " D " type side wall or " I " type side wall or other shapes, and the present invention does not limit this.Being formed with of side wall is beneficial to protection fin 107 and in follow-up etching and oxidizing process, is not destroyed.At first, as shown in Figure 4, on whole semiconductor structure, cover second resilient coating 108, for example can be: SiO
2, TEOS or other dielectric materials, be preferably SiO in an embodiment of the present invention
2, can pass through chemical vapor deposition, heat growth or additive method and form, thickness is about 20-60nm.Then on said second resilient coating, form second protective layer 109, for example can comprise: SiN, Si
3N
4Or other dielectric materials, embodiments of the invention are preferably Si
3N
4, for example can form through chemical vapor deposition or additive method, thickness is about 20-60nm.As shown in Figure 5, at last said second resilient coating and second dielectric layer are carried out etching, (RIE ReactiveIonEtch), thereby has formed double- deck side wall 108 and 109 for example to adopt reactive ion etching.
Then, with reference to figure 6, Fig. 7, form the spacer medium layer in the substrate 101 below said fin 107 and groove 106, the present invention is preferably isolating oxide layer 110.Particularly, at first as shown in Figure 6, further the said groove 106 of etching is so that said groove 106 further extends in the said Semiconductor substrate 101, and the part that said groove 106 extends increases, and has so just formed groove 106 '.Groove 106 ' is positioned at the following width in said fin 107 bottoms greater than top width.Further the method for etched recesses 106 can adopt isotropic dry method or wet etching; Preferably can adopt the said groove of the further etching of dry method to enter into the about 80-120nm of substrate 101 degree of depth of place, fin 107 bottoms under, perhaps also can adopt the method for wet etching to carry out etching.Should all do not eroded with the silicon substrate that guarantees fin bottom in the corrosion process according to the speed and the time of the THICKNESS CONTROL wet etching of said fin 107 in the etching process.Adopt the said Semiconductor substrate 101 of dry-oxygen oxidation in said groove 106 ', to form isolating oxide layer 110 then.This isolating oxide layer can play buffer action, eliminates the leakage current path between fin and the substrate.The thickness of said isolating oxide layer 110 can be 50-300nm.The thickness of said isolating oxide layer 110 can be optimized and select according to actual needs; For example can decide according to the degree of depth of the groove that is positioned at remaining backing material in said fin 107 belows and isotropic etch behind the isotropic etch, fully oxidized with the remaining backing material 102 of fin 107 bottoms behind the assurance isolation oxidation to form good isolation.In addition, the thickness of isolating oxide layer can not be too thick and since in the oxidizing process volume of oxide layer can increase cause oxide layer upwards structures such as growth and then fin above the extruding and side wall cause bigger stress and distortion.
Then, as shown in Figure 8, first resilient coating 104 and first protective layer 105 of first side wall 108, second side wall 109 and the top of fin 107 both sides are removed.Preferably, adopt the method for wet etching that the dielectric layer around the fin 107 is removed to form fin 107, the solution of corrosion can be SPA (H
3PO
4).
So just formed the fin structure that obtains according to embodiments of the invention.In structure shown in Figure 8, the Semiconductor substrate of below, fin bottom adopts oxide layer to form isolation structure, helps suppressing the bottom parasitic transistor, eliminates the leakage current passage of bottom, improves the performance of device.
Figure 10 A is for to overlook the sketch map of direction along semiconductor substrate surface, and Figure 10 B is the cutaway view along AA ' direction among Figure 10 A, and Figure 10 C is the cutaway view along BB ' direction among Figure 10 A, and Figure 10 D is the cutaway view along CC ' direction among the 10A.With reference to figure 9, Figure 10 A, Figure 10 B, Figure 10 C and Figure 10 D, on entire substrate, form gate dielectric layer and electrode material, etching forms the gate electrode structure then.Said gate dielectric layer material can be common gate dielectric material, for example SiO
2, or other high K medium material, for example SiON and HfAlON, HfTaON, HfSiON, Al
2O
3Deng, preferred SiO in the present invention ground embodiment
2, can pass through methods such as low-pressure chemical vapor deposition, physical vapor deposition, metal organic chemical vapor deposition or atomic layer deposition and form, the equivalent oxide thickness of gate medium is 5 to 100
Said gate material can be refractory metal W, Ti, Ta; Mo and metal nitride, TiN for example, TaN; HfN, MoN etc. or other materials, gate material can adopt low-pressure chemical vapor phase deposition; Metal organic chemical vapor deposition, atomic layer deposition or additive method form, and thickness is chosen as 300 to 3000
Alternatively, after forming the grid stacked structure, said method further comprises: carry out the inclination angle ion and inject, with formation source/drain extension region in said fin; Or carry out the inclination angle ion and inject, in said fin, to form the halo injection region.
Then, can on the sidewall that grid pile up, form the grid side wall.The formation of grid side wall can be repeated no more with reference to routine techniques here.
At last, in grid pile up the Semiconductor substrate of both sides, carry out ion and inject formation source/drain region.
Figure 11 is the output characteristic curve and the transfer characteristic curve of the body silicon multi gate fet of employing this method preparation.From curve, can find out, adopt the device of this method preparation to have characteristic preferably.Especially the characteristic of P pipe can be good at the short-channel effect (SCE) of suppression device.
In addition, embodiments of the invention can have been realized the multi-gate structure preparation of devices on the body silicon substrate.This method adopts traditional top-down technology based on directrix plane, and preparation technology's simple possible has favorable compatibility with the CMOS planar technique, and is easy to integrated.
In above description, do not make detailed explanation for ins and outs such as the composition of each layer, etchings.Can be but it will be appreciated by those skilled in the art that through various means of the prior art, form layer, zone of required form etc.In addition, in order to form same structure, those skilled in the art can also design and the not identical method of the method for above description.
Abovely the present invention has been given explanation with reference to embodiments of the invention.But these embodiment only are for illustrative purposes, and are not in order to limit scope of the present invention.Scope of the present invention is limited accompanying claims and equivalent thereof.Do not depart from the scope of the present invention, those skilled in the art can make multiple replacement and modification, and these replacements and modification all should drop within the scope of the present invention.
Claims (11)
1. the preparation method of a field-effect transistor comprises:
On Semiconductor substrate, form fin;
Top and side at said fin form the grid stacked structure;
Formation source/drain structure in the fin of said grid stacked structure both sides;
Wherein, comprise the spacer medium layer in the Semiconductor substrate below the said fin.
2. method according to claim 1, wherein, the step that on Semiconductor substrate, forms fin comprises:
On Semiconductor substrate, form dielectric layer;
The said dielectric layer of etching forms at least two grooves to embed said Semiconductor substrate, forms fin between the said groove;
Sidewall at said fin forms side wall;
Below said fin and groove, form the spacer medium layer;
Remove said side wall and the dielectric layer above the said fin.
3. method according to claim 2, wherein, the step of said formation dielectric layer comprises:
On said Semiconductor substrate, form first resilient coating;
On said first resilient coating, form first protective layer.
4. method according to claim 3, wherein, said first resilient coating comprises SiO
2Or TEOS, said first protective layer comprises Si
3N
4Or SiN.
5. method according to claim 2, wherein, the width of said fin is 10-60nm.
6. method according to claim 2, wherein, the step that said sidewall at said fin forms side wall comprises:
Form second resilient coating;
On said second resilient coating, form second protective layer;
Said second resilient coating of etching and said second protective layer are to form side wall.
7. method according to claim 2, wherein, said spacer medium layer comprises isolating oxide layer, the step that forms the spacer medium layer in the said Semiconductor substrate below said fin and groove comprises:
Further the said groove of etching is so that said groove further extends in the said Semiconductor substrate, and the part that said groove extends increases;
The said Semiconductor substrate of dry-oxygen oxidation is to form isolating oxide layer in said groove.
8. method according to claim 7, wherein, the said groove of said further etching comprises:
Adopt the said groove of the further etching of isotropic methods.
9. method according to claim 7, wherein, the thickness of said isolating oxide layer is 50-300nm.
10. method according to claim 1, before formation source/drain structure, said method further comprises in the fin of said grid stacked structure both sides:
Carry out the inclination angle ion and inject, with formation source/drain extension region in said fin; Or
Carry out the inclination angle ion and inject, in said fin, to form the halo injection region.
11. according to each described method in the claim 1 to 10, wherein, said Semiconductor substrate is the body silicon substrate.
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| CN103579295A (en) * | 2012-07-25 | 2014-02-12 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| WO2014036677A1 (en) * | 2012-09-10 | 2014-03-13 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method therefor |
| CN104134695A (en) * | 2014-07-15 | 2014-11-05 | 华为技术有限公司 | Tunneling field effect transistor and manufacturing method thereof |
| CN104392917A (en) * | 2014-11-17 | 2015-03-04 | 上海集成电路研发中心有限公司 | Method for forming totally-enclosed gate structure |
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