CN106601602B - For the method for the dual composition of autoregistration and the manufacturing method of semiconductor devices - Google Patents
For the method for the dual composition of autoregistration and the manufacturing method of semiconductor devices Download PDFInfo
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- CN106601602B CN106601602B CN201510661320.6A CN201510661320A CN106601602B CN 106601602 B CN106601602 B CN 106601602B CN 201510661320 A CN201510661320 A CN 201510661320A CN 106601602 B CN106601602 B CN 106601602B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
The present invention provides the manufacturing method of a kind of method for the dual composition of autoregistration and semiconductor devices, is related to technical field of semiconductors.This method comprises: providing semiconductor substrate, core model material layer is formed on the semiconductor substrate；The core model material layer is handled so that it is densified；The graphical core model material layer, to form core model；Isotropic etching is carried out to the core model；Compensation layer is formed on the mandrel surface and side wall；Hardmask material is formed on the surface of the substrate and the surface of the core model and side wall；Etch-back is executed, to form the side wall being made of the hardmask material on the side wall of the core model；Remove the core model.It is of the invention for the method for the dual composition of autoregistration and the manufacturing method of semiconductor devices, can be without side-effects in the low frequency roughness of the dual composition core mould side wall of autoregistration, to improve the performance and yield for the semiconductor devices being subsequently formed.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of method for the dual composition of autoregistration and half
The manufacturing method of conductor device.
Background technique
As dimensions of semiconductor devices constantly reduces, photoetching critical size (CD), which moves closer to, has been even more than optical lithography
Physics limit, thus propose more acute challenge to semiconductor processing technology especially photoetching technique.And dual composition
Technology also arrives in due course, and basic thought is that final target pattern is formed by composition twice, to obtain single composition institute not
Attainable photolithography limitation.
Dual recompose-technique mainly includes following three: SADP (the dual composition of autoregistration), LELE (photoetching-etching-at present
Photoetching-etching) DP and LLE (photoetching-photoetching-etching) DP.In these three technologies, LELE DP technology and LLE DP technology by
In using photoresist twice, so the linearity to photoresist is very high, and therefore but also manufacturing cost improves, so that
Its application is limited to.And SADP technology is due to being only intended for single use photoresist, and can break through the physics limit of CD and make most
Small spacing is decreased to the half of CD, is therefore particularly suitable for manufacture CD in 32nm semiconductor devices below.
And based on core model (mandrel) and side wall (spacer) technique the dual patterning technique of autoregistration be possible to by
The minimum space half period of integrated circuit is pushed into smaller node, receives the extensive concern of semiconductor product industry recently, master
Wanting principle is: forming side wall (spacer) in preformed core model pattern two sides first, then removes core model pattern, and by side
Wall pattern is transferred in target material layer, to keep the number of patterns that can be formed in unit area double, i.e., between pattern most
Small spacing (pitch) can be decreased to the half of CD.
However, line width roughness has become a key of manufacturing process with the critical dimension reduction of integrated circuit
Problem is even more important for the formation of grid.Low frequency side wall roughness has been considered to will lead to the reduction of SRAM yield, this is
Because low frequency side wall roughness will lead to local bridge joint (local-bridging) when the critical size of integrated circuit is smaller,
Deteriorate and threshold voltage distributing deflection so as to cause subthreshold behavior.
In view of the foregoing, a kind of dual patterning process of improved autoregistration is needed, it is expected that this method can overcome tradition
The drawbacks described above of technique, and can be easy compatible with traditional cmos process.
Summary of the invention
In view of the deficiencies of the prior art, the present invention proposes a kind of method and semiconductor devices for the dual composition of autoregistration
Manufacturing method, the low frequency roughness of core model side wall can be improved in the dual composition of autoregistration and without side-effects, to improve
The performance and yield for the semiconductor devices being subsequently formed.
One embodiment of the present of invention provides a kind of method for the dual composition of autoregistration comprising: step S101 is mentioned
For semiconductor substrate, core model material layer is formed on the semiconductor substrate；Step S102, at the core model material layer
It manages so that it is densified；Step S103, the graphical core model material layer, to form core model；Step S104, to the core model into
Row isotropic etching；Step S105 forms compensation layer on the mandrel surface and side wall；Step S106, in the substrate
Surface and the core model surface and side wall on form hardmask material；Step S107 executes etch-back, described
The side wall being made of the hardmask material is formed on the side wall of core model；Step S108 removes the core model.
Further, the step S102 includes: step S1021, ion implanting is carried out to the core model material layer, to change
It is apt to the surface roughness of the core model material layer；Step S1022 handles the core model material using adaptive coupled plasma
Layer, to increase the hardness of the core model material layer.
Further, the core model material layer is amorphous silicon layer.
Further, in the step S104, the isotropic etching is carried out by chemical drying method etching.
Further, the step S103 includes: step S1031, forms sacrificial material layer in the core model material layer；
Step S1032, the graphical sacrificial material layer；Step S1033, using the patterned sacrificial material layer as mask etching institute
Core model layer is stated, it will be in pattern transfer to the core model material layer.
Further, the sacrificial material layer is amorphous carbon.
Another embodiment of the present invention provides a kind of manufacturing methods of semiconductor devices comprising: substrate is provided, in institute
It states and forms target material layer and core model material layer on substrate；Use the above-mentioned method shape for the dual composition of autoregistration of the present invention
At the first hard mask layer；Subsequent technique is executed as exposure mask using first hard mask layer.
Further, be formed between the target material layer and the core model material layer the second hardmask material,
At least one of etching stopping layer and boundary layer.
Further, the subsequent technique is etch process, ion implantation technology or selective epitaxial growth process.
It is of the invention for the method for the dual composition of autoregistration and the manufacturing method of semiconductor devices, passing through improves core model material
The consistency of material makes its densification, it is difficult to be oxidized, thus can change in subsequent isotropic etching by isotropic etching
Kind low frequency line width roughness, and by the material layer of compensation loss, it further increases critical size consistency and improves low frequency wire
Broad and rough rugosity, to improve the performance and yield for the semiconductor devices being subsequently formed.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows a kind of flow chart of the method according to an embodiment of the invention for the dual composition of autoregistration；
Fig. 2A~Fig. 2 G is to show in the method according to an embodiment of the invention for the dual composition of autoregistration respectively
The schematic cross sectional view of a step；
Fig. 3 shows a kind of flow chart of the manufacturing method of semiconductor devices according to an embodiment of the invention；
Fig. 4 A~Fig. 4 C shows showing for each step in the manufacturing method of an embodiment semiconductor devices according to the present invention
Meaning property sectional view.
Specific embodiment
Now, an exemplary embodiment of the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.
It should be understood that the element can directly connect when element arrives another element referred to as " connection " or " in conjunction with "
Another element is connect or be integrated to, or may exist intermediary element.Unlike, when element is referred to as " being directly connected to " or " straight
When another element is arrived in binding conjunction ", intermediary element is not present.In all the attached drawings, identical appended drawing reference is always shown identical
Element.As used herein, term "and/or" include one or more related listed items any combination and all groups
It closes.Should explain in an identical manner for describing the relationship between element or layer other words (for example, " ... between "
" between directly existing ... ", " with ... it is adjacent " and " with ... direct neighbor ", " ... on " and " on directly existing ... "
Deng).
Additionally, it should be understood that different to describe although term " first ", " second " etc. can be used herein
Element, component, regions, layers, and/or portions, but these elements, component, regions, layers, and/or portions should not be by these terms
Limitation.These terms are intended merely to an element, component, region, layer or part and another element, component, region, layer
Or part distinguishes.Therefore, discussed further below in the case where not departing from the introduction of an exemplary embodiment of the present invention
First element, component, region, layer or part can also be referred to as second element, component, region, layer or part.
For ease of description, spatially relative term can be used herein, as " ... under ", " ... on ",
" following ", " ... top ", " above " etc., for describing such as an elements or features and other elements shown in figure
Or the spatial relation of feature.It should be understood that spatially relative term is intended to comprising in addition to device is discribed in figure
Different direction in use or operation except orientation.For example, being described as if the device in attached drawing is squeezed " at it
Below his elements or features " or the element of " under other elements or feature " after will be positioned as " in other elements or spy
Sign top " or " on other elements or feature ".Thus, exemplary term " ... lower section " may include " ... on
Side " and " in ... lower section " two kinds of orientation.The device can also be positioned with other different modes (to be rotated by 90 ° or in its other party
Position), and respective explanations are made to spatial relative descriptor used herein above.
Term used herein above is not intended to restricted root according to of the invention exemplary merely to description specific embodiment
Embodiment.As used herein, unless the context clearly indicates otherwise, otherwise singular is also intended to include plural shape
Formula.Additionally, it should be understood that when the term " comprising " and/or " including " is used in this specification, indicating that there are institutes
Feature, entirety, step, operation, element and/or component are stated, but do not preclude the presence or addition of other one or more features, whole
Body, step, operation, element, component and/or their combination.
Here, the schematic cross sectional view referring to preferred embodiment (and intermediate structure) as exemplary embodiment describes
An exemplary embodiment of the present invention.In this way, it is expected that will appear the shape for example shown as caused by manufacturing technology and/or tolerance
The variation of shape.Therefore, exemplary embodiment should not be construed as limited to the concrete shape in the region being shown here, but also
It may include for example by the form variations caused by manufacturing.For example, be shown as the injection zone of rectangle can have at its edge
The change of gradient of rounding or curved feature and/or implantation concentration, and it is not only the binary from injection zone to non-implanted region
Variation.Equally, it will lead to by the buried regions that injection is formed in the region between the surface that the buried regions and injection pass through
There can be some injections.Therefore, the region shown by scheming is substantially schematical, their shape is not intended to show device
In each region true form, and be not intended to limitation an exemplary embodiment of the present invention range.
Unless otherwise defined, it is used herein above whole term (including technical terms and scientific terms) all have with
The normally understood meaning equivalent in meaning of those skilled in the art.It will be further understood that unless bright here
Determine justice, this kind of term of the term otherwise such as defined in common dictionary should be interpreted as having and they are in related fields
The consistent meaning of looking like in context, without being explained with ideal or too formal meaning.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
Embodiment one
It is described in detail next, with reference to Fig. 1 and Fig. 2A-Fig. 2 G according to an embodiment of the invention in semiconductors manufacture mistake
The method of the dual composition of autoregistration is used in journey.Wherein, Fig. 1 shows according to an embodiment of the invention dual for autoregistration
A kind of flow chart of the method for composition；Fig. 2A~Fig. 2 G be show it is according to an embodiment of the invention for the dual structure of autoregistration
The schematic cross sectional view of each step in the method for figure.
The method for the dual composition of autoregistration of this implementation, comprising:
Step S101 provides semiconductor substrate, forms core model material layer on the semiconductor substrate.
As shown in Figure 2 A, semiconductor substrate 200 is provided, is pre-formed with target material layer on semiconductor substrate 200
201, and core model material layer 202 is formed in target material layer 201
The constituent material of substrate 200 can be undoped with monocrystalline silicon, the monocrystalline silicon doped with N-type or p type impurity, polycrystalline
Silicon, germanium silicon or silicon-on-insulator (SOI) etc..
Target material layer 201 can be formed in interconnection wiring layer on substrate, interlayer dielectric layer, gate material layers or
Hard mask layer.The constituent material of the interconnection wiring layer is selected from least one of tungsten, tungsten silicide, aluminium, titanium and titanium nitride.It is described
The constituent material of interlayer dielectric layer can be selected from low-k (k) material or ultralow-k material film, for example, holy big by California, USA
Black DiamondTM II (BDII) dielectric of gram Laura city Applied Materials companies market, by Dow
Chemical companies marketWith(benzocyclobutene) dielectric material.The composition of the gate material layers
Material is selected from one of polysilicon and aluminium.The constituent material of the hard mask layer is selected from oxide, undoped silicon glass, glass
At least one of upper silicon, SiON, SiN, SiBN, BN and high-g value.It should be noted that target material layer 201 be it is optional and
Optionally, it can be accepted or rejected according to the actual situation.
Core model material layer 202 can any suitable material for being conducive to forming and removal.Illustratively, in the present embodiment
In, core model material layer 202 is amorphous silicon layer.
Step S102 is handled the core model material layer so that it is densified.By to the core model material layer into
Row densification, can prevent in the subsequent process its be oxidized and lead to low frequency roughness.
Illustratively, in the present embodiment, the step S102 includes:
Step S1021 carries out ion implanting to the core model material layer 202, to improve the table of the core model material layer 202
Surface roughness.Illustratively, ion implanting is carried out using band shaped plasma beam (plasma ribbon beam), injects ion
It can be phosphorus, argon, arsenic etc., implantation dosage is schematically 1E14~2E16atoms/cm2, Implantation Energy is schematically 40~
80keV。
Step S1022 handles the core model material layer using adaptive coupled plasma, to increase the core model material
The hardness of layer.Using with adaptive coupled plasma source (adaptively coupled plasma (ACP) source)
In etching system, the core model material layer 202 is handled, to increase the hardness of core model material layer 202.ACP plasma with
ICP (inductively coupled plasma body) and the characteristics of CCP (capacitance coupling plasma), after ACP plasma etching etching,
The hardness of material can be increased.Illustratively, in the present embodiment, in ACP chamber, pressure 15mTorr, plasma source function
Rate is 1200W.
Step S103, the graphical core model material layer, to form core model.
As shown in Figure 2 B, by the graphical core model material layer 202 of the common methods such as photoetching, to form core model 203.
Illustratively, in this embodiment, core model material layer 202 is stated by following step figure, specifically:
Step S1031 forms sacrificial material layer in the core model material layer 202.
As shown in Figure 2 C, sacrificial material layer 204 is formed in core model material layer 202.
Sacrificial layer 204 can be amorphous carbon structure or advanced patterned film (APF, Advanced Patterning Film) material
Material is constituted.Wherein, APF material can be obtained from the Applied Materials of the holy santa clara of California, such as Advanced
Patterning FilmTM.This APF materials'use bilayer patterned film is laminated, by peelable CVD carbon hardmask technology with
Dielectric anti-reflective coating (DRAC) technology combines, to realize the contact etching of large ratio of height to width.The further money of APF material
Material and it is patterned to make it have the process of pattern and can be found in China application No. is 200810132400.2
Patent application in the publication has a detailed description this.As an example, constituting sacrificial layer 204 with amorphous carbon in the present embodiment.
Certainly, sacrificial layer 204 is not limited in both materials, as long as but it can be removed by dry or wet
It is suitable for the present invention without dry etching, that is, removable material.I.e. it is capable to remove nothing by dry or wet
The material for needing dry etching i.e. removable existing or being likely to occur in the future may be used to constitute the sacrifice in the present invention
Layer, therefore still fall within the scope of the invention.
Step S1032, the graphical sacrificial material layer.
As shown in Figure 2 C, photoresist layer 206 is formed in the sacrificial material layer 204, and passes through the operation such as exposure development
The photoresist layer 206 is patterned, is then sacrificial material layer described in mask etching with patterned photoresist layer 206
204, the composition is transferred in the patterned sacrificial material layer 204.Pass through the common process such as photoetching and etching
Sacrificial layer 204 is patterned it is known to those skilled in the art to make it have the process of pattern and condition etc.,
This is repeated no more.
Furthermore it in order to provide the resolution ratio of photoetching and avoid pollution of the photoresist to device, is gone back in sacrificial material layer 204
The film layer 205 including at least one of bottom anti-reflection layer (BRAC), the hard hard membrane layer of composition can be formed.
Step S1033 arrives pattern transfer using the patterned sacrificial material layer as core model layer described in mask etching
In the core model material layer, it is as shown in Figure 2 B to be formed by structure.
Since in 65nm and following technology node, it is biggish not to be used in etching depth-to-width ratio for photoresist layer thinner thickness
Lines, thus by forming thicker sacrificial material layer, it is transferred in the sacrificial material layer to be first about to photoetching offset plate figure, with more
The composition to core model material layer is realized well.
Step S104 carries out isotropic etching to the core model.
Illustratively, in this embodiment, it is handled using CDE (chemical down-stream etch) method to described
Core model 203 carries out isotropic etching.The etching is chemical etching, mainly each to carry out by active group and reacting for core model
It is etched to the same sex.Illustratively, in the present embodiment, the core model constituted in the CDE using oxygen-enriched active group come amorphous silicon
203 carry out isotropic etching.By the isotropic etching, the low frequency line width roughness of core model 203 can be improved.
Step S105 forms compensation layer on the mandrel surface and side wall.
As shown in Figure 2 D, compensation layer 207 is formed on 203 surface of core model and side wall.It is exemplary, in the present embodiment, lead to
The silicon substrate above ise chamber is crossed, to make silicon atom be fallen on 203 surface of core model and side wall from top to bottom, with compensation
The some materials that core model 203 is lost in step S104 due to isotropic etching, further the line width of the core model 203 is coarse
Degree.
Step S106 forms hardmask material on the surface of the substrate and the surface of the core model and side wall.
As shown in Figure 2 E, the shape on the surface on 201 surface of target material layer and core model 203 on substrate 200 and side wall
At hardmask material 208.Wherein, hardmask material 208 can be made of silicon.It as an example, can be by temperature
About 800~1200 DEG C and air pressure are to decompose comprising at least one in SiCl2, SiCl3 and SiCl4 under conditions of 100~760 supports
Kind source gas form monocrystalline silicon layer, as hardmask material 208.As another example, can by 500~
Hardmask material 208 is formed as source gas using SiH4 at a temperature of 700 DEG C.The process of monocrystalline silicon layer formed more and
Condition can be found in the Chinese patent application application No. is 99801049.9, have a detailed description in the publication to this.In addition, covering firmly
Membrane layers 208 can also be made of at least one of SiO2, SiN, TaN and TiN.
In addition, in addition to CVD method, it is preferable that hardmask material 208 can also be formed, by ALD method so as to lower layer
The surface of film layer (for example, target material layer 201 and core model 203) has preferable spreadability.
Step S107 executes etch-back, is made of with being formed on the side wall of the core model the hardmask material
Side wall.
Etch-back is executed, removal is located at the hardmask material 208 above the top surface of core model 203, at least to expose core
The top surface of mould 203, to form the side wall being made of a part of hardmask material 208 on the side wall of core model 203
209, as shown in Figure 2 F.Technique used by etch-back can be plasma etching conventional in field of semiconductor manufacture
(RIE) technique.
Step S108 removes the core model.
After executing etch-back as described above, core model 203 is removed, retains side wall 209, as shown in Figure 2 G.According to core model 203
Material selection suitable dry or wet technique removal, the process conditions and parameter for removing core model 203 are those skilled in the art
Well known to member, details are not described herein.
Need to be explained, as shown in Figure 2 F, the minimum spacing P2 made by means of the present invention with as existing
The minimum spacing P1 of technology photolithography limitation CD is compared and is obviously reduced, and can reduce to the half of CD.For example, immersion
The limit CD of photoetching technique is 32nm, and utilizes method of the invention, can obtain 16nm small spacing below.
Further, in embodiment, due to having carried out densification to core model material, thus in subsequent progress chemistry
When isotropic etching, it is not easy to it is oxidized, thus the low frequency wire that can improve core model by chemical isotropic is broad and rough
Rugosity so as to improve the low frequency line width roughness of side wall, and not will cause other influences.
Embodiment two
The system of semiconductor devices according to an embodiment of the invention is described in detail next, with reference to Fig. 3 and Fig. 4 A- Fig. 4 C
Make method.Wherein, Fig. 3 shows a kind of flow chart of the manufacturing method of semiconductor devices according to an embodiment of the invention；Figure
4A~Fig. 4 C shows the schematic cross sectional view of each step in the manufacturing method of an embodiment semiconductor devices according to the present invention.
The manufacturing method of the semiconductor devices of the present embodiment, comprising:
Step S301 provides substrate, forms target material layer and core model material layer over the substrate.
As shown in Figure 4 A, semiconductor substrate 400 is provided, the formation target material layer 401 in semiconductor substrate 400, and
Core model material layer 402 is formed in target material layer 401.
The constituent material of substrate 400 can be undoped with monocrystalline silicon, the monocrystalline silicon doped with N-type or p type impurity, polycrystalline
Silicon, germanium silicon or silicon-on-insulator (SOI) etc..Target material layer 401 can be formed in interconnection wiring layer, interlayer on substrate
Dielectric layer, gate material layers or hard mask layer.Also, target material layer 401 be it is optional and optionally, can be according to practical feelings
Condition is accepted or rejected.Core model material layer 402 selects suitable material according to demand, exemplary, such as amorphous silicon layer.
Step S302 is formed with the first hard mask layer 403 for using method described in the above embodiment of the present invention to be formed
Structure chart 4B shown in.
Step 303, subsequent technique is executed so that first hard mask layer 403 is exposure mask.
It is exposure mask with first hard mask layer 403, target material layer 401 is etched, by the figure of the first hard mask layer 403
Case is transferred to target material layer 401, to form the target material layer 404 with predetermined pattern, as shown in Figure 4 C.Etching is adopted
Technique is it is known in the art that details are not described herein.
Here, need to be understood, through the above way can target material layer 401 formed grid structure, bit line and/
Or active area, a part as the semiconductor devices being subsequently formed.It as an example, will be in target material layer 401
Grid structure pattern is formed, in this case, target material layer 401 can be conductive layer (for example, polysilicon layer) or metal layer
(for example, tungsten layer or tungsten silicide layer).As another example, bit line pattern will be formed in target material layer 401, in this feelings
In condition, target material layer 4010 can be metal layer (for example, tungsten or aluminium layer).It needs to draw attention to, also can use the present invention
Hard mask layer active area pattern is formed in target material layer 401, in this case, target material layer 401, which can be, partly to be led
Body substrate, masking layer when the first hard mask layer 403 is as active area ion implanting at this time.Alternatively, it is also possible to utilize the present invention
The alternatively property epitaxial growth of the first hard mask layer 403 masking layer, and the needs occurred in the future can also be used for
Any technique of masking layer.
In addition to above-mentioned film layer, before the formation of core model layer 402, etching can also be formed in target material layer 401
Stop-layer or boundary layer (interface layer) or the second hardmask material, to be etched to target material layer
When protection underlying film layer will not cause to damage due to overetch (over-etch), or avoid the core model to device contamination.
The constituent material of etching stopping layer and boundary layer can be, for example, SiN, SiO2 or dielectric substance.Form etching stopping layer and boundary
The process conditions and parameter of surface layer are known to those skilled in the art, also repeat no more herein.
It can be applied in a variety of integrated circuits (IC) according to the semiconductor devices that embodiment as described above manufactures.According to this
The IC of invention is, for example, memory circuit, as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM),
Static RAM (SRAM) or read-only memory (ROM) etc..IC according to the present invention can also be logical device, such as programmable to patrol
Volume array (PLA), specific integrated circuit (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or
Other any circuit devcies.IC chip according to the present invention can be used for such as consumer electronic products, such as personal computer, portable
In the various electronic products such as computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of method for the dual composition of autoregistration, which is characterized in that include the following steps:
Step S101 provides semiconductor substrate, forms core model material layer on the semiconductor substrate；
Step S102 is handled the core model material layer so that it is densified；
Step S103, the graphical core model material layer, to form core model；
Step S104 carries out isotropic etching to the core model；
Step S105 forms compensation layer on the mandrel surface and side wall；
Step S106 forms hardmask material on the surface of the substrate and the surface of the core model and side wall；
Step S107 executes etch-back, to form the side wall being made of the hardmask material on the side wall of the core model；
Step S108 removes the core model.
2. being used for the method for the dual composition of autoregistration as described in claim 1, which is characterized in that the step S102 includes:
Step S1021 carries out ion implanting to the core model material layer, to improve the surface roughness of the core model material layer；
Step S1022 handles the core model material layer using adaptive coupled plasma, to increase the core model material layer
Hardness.
3. being used for the method for the dual composition of autoregistration as claimed in claim 1 or 2, which is characterized in that the core model material layer
For amorphous silicon layer.
4. being used for the method for the dual composition of autoregistration as claimed in claim 1 or 2, which is characterized in that in the step S104
In, the isotropic etching is carried out by chemical drying method etching.
5. being used for the method for the dual composition of autoregistration as claimed in claim 1 or 2, which is characterized in that the step S103 packet
It includes:
Step S1031 forms sacrificial material layer in the core model material layer；
Step S1032, the graphical sacrificial material layer；
Step S1033 arrives pattern transfer using the patterned sacrificial material layer as core model material layer described in mask etching
In the core model material layer.
6. being used for the method for the dual composition of autoregistration as claimed in claim 5, which is characterized in that the sacrificial material layer is nothing
Shape carbon.
7. a kind of manufacturing method of semiconductor devices, which comprises
Substrate is provided, forms target material layer and core model material layer over the substrate；
The first hard mask layer is formed using the method such as according to any one of claims 1 to 6 for the dual composition of autoregistration；
Subsequent technique is executed as exposure mask using first hard mask layer.
8. the manufacturing method of semiconductor devices according to claim 7, which is characterized in that in the target material layer and institute
It states and is formed at least one of the second hardmask material, etching stopping layer and boundary layer between core model material layer.
9. the manufacturing method of semiconductor devices according to claim 8, which is characterized in that the subsequent technique is etching work
Skill, ion implantation technology or selective epitaxial growth process.
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| US11106126B2 (en) * | 2018-09-28 | 2021-08-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing EUV photo masks |
| DE102019110706A1 (en) | 2018-09-28 | 2020-04-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | METHOD FOR PRODUCING EUV PHOTO MASKS |
| CN110379706B (en) | 2019-07-17 | 2021-08-13 | 上海华力微电子有限公司 | Method for optimizing double exposure key size of NAND flash |
| CN112309978A (en) * | 2019-07-31 | 2021-02-02 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure and transistor |
| CN113130751B (en) * | 2021-03-02 | 2022-07-22 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| CN113078100B (en) * | 2021-03-19 | 2021-12-17 | 长江存储科技有限责任公司 | Self-aligned imaging method |
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