CN107978558A - 导通孔的铜填充工艺 - Google Patents
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Abstract
本发明涉及导通孔的铜填充工艺,包括以下步骤:在第一偏压下,对导通孔进行铜的第一次物理气相沉积;在第二偏压下,对导通孔继续进行铜的第二次物理气相沉积,且第二偏压小于第一偏压。本发明采用物理气相沉积铜填充工艺替代化学气相沉积钨填充工艺,在不降低孔结构填充能力的情况下,能提高金属薄膜质量以及降低电阻率,同时结合铜电镀(ECP)工艺,简化工艺制程,降低工艺生产成本。
Description
技术领域
本发明涉及半导体的制造工艺领域,特别涉及一种导通孔的铜填充工艺。
背景技术
随着半导体技术的不断发展,目前存储器制造技术已经逐步从简单的平面结构过渡到较为复杂的三维结构,三维存储器的技术研发是国际研发的主流之一。
在半导体的版图中,有源区、多晶硅和金属层之间的连接都需要通过接触孔/导通孔实现。有源区、多晶硅和金属层之间的连接称为接触孔。不同金属层之间的连接称为导通孔。
在三维存储器的制造工艺中,目前对于导通孔的填充多使用金属钨的化学气相沉积法,通过含有钨元素的气态反应剂在导通孔内发生化学反应生成金属钨薄膜进行填充。这种铜填充工艺具有均匀性、重复性好,台阶覆盖形优良等特点。
目前的金属钨的铜填充工艺已发展比较成熟并且薄膜性能也比较稳定,不易产生空洞和缺陷,但是由于钨的金属特性,也存在一些难以克服的缺陷。一方面钨的应力和电阻率较大,电性较差,另一方面,钨的填充成本也较高。
与此相对的是,铜是一种电性良好且工艺成本低的金属,物理气相沉积铜填充(PVD铜填充)是一种用于集成电路半导体金属互联的重要工艺,它是一种通过等离子体对靶材的轰击产生离化的铜离子,铜离子在偏压的作用下发生溅射,生长成种子层的工艺。但是由于目前发展有限,该工艺仅主要应用于沟槽结构的填充中。对于孔状结构而言,物理气相沉积铜填充生成的种子层的台阶覆盖率很难满足工艺要求。如果能有新的改进工艺,提高铜在孔状结构中的填充能力,将可以在导通孔的铜填充工艺中用金属铜来取代金属钨,从而解决现有的缺陷。
发明内容
本发明的目的是为解决以上问题的至少一个,本发明提供导通孔的铜填充工艺。
一种导通孔的铜填充工艺,包括以下步骤:
在第一偏压条件下,对导通孔进行铜的第一次物理气相沉积;
在第二偏压条件下,对经过第一次铜的物理气相沉积后的导通孔继续进行铜的第二次物理气相沉积,且第二偏压小于第一偏压。
其中,第一偏压的范围为500~1000W,第二偏压的范围为50~500W。
其中,导通孔的口径小于等于150nm,导通孔的深宽比小于等于3:1。
本发明采用物理气相沉积铜填充工艺替代化学气相沉积钨填充工艺,在不降低孔结构填充能力的情况下,能提高金属薄膜质量以及降低电阻率,同时结合铜电镀(ECP)工艺,简化工艺制程,降低工艺生产成本。
附图说明
通过阅读下文优选实施方式的详细描述,各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的,而并不认为是对本发明的限制。而且在整个附图中,用相同的参考符号表示相同的部件。在附图中:
图1示出了一般铜填充工艺的导通孔的填充后截面图;
图2示出了根据本发明实施方式的铜填充工艺的导通孔的填充后截面TEM图;
图3示出了根据本发明实施方式的铜填充工艺的导通孔的填充后表面缺陷图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式,然而应当理解,可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反,提供这些实施方式是为了能够更透彻地理解本公开,并且能够将本公开的范围完整的传达给本领域的技术人员。
现有技术中,使用PVD铜沉积工艺对孔状结构的填充时,由电场强力加速的离子轰击靶材,轰击能够使铜离子从靶材喷射出并在孔侧壁沉积,由于喷射的粒子在进入孔内部之前先接触孔侧壁的顶部,因此沉积通常在空侧壁的顶部附近发生较快,形成如图1所示的悬突1。悬突1的产生能导致孔内产生具有孔隙的金属栓塞。这些金属栓塞会严重影响器件的导电率。
本发明通过使用偏压大小不同的两步溅射工艺对导通孔进行铜的物理气相沉积,先用大偏压尽可能多的将铜离子溅射到底部和侧壁,防止悬突现象导致开口处提前封口,再使用小偏压对孔洞进行正常填充,通过适宜大小的偏压间的相互配合消除栓塞缝隙现象,降低填充的表面缺陷,同时使铜种子层的厚度更加均匀且细密。
一种导通孔的铜填充工艺,具体包括以下步骤:
在第一偏压条件下,对导通孔进行铜的第一次物理气相沉积;在第二偏压条件下,对经过第一次铜的物理气相沉积后的导通孔继续进行铜的第二次物理气相沉积,且第二偏压小于第一偏压。
经反复实验证明,当第一偏压的取值范围为500~1000W,第二偏压的取值范围为50~500W,填充后的表面缺陷量和内部孔隙率能够满足三维存储器的工艺要求。
在一个具体的实施例中,在700W的第一偏压下,对导通孔进行铜的第一次物理气相沉积,然后在100W的第二偏压下,对导通孔继续进行第二次铜的物理气相沉积。导通口的孔径为150nm,深宽比为3:1,沉积结果如图2和图3所示。如图2所示,导通孔内沉积的铜种子层没有悬突现象,质地细密,没有间隙产生,且厚度均匀,如图3所示,平坦化后的填充表面缺陷少,且多集中于0~0.5um之间,大多为干扰缺陷。
综上所述,本发明先利用大偏压将多数铜离子溅射到导通孔的底部和侧壁,一方面使得导通孔的开口处不会发生提前封口,铜电镀后不会产生空洞,另一方面能够结合小偏压使得在用整个铜沉积的过程中,位于导通孔底部和侧壁的种子层的生长良好,具有一定厚度,满足铜电镀的要求,保证填充质量。
以上所述,仅为本发明较佳的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。
Claims (3)
1.导通孔的铜填充工艺,其特征在于,包括以下步骤:
在第一偏压下,对导通孔进行铜的第一次物理气相沉积;
在第二偏压下,对导通孔继续进行铜的第二次物理气相沉积,且第二偏压小于第一偏压。
2.如权利要求1所述的铜填充工艺,其特征在于,
第一偏压的范围为500~1000W,第二偏压的范围为50~500W。
3.如权利要求1所述的铜填充工艺,其特征在于,
导通孔的口径小于等于150nm,导通孔的深宽比小于等于3:1。
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Cited By (2)
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US10665500B1 (en) | 2018-12-07 | 2020-05-26 | Yangtze Memory Technologies Co., Ltd. | Methods of semiconductor device fabrication |
CN113097083A (zh) * | 2021-03-12 | 2021-07-09 | 长江存储科技有限责任公司 | 一种字线的填充空隙率的确定方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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CN113097083A (zh) * | 2021-03-12 | 2021-07-09 | 长江存储科技有限责任公司 | 一种字线的填充空隙率的确定方法 |
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