CN107942797A - Embedded dual core servo controller and its design method based on SOPC - Google Patents
Embedded dual core servo controller and its design method based on SOPC Download PDFInfo
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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Abstract
The present invention provides a kind of embedded dual core servo controller and its design method based on SOPC, hardware structure, the power-supply system that is connected comprising FPGA with signal therewith, program FLASH, data FLASH, driver, data command communication unit, sensing data reading unit etc., FPGA carries out double-core parallel computation equipped with two Microblaze soft-core processors；Multiple soft cores of IP carry out signal connection by PLB buses, and each Microblaze soft-core processors carry out data interaction by PLB buses and the soft cores of each IP；Double-core data communication is carried out between two Microblaze soft-core processors.Hardware structure, interface type are determined according to control system functional requirement, it is then determined that bottom most software framework, is compiled using XPS instruments, export top layer interface document, the soft nuclear control device of top layer is carried out in SDK platforms and is designed and developed.The present invention improves the collaboration disposal ability of controller, has the advantages that strong aboundresources, scalability, the high and low cost of reliability and design are easy.
Description
Technical field
According to the present invention is Digitalized servo control system field, more particularly to a kind of Embedded Double based on SOPC
Core servo controller and its design method.
Background technology
At present, digital servo controller hardware platform mainly includes tri- kinds of frameworks of DSP, DSP+FPGA, FPGA, is based on
The servo controller of DSP has flexible design, the convenient advantage of debugging, but peripheral resources are limited, it is impossible to adapts to a variety of at present
The demand of communication interface high-speed parallel processing, even if TI companies are proposed F28M35 dual core processors, can not change this disadvantage
End, the servo controller based on DSP+FPGA, can meet at the same time flexible design with and connect the requirement of letter, but circuit is more
Complexity, cost are higher.Recently as the development of microelectric technique, on piece Programmable Technology is also gradually risen, can inside FPGA
With the soft core of insertion or hard nucleus management device, the function needed for the system designs such as processor, memory, I/O interfaces is integrated into one
On a programmable logic device FPGA, so as to form on piece programmable system (SOPC), it is using the controller based on single FPGA
The all functions of DSP+FPGA controllers can be achieved, so as to be widely applied in space flight, aviation field.
With increasing for task amount, the access that the embedded monokaryon systems of FPGA have to memory cannot be carried out at the same time,
The problem of easily chaotic in the case of high-speed cruising, the FPGA of Xilinx companies is proposed Dinuclear Systems, you can with a FPGA
Be internally embedded the soft core Microblaze of two on piece microprocessors (it is a kind of for Xilinx FPGA devices and the function that optimizes is strong
Big 32-bit microprocessor, and the most fast soft processor IP kernel solution of industry), multitask coordinated, parallel computation is carried out,
Greatly improve the response speed of system.
Recent domestic scholar has carried out numerous studies, Harbin Institute of Technology for the embedded system based on FPGA
Wang Xiaolu the several method to communicate between double-core is described in " the embedded dual core system design based on FPGA " text.South
The Bai Yuxian of capital Polytechnics is proposed in " embedded control system research and design based on SOPC technologies " text and is based on
Xilinx companies Virtex-5FXT FPGA are the designing scheme of the embedded control system of platform, this scheme is mainly based upon embedding
Enter formula real time operating system VxWorks software development and apply relevant research, in addition in the text it is mentioned that PowerPC440
Hard nucleus management device, not using the soft-core processor of Microblaze.The Yao Ming of Xia Men universities is same to aim at the " double-core based on FPGA
Proposing a kind of Virtex-II Pro development boards based on Xilinx in an embedded system structure " text realizes double-core insertion
Formula system constructing, gives the construction method and principle of Dinuclear Systems, at the stone of this main PowerPC405 of construction method
Manage device framework.
Patent application " autonomous configuration method of the embedded dual core system based on FPGA " (CN201410047913.9) one
Wen Zhong, it is proposed that the problem of Dinuclear Systems are independently completed to configure and load.Patent application " the embedded dual core relay based on FPGA
The double-core design method based on NIOS II soft-core processors is proposed in protection system " (CN201510107412.X) text.Patent
Apply for a kind of " machine vision control method and robot controller and robot control system " (CN201610122709.8) one
Application of the embedded dual core microprocessor in image procossing and motion control is proposed in text.The prior art, which is showed no, is related to base
In the embedded dual core antenna servo controller design method of SOPC.
At present, the monokaryon Digitalized servo control system based on FPGA, using single main thread, multi-task scheduling is both needed to adopt
With inquiry or the mode interrupted, the stand-by period under blocked state is increased, extends the cycle of data update, and without absolute
Parallel processing in meaning.The practical problems such as multitask, big data quantity are being faced, the single core processor execution time is longer and can not
The inferior position of parallel processing gradually appears, and the real-time and arithmetic accuracy of control can not be guaranteed.
The content of the invention
It is a kind of based on the embedded of SOPC it is an object of the invention to propose to solve the problems, such as that above current art exists
Double-core servo controller, improves the collaboration disposal ability of controller, and with aboundresources, scalability is strong, reliability is high,
The advantages of low cost and easy design.Present invention also offers the design side of the embedded dual core servo controller based on SOPC
Method.
In order to achieve the above object, a technical solution of the invention is to provide a kind of embedded dual core based on SOPC and watches
Controller is taken, it includes：
As the FPGA of master controller, connected with signal therewith with lower module：
Power-supply system, is FPGA and other module for power supply；
Program FLASH, stores program, for FPGA reading programs；
Data FLASH, stores control parameter, and control parameter is read for FPGA；
Data command communication unit, realizes that FPGA communicates with the data command of external device (ED)；
Sensing data reading unit, obtains sensing data, there is provided to FPGA；
Driver, the drive signal provided according to FPGA, is driven executive device；
Wherein, FPGA carries out double-core parallel computation equipped with two Microblaze soft-core processors；Multiple soft cores of IP lead to
Cross PLB buses and carry out signal connection, each Microblaze soft-core processors carry out data friendship by PLB buses and the soft cores of each IP
Mutually；Double-core data communication is carried out between two Microblaze soft-core processors.
Preferably, the first soft-core processor Microblaze0 carry out data command receive send, sensing data read and
Pretreatment, and pass through double-core data communication and the second soft-core processor Microblaze1 shared datas；Second soft-core processor
Microblaze1 powers on reading control parameter, and the calculating of servo control algorithm is completed according to shared data, and sends out drive signal
To driver, the set function of servo-drive system is realized.
Preferably, the first soft-core processor Microblaze0 is controlled by the first PLB buses with timer IP kernel, interruption
IP kernel, sensor read IP kernel interaction data；Second soft-core processor Microblaze1 is by the 2nd PLB buses, with timer
IP kernel, Interrupt controller IP core, data command read IP kernel, driver control IP kernel, control parameter storage IP kernel interaction data.
Preferably, the double-core data communication between two Microblaze soft-core processors, based on Shared BRAM or
MailBox modes are realized.
Preferably, Shared BRAM modes are also arbitrated by exclusive reference IP kernel Mutex.
Preferably, when data sharing amount is more than 1000 byte, double-core data communication selection Shared BRAM modes, otherwise
Select Mailbox.
Another technical solution of the present invention is to provide a kind of design of the embedded dual core servo controller based on SOPC
Method, suitable for any one above-mentioned embedded dual core servo controller based on SOPC.
Preferably, the design method comprises the steps of：
S1, the demand according to the set function of servo-drive system, build control loop；
S2, according to control loop, determine the hardware structure of embedded dual core servo controller, comprising FPGA and therewith signal
The power-supply system of connection, program FLASH, data FLASH, driver, data command communication unit, sensing data read single
Member；
S3, according to hardware structure and control strategy, determine the soft cores of IP needed for embedded dual core servo controller bottom, wrap
IP kernel containing timer, Interrupt controller IP core, sensor read IP kernel, data command reading IP kernel, driver control IP kernel, control
Parameter stores IP kernel；Each soft cores of IP open corresponding data port and are connected with PLB buses；
S4, build the bottom software platform based on the soft cores of IP in XPS：
According to the FPGA models of selection, the bottom software platform with two Microblaze soft-core processors is created；Will
The soft cores of IP are added in bottom software platform to be connected with PLB buses, and distribution internal clocking, outside port, address, it is soft to carry out bottom
Part schema compilation；
After the completion of the bottom most software schema compilation that S5, XPS are built, export top layer interface document is controlled into SDK is
The top layer exploitation of system.
The present invention provides a kind of embedded dual core servo controller and its design method based on SOPC, using based on
Double MicroBlaze soft-core processors of Xilinx (match Sentos) company FPGA, complete digitial controller parallel computation, cooperate with work
Make, improve operating rate, realize the high request SERVO CONTROLs such as high accuracy, high real-time, multitask.
Hardware structure, interface type are determined according to control system functional requirement, it is then determined that bottom most software framework, utilizes
XPS instruments are compiled, and export top layer interface document, and the soft nuclear control device of top layer is carried out in SDK platforms and is designed and developed.
The present invention brings following beneficial effect：
(1) high real-time：The design method uses two Microblaze embedded software core processors, it is possible to achieve control
The synchronous operation of algorithm and data prediction, real-time are greatly improved.
(2) it is inexpensive：The design method realizes all functions of original DSP+FPGA schemes using single FPGA, can be with
Realize low-cost design.
(3) flexibility is high：Control algolithm and data prediction are run using embedded system Microbalze, can be online
Operation debugging, monitoring run data, change the cumbersome debud mode of traditional FPGA.Moreover, control parameter can more than
Electricity is read, and can be adjusted flexibly according to the otherness of servo-drive system.
(4) stability is good：Be verified by experiments, the system repeat power on and long-time high-low-temperature environmental testing and vibration examination
Testing down still can stable operation.
Brief description of the drawings
Fig. 1 is the hardware structure schematic diagram of the embedded dual core servo controller based on SOPC；
Fig. 2 is the schematic diagram of the parametrization debugging hardware debugging platform of Duo-Core Architecture in the present invention；
Fig. 3 is the schematic diagram of the controller parameter changing process of the invention based on state machine；
Fig. 4 is the stable loop schematic diagram of angular rate gyroscope formula stabilized platform in the embodiment of the present invention；
Fig. 5 is the schematic diagram of the hardware structure of angular rate gyroscope formula stabilized platform in the embodiment of the present invention；
Fig. 6 is the bottom software configuration diagram of angular rate gyroscope formula stabilized platform in the embodiment of the present invention.
Embodiment
Double-core control system of the present invention based on SOPC, the FPGA for being all based on Xilinx companies are core processing
Device, and using two MicroBlaze soft-core processors of on piece, realize digitial controller double-core parallel computation.FPGA includes rich
Rich logical design resource, can complete the logic and data processing function of complexity, have repeatable programming, design cycle it is short,
The advantages such as R＆D costs are low.
Double-core control system hardware structure based on SOPC is as shown in Figure 1, include FPGA master controllers, power-supply system, journey
Sequence FLASH, data command communication, sensing data reading unit, driver, data FLASH etc..Power-supply system is mainly FPGA
And other modules provide power supply, program FLASH is mainly used for program storage, and data FLASH is mainly used for storing control parameter, drives
Dynamic device is mainly used for driving executive device, and FPGA master controllers are used to complete reading program, sensing data, operation control calculation
The functions such as method, output drive signal.
Double-core control system FPGA in house softwares framework is as shown in Fig. 2, including two Microblaze soft-core processors, base
Double-core data communication, memory I P cores, timer are realized in Shared BRAM (shared drive mode) or MailBox (mailbox)
IP kernel, Interrupt controller IP core, external function IP kernel, data command communication IP kernel, driver control IP kernel, control parameter storage IP
Core etc., the soft cores of above IP are attached by PLB buses, Microblaze soft-core processors by PLB buses and each soft core into
Row data interaction.
FPGA double-cores communication at present mainly includes 2 kinds of modes：Shared BRAM and Mailbox.Based on Shared BRAM
Double-core communication mode it is relatively simple, share situation suitable for big data quantity, reading speed is fast, realize it is simple, but two
A Microblaze processors there is a situation where to read while write, it is necessary to which by internal Mutex, (XPS is provided multi-thread for handling
The exclusive reference IP kernel that journey works to shared resource) arbitrate, realize exclusive reference, and double-core has no real time data friendship
Change.Soft core based on Mailbox sets up the communication between two soft core, and each Mailbox carries data sending and reception
FIFO, can accomplish the real-time direct interaction of data, be adapted to frequent data item Frame switch.Both the above communication mode respectively has advantage and disadvantage,
The present invention, which does not limit, uses which kind of mode therein into row data communication., can be according to data sharing amount in preferable example
Make choice, if greater than 1000 bytes, select Shared BRAM, otherwise suggest selection Mailbox.
Double-core control system operating scheme based on SOPC is as shown in figure 3, stablizing for SERVO CONTROL field control algolithm is real
It is existing, be built upon fixed cycle T when domain operation on, and the controlling cycle should be much smaller than the response cycle of servo-drive system.
In high accuracy, high real-time, multitask SERVO CONTROL field, in order to obtain higher controller computational accuracy, it is desirable to control week
Phase is very short, and sensor pretreatment and complicated control algolithm can consume substantial amounts of operation time at the same time, it is therefore necessary to using double
Core system can preferably solve problems.
Wherein, soft core Microblaze0 is used as sensor reading and command reception sending function, and as requested into line number
Data preprocess, passes through Mailbox or Shared RAM and soft core Microblaze1 shared datas；Soft core Microblaze1 is powered on
Control parameter is read, the calculating of servo control algorithm is completed according to shared data, and sends out drive signal and is watched to driver, realization
The set function of dress system.
Herein by taking two axis high-precision spatial stabilized platforms as an example, it is discussed in detail proposed by the present invention a kind of based on the embedding of SOPC
Enter the design method of formula double-core servo controller：
1st, required according to function of servo system, build control loop
The structure of control loop determined according to different control functions demand, at present angular rate gyroscope formula stabilized platform
Stable loop is mainly by controller Gc(s), the driving mechanism G (s) of motor power amplifier, motor and mechanism, rate gyroscope T (s) are included,
Tachometer etc. is formed, as shown in Figure 4.By velocity measurement mechanisms into inner looping be mainly used for improve system stiffness, by rate gyroscope structure
Into external loop be mainly used for isolating disturbance, realize spatial stability.
2nd, according to control loop, entirety hardware control framework is determined
According to the control loop of structure, the hardware structure of controller, as shown in figure 5, be based on FPGA, with RS 422 into line number
According to command communication, AD signal-obtainings are carried out to tachometer, signal-obtaining is carried out with RS 422 to gyro, PWM is exported to driver
Signal, and carry out SPI signal read-write with data Flash.Not to choosing tachometer, type of driver, gyro in the present embodiment
The problems such as interface type, discusses, and can be solved according to techniques well known.
3rd, according to overall hardware control framework and control, the soft cores of IP needed for bottom are determined
According to controller hardware framework, it may be determined that the bottom software framework of controller needs：Timer IP kernel, interrupt control
IP kernel processed, gyro RS422 read IP kernel, tachometer AD reads IP kernel, data command RS422 reads IP kernel, pwm driver control
IP kernel, SPI data storage IP kernel, as shown in fig. 6, the data communication and sensing data amount due to being referred in this example are no more than
1000 bytes, the communication mode between double-core select Mailbox modes.The soft cores of IP open phase as needed during writing
Data port is answered to be connected with PLB buses.
4th, the bottom software platform based on the soft cores of IP is built in XPS
XPS (Xilinx Platform Studio) be Xilinx companies provide the programming tool based on the soft cores of IP, root
According to the FPGA models of selection, the double Microblaze platforms of bottom are created by XPS, the software architecture determined according to Fig. 6 will be above-mentioned
The soft cores of IP are added in XPS platforms, are connected to PLB buses, distribute internal clocking and outside port, then distribute address, carry out
Bottom software schema compilation.
5th, system design is controlled in SDK
SDK (Software Develop Kit) is the embedded platform developing instrument that Xilinx companies provide, main to use
Specific implementation and algorithm in development system, debugging are convenient, flexible.The bottom most software schema compilation that above-mentioned XPS is built is completed
Afterwards, SDK platforms can be exported to and carry out top layer exploitation.Details are not described herein for the design method of IP kernel.
As shown in figure 3, soft core Microblaze0 can complete gyro data reading, tachometer data in timer interruption
Read, line number of going forward side by side Data preprocess, data interaction is carried out by Mailbox and Microbalze1；Microblaze1 mainly can
Complete to read with Microlbalze0 data interactions, control algolithm operation, driver control and parameter in timer interruption, deposit
Storage.
The cycle T of Microblaze1 timer interruptions1Mainly determined, should met following by the response characteristic of control loop
Formula：
T≤1/10/fbw
F in formulabwResponsive bandwidth needed for control system.
The cycle T of Microblaze0 timer interruptions0It is T1More than 2 times.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. a kind of embedded dual core servo controller based on SOPC, it is characterised in that include：
As the FPGA of master controller, connected with signal therewith with lower module：
Power-supply system, is FPGA and other module for power supply；
Program FLASH, stores program, for FPGA reading programs；
Data FLASH, stores control parameter, and control parameter is read for FPGA；
Data command communication unit, realizes that FPGA communicates with the data command of external device (ED)；
Sensing data reading unit, obtains sensing data, there is provided to FPGA；
Driver, the drive signal provided according to FPGA, is driven executive device；
Wherein, FPGA carries out double-core parallel computation equipped with two Microblaze soft-core processors；Multiple soft cores of IP pass through PLB
Bus carries out signal connection, and each Microblaze soft-core processors carry out data interaction by PLB buses and the soft cores of each IP；Two
Double-core data communication is carried out between a Microblaze soft-core processors.
2. the embedded dual core servo controller based on SOPC as claimed in claim 1, it is characterised in that
First soft-core processor Microblaze0 carries out data command and receives transmission, sensing data reading and pretreatment, and leads to
Cross double-core data communication and the second soft-core processor Microblaze1 shared datas；
Second soft-core processor Microblaze1 powers on reading control parameter, and servo control algorithm is completed according to shared data
Calculate, and send out drive signal to driver, realize the set function of servo-drive system.
3. the embedded dual core servo controller based on SOPC as claimed in claim 1 or 2, it is characterised in that
First soft-core processor Microblaze0 is by the first PLB buses, with timer IP kernel, Interrupt controller IP core, sensor
Read IP kernel interaction data；
Second soft-core processor Microblaze1 is referred to by the 2nd PLB buses with timer IP kernel, Interrupt controller IP core, data
IP kernel, driver control IP kernel, control parameter storage IP kernel interaction data are read in order.
4. the embedded dual core servo controller based on SOPC as claimed in claim 1 or 2, it is characterised in that
Double-core data communication between two Microblaze soft-core processors, it is real based on Shared BRAM or MailBox mode
It is existing.
5. the embedded dual core servo controller based on SOPC as claimed in claim 4, it is characterised in that
Shared BRAM modes are also arbitrated by exclusive reference IP kernel Mutex.
6. the embedded dual core servo controller based on SOPC as claimed in claim 4, it is characterised in that
When data sharing amount is more than 1000 byte, double-core data communication selection Shared BRAM modes, otherwise select Mailbox.
A kind of 7. design method of the embedded dual core servo controller based on SOPC, it is characterised in that the design method bag
Containing following steps：
S1, the demand according to the set function of servo-drive system, build control loop；
S2, according to control loop, determine the hardware structure of embedded dual core servo controller, connected comprising FPGA with signal therewith
Power-supply system, program FLASH, data FLASH, driver, data command communication unit, sensing data reading unit；
S3, according to hardware structure and control strategy, the soft cores of IP needed for embedded dual core servo controller bottom are determined, comprising fixed
When device IP kernel, Interrupt controller IP core, sensor reads IP kernel, data command reads IP kernel, driver control IP kernel, control parameter
Store IP kernel；Each soft cores of IP open corresponding data port and are connected with PLB buses；
S4, build the bottom software platform based on the soft cores of IP in XPS：
According to the FPGA models of selection, the bottom software platform with two Microblaze soft-core processors is built；IP is soft
Core is added to bottom software platform and is connected with PLB buses, and each Microblaze soft-core processors are soft by PLB buses and each IP
Core carries out data interaction, and distribution internal clocking, outside port, address, carry out bottom software schema compilation；
Between two Microblaze soft-core processors, double-core data are carried out based on Shared BRAM or MailBox mode and are led to
Letter；
After the completion of the bottom most software schema compilation that S5, XPS are built, export top layer interface document is controlled system into SDK
Top layer is developed.
8. the design method of the embedded dual core servo controller based on SOPC as claimed in claim 7, it is characterised in that
First soft-core processor Microblaze0 reads IP kernel with timer IP kernel, Interrupt controller IP core, sensor and interacts number
According to progress data command receives transmission in timer interruption, sensing data is read and pretreatment, and is led to by double-core data
Letter and the second soft-core processor Microblaze1 shared datas；
Second soft-core processor Microblaze1 reads IP kernel, driving with timer IP kernel, Interrupt controller IP core, data command
Device control IP kernel, control parameter storage IP kernel interaction data, power on reading control parameter, according to shared data in timer interruption
The calculating of servo control algorithm is completed, and sends out drive signal to driver, realizes the set function of servo-drive system.
9. the embedded dual core servo controller based on SOPC as claimed in claim 8, it is characterised in that
The cycle T of second soft-core processor Microblaze1 timer interruptions1Determined by the response characteristic of control loop, meet with
Lower formula：
T1≤1/10/fbw
In formula, fbwResponsive bandwidth needed for control system；
The cycle T of first soft-core processor Microblaze0 timer interruptions0It is T1More than 2 times.
10. the design method of the embedded dual core servo controller based on SOPC as claimed in claim 7, it is characterised in that
When data sharing amount is more than 1000 byte, the double-core data communication selection between two Microblaze soft-core processors
Shared BRAM modes, otherwise select Mailbox.
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