CN101587342A - Wastewater treatment electric-control system based on the SOPC technology - Google Patents
Wastewater treatment electric-control system based on the SOPC technology Download PDFInfo
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- CN101587342A CN101587342A CNA2008100531768A CN200810053176A CN101587342A CN 101587342 A CN101587342 A CN 101587342A CN A2008100531768 A CNA2008100531768 A CN A2008100531768A CN 200810053176 A CN200810053176 A CN 200810053176A CN 101587342 A CN101587342 A CN 101587342A
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Abstract
A kind of wastewater treatment electric-control system based on the SOPC technology is made up of cpu motherboard module, several daughter boards IO expansion relays, several daughter boards IO expansion module and the two poles of the earth private bus; The cpu motherboard module is carried out two-way the connection with several daughter boards IO expansion relays by private bus, and each daughter board IO expansion relays is carried out two-way the connection by private bus with several daughter boards IO expansion module.Advantage of the present invention is: 1) good reliability.2) owing to adopted the FPGA structure of hardware description, so function expansibility and upgradability are strong.3) the controlled digital quantity I/O of controller mouth, analog quantity I/O mouth, it is individual to reach hundreds of thousands, can make the carefree expansion point of user.Overcome the low shortcoming of general programmable sequence controller I/O cost performance.
Description
Affiliated field:
The present invention relates to a kind of special-purpose electric-control system of wastewater treatment, particularly a kind of wastewater treatment electric-control system based on the SOPC technology.
Background technology:
The wastewater treatment electric-control system main problem that is in operation is: cesspool capacity such as regulating reservoir, hydrolysis acidification pool, intermediate pool, CAST reaction tank are big, electric-control system can not cut off the power supply throughout the year, interrupt even produce festivals or holidays, wastewater treatment can not be interrupted, this poses a big pressure to electric-control system, especially central control unit, be the CPU of programmable controller, generally through the continuous running in 5～6 years, faults such as deadlock very easily take place, cause plant of water disposal control malfunctioning, cause sewage outflow, contaminated environment.
Summary of the invention:
Purpose of the present invention just is to overcome above-mentioned the deficiencies in the prior art, and a kind of wastewater treatment electric-control system based on the SOPC technology is provided, and the functional reliability of this electric-control system, function expansibility and upgradability are strong.
Technical scheme of the present invention is: a kind of wastewater treatment electric-control system based on the SOPC technology is characterized in that: be made up of cpu motherboard module, several daughter boards IO expansion relays, several daughter boards IO expansion module and the two poles of the earth private bus; The cpu motherboard module is carried out two-way the connection with several daughter boards IO expansion relays by private bus, and each daughter board IO expansion relays is carried out two-way the connection by private bus with several daughter boards IO expansion module; Above-mentioned cpu motherboard module is integrated among the FPGA by several IP kernels; The IP kernel main body module is made up of two CPU main preparation system structures, Profibus controller, TCP/IP controller, RS232 serial communication controller and dedicated bus interface controller; Two CPU main preparation system structures are respectively with Profibus controller, TCP/IP controller, RS232 serial communication controller with the dedicated bus interface controller is two-way is connected; Wherein, two CPU main preparation system structures are made up of CPU1, CPU2, token moderator arbitrator, internal bus buffering switch mul, storage unit SRAM, FLASH and I/O interface; The output signal of enlivening of CPU1 is connected with the input port of token moderator arbitrator, the token output port of token moderator arbitrator is connected with the input port of CPU1, the output signal of enlivening of CPU2 is connected with the input port of token moderator arbitrator, and the token output port of token moderator arbitrator is connected with the input port of CPU2; CPU1 carries out two-way the connection by internal bus buffering switch mul with storage unit SRAM, FLASH and I/O interface respectively with CPU2.
Above-mentioned token moderator arbitrator is made up of timer, watchdog circuit, arbitration seeker, alarm and token follower; Watchdog circuit receives the output signal of timer, CPU1, CPU2, and is entered into the input end of arbitration seeker, and arbitration seeker output terminal is connected with the token follower with alarm respectively.
Above-mentioned CPU1, CPU2 adopt the soft nuclear flush bonding processor of the second generation NIOS II of altera corp.
Advantage of the present invention is:
1) good reliability.The present invention utilizes the embedded nuclear of NIOS II, and promptly two CPU of exploitation examine on a chip, and wherein No. 0 CPU is a host CPU, and No. 1 CPU is a stand-by heat.When a fault such as CPU generation deadlock, another seamless immediately startup overcomes general programmable controller, does not cut off the power supply all the year round like this, and (often reaching the several years) CPU control is malfunctioning, guarantees that the wastewater treatment electric-control system runs well.
2) owing to adopted the FPGA structure of hardware description, so function expansibility and upgradability are strong.
3) the controlled digital quantity I/O of controller mouth, analog quantity I/O mouth, it is individual to reach hundreds of thousands, can make the carefree expansion point of user.Overcome the low shortcoming of general programmable sequence controller I/O cost performance.
Description of drawings:
Fig. 1 is a main body theory diagram of the present invention.
Fig. 2 is two CPU main preparation system structural drawing.
Fig. 3 is the theory diagram of token moderator.
Embodiment:
As shown in Figure 1, 2: a kind of wastewater treatment electric-control system based on the SOPC technology is characterized in that: be made up of cpu motherboard module, several daughter boards IO expansion relays, several daughter boards IO expansion module and the two poles of the earth private bus; The cpu motherboard module is carried out two-way the connection with several daughter boards IO expansion relays by private bus, and each daughter board IO expansion relays is carried out two-way the connection by private bus with several daughter boards IO expansion module; Above-mentioned cpu motherboard module is integrated among the FPGA by several IP kernels; The IP kernel main body module is made up of two CPU main preparation system structures, Profibus controller, TCP/IP controller, RS232 serial communication controller and dedicated bus interface controller; Two CPU main preparation system structures are respectively with Profibus controller, TCP/IP controller, RS232 serial communication controller with the dedicated bus interface controller is two-way is connected; Wherein, two CPU main preparation system structures are made up of CPU1, CPU2, token moderator arbitrator, internal bus buffering switch mul, storage unit SRAM, FLASH and I/O interface; The output signal of enlivening of CPU1 is connected with the input port of token moderator arbitrator, the token output port of token moderator arbitrator is connected with the input port of CPU1, the output signal of enlivening of CPU2 is connected with the input port of token moderator arbitrator, and the token output port of token moderator arbitrator is connected with the input port of CPU2; CPU1 carries out two-way the connection by internal bus buffering switch mul with storage unit SRAM, FLASH and I/O interface respectively with CPU2.
Above-mentioned token moderator arbitrator is made up of timer, watchdog circuit, arbitration seeker, alarm and token follower; Watchdog circuit receives the output signal of timer, CPU1, CPU2, and is entered into the input end of arbitration seeker, and arbitration seeker output terminal is connected with the token follower with alarm respectively.Above-mentioned CPU1, CPU2 adopt the soft nuclear flush bonding processor of the second generation NIOS II of altera corp.
Principle of work of the present invention is: adopt the special-purpose SOPC embedded system of wastewater treatment of NIOSII nuclear, distributed input and output expansion structure.Integrated two processor cores that function is identical on a processor substrate are about to two physical processor core and are integrated in the kernel.Use the NiosII processor of altera corp and the double-core system that SOPC Builder developing instrument is designed and Implemented resource sharing, the embedded system of memory interface and I/O peripheral hardware.The double-core system overriding concern of resource sharing be the problem of resource sharing, resources shared can be visited by two processors.Which resource in the decision systems is shared, and how to use this resource between the different processor jointly be very crucial problem.Promptly two CPU of exploitation examine on a chip, and the dual-cpu structure schematic diagram is shown in 3.Wherein CPU_1 is a host CPU, and CPU_2 makes stand-by heat.Like this when faults such as CPU_1 generation deadlock, arbitration nuclear abitrator does not receive the regular pulse signal of CPU_1, arbitration nuclear just will encourage it by work_1, if still there is not back-signalling, arbitration nuclear just will join token to CPU_2, and while switchable memory interface, as stack (Stack), heap (Heap), variable storage district (R/W data), constant memory block (RO data), program entity district (Text) interface all seamlessly switches to CPU_2, other is as the IO mouth, interface controllers etc. all switch to CPU_2, CPU_2 has accepted work and has continued operation, to guarantee the normal operation of wastewater treatment electric-control system.Here researched and developed 3 technology, hardware link is switched nuclear, and storage resources is shared, and the double-core arbitration mechanism realizes active and standby seamless standby.
(1) hardware link is switched nuclear
When faults such as CPU_1 generation deadlock, arbitration nuclear abitrator does not receive the regular pulse signal of CPU_1, arbitration nuclear just will encourage it by work_1, if still there is not back-signalling, arbitration nuclear just will join token to CPU_2, and switches internal bus interface simultaneously (comprising data bus data and address bus addr).
(2) storage resources is shared
Storage resources is realized mapping fully as stack (Stack), heap (Heap), variable storage district (R/W data), constant memory block (RO data), program entity district (Text).
(3) double-core arbitration mechanism
Arbitration nuclear abitrator does not receive the regular pulse signal of CPU_1, arbitrates nuclear and just will encourage it by work_1, if still there is not back-signalling, arbitration nuclear just will join token to CPU_2, and while switchable memory interface.
Claims (3)
1, a kind of wastewater treatment electric-control system based on the SOPC technology is characterized in that: be made up of cpu motherboard module, several daughter boards IO expansion relays, several daughter boards IO expansion module and the two poles of the earth private bus; The cpu motherboard module is carried out two-way the connection with several daughter boards IO expansion relays by private bus, and each daughter board IO expansion relays is carried out two-way the connection by private bus with several daughter boards IO expansion module; Above-mentioned cpu motherboard module is integrated among the FPGA by several IP kernels; The IP kernel main body module is made up of two CPU main preparation system structures, Profibus controller, TCP/IP controller, RS232 serial communication controller and dedicated bus interface controller; Two CPU main preparation system structures are respectively with Profibus controller, TCP/IP controller, RS232 serial communication controller with the dedicated bus interface controller is two-way is connected; Wherein, two CPU main preparation system structures are made up of CPU1, CPU2, token moderator arbitrator, internal bus buffering switch mul, storage unit SRAM, FLASH and IO interface; The output signal of enlivening of CPU1 is connected with the input port of token moderator arbitrator, the token output port of token moderator arbitrator is connected with the input port of CPU1, the output signal of enlivening of CPU2 is connected with the input port of token moderator arbitrator, and the token output port of token moderator arbitrator is connected with the input port of CPU2; CPU1 carries out two-way the connection by internal bus buffering switch mul with storage unit SRAM, FLASH and IO interface respectively with CPU2.
2, the wastewater treatment electric-control system based on the SOPC technology according to claim 1 is characterized in that: above-mentioned token moderator arbitrator is made up of timer, watchdog circuit, arbitration seeker, alarm and token follower; Watchdog circuit receives the output signal of timer, CPU1, CPU2, and is entered into the input end of arbitration seeker, and arbitration seeker output terminal is connected with the token follower with alarm respectively.
3, the wastewater treatment electric-control system based on the SOPC technology according to claim 1 is characterized in that: above-mentioned CPU1, CPU2 adopt the soft nuclear flush bonding processor of the second generation NIOS II of altera corp.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810053176A CN101587342B (en) | 2008-05-21 | 2008-05-21 | Sewage treatment electronic control system based on SOPC technique |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810053176A CN101587342B (en) | 2008-05-21 | 2008-05-21 | Sewage treatment electronic control system based on SOPC technique |
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| CN101587342A true CN101587342A (en) | 2009-11-25 |
| CN101587342B CN101587342B (en) | 2012-10-03 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107942797A (en) * | 2017-11-29 | 2018-04-20 | 上海无线电设备研究所 | Embedded dual core servo controller and its design method based on SOPC |
| CN109144732A (en) * | 2018-09-05 | 2019-01-04 | 合肥英睿系统技术有限公司 | A kind of multi-core CPU implementation method and relevant apparatus based on FPGA |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6298393B1 (en) * | 1998-09-30 | 2001-10-02 | Rockwell Technologies, Llc | Industrial control systems having input/output circuits with programmable input/output characteristics |
| US6711629B1 (en) * | 1999-10-18 | 2004-03-23 | Fisher-Rosemount Systems, Inc. | Transparent support of remote I/O in a process control system |
| CN1154615C (en) * | 2000-09-22 | 2004-06-23 | 北京中环康裕环保工程技术有限公司 | Automatic controller for sewage treatment process |
| CN2828173Y (en) * | 2005-09-09 | 2006-10-18 | 商学业 | Sewage treatment system |
-
2008
- 2008-05-21 CN CN200810053176A patent/CN101587342B/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107942797A (en) * | 2017-11-29 | 2018-04-20 | 上海无线电设备研究所 | Embedded dual core servo controller and its design method based on SOPC |
| CN107942797B (en) * | 2017-11-29 | 2020-12-22 | 上海无线电设备研究所 | Embedded dual-core servo controller based on SOPC and design method thereof |
| CN109144732A (en) * | 2018-09-05 | 2019-01-04 | 合肥英睿系统技术有限公司 | A kind of multi-core CPU implementation method and relevant apparatus based on FPGA |
| CN109144732B (en) * | 2018-09-05 | 2022-02-11 | 合肥英睿系统技术有限公司 | Multi-core CPU (Central processing Unit) implementation method based on FPGA (field programmable Gate array) and related device |
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| CN101587342B (en) | 2012-10-03 |
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Effective date of registration: 20120925 Address after: 300222 Liu Lindong, Tianjin, Hexi District Patentee after: Tianjin Engineering Normal College Patentee after: Tianjin Yitong Electrical Technology Development Group Limited Address before: 300222 Liu Lindong, Tianjin, Hexi District Patentee before: Tianjin Engineering Normal College |
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