CN107942797B - Embedded dual-core servo controller based on SOPC and design method thereof - Google Patents
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Abstract
The invention provides an embedded dual-core servo controller based on an SOPC (system on programmable chip) and a design method thereof.A hardware architecture comprises an FPGA (field programmable gate array), a power supply system, a program FLASH, a data FLASH, a driver, a data instruction communication unit, a sensor data reading unit and the like which are in signal connection with the FPGA, wherein the FPGA is provided with two Microblaze soft-core processors for dual-core parallel calculation; the plurality of IP soft cores are in signal connection through PLB buses, and each Microblaze soft core processor performs data interaction with each IP soft core through the PLB buses; and dual-core data communication is carried out between the two Microblaze soft-core processors. Determining a hardware architecture and an interface type according to the functional requirements of a control system, then determining a software bottom architecture, compiling by using an XPS tool, exporting a top interface file, and designing and developing a top soft core controller in an SDK platform. The invention improves the cooperative processing capability of the controller and has the advantages of rich resources, strong expandability, high reliability, low cost and easy design.
Description
Technical Field
The invention relates to the field of digital servo control systems, in particular to an embedded dual-core servo controller based on an SOPC (system on programmable chip) and a design method thereof.
Background
At present, a hardware platform of a digital servo controller mainly comprises three architectures of DSP, DSP + FPGA and FPGA, the DSP-based servo controller has the advantages of flexible design and convenience in debugging, but the peripheral resources are limited, the DSP-based servo controller cannot meet the requirements of high-speed parallel processing of various communication interfaces at present, even if an F28M35 dual-core processor is released by TI companies, the defect cannot be changed, the DSP + FPGA-based servo controller can meet the requirements of flexible design and parallel communication at the same time, but the circuit is complex and the cost is high. In recent years, with the development of microelectronic technology, on-chip programmable technology is gradually emerging, a soft core or a hard core processor can be embedded in an FPGA, functions required by system design such as a processor, a memory, an I/O interface and the like are integrated on a programmable logic device FPGA, so that an on-chip programmable System (SOPC) is formed, all functions of a DSP and an FPGA controller can be realized by adopting a controller based on a single FPGA, and the system is widely applied to the fields of aerospace and aviation.
With the increase of the task quantity, the problem that the access to a memory cannot be performed simultaneously and the system is easily confused under the condition of high-speed operation exists in an FPGA embedded single-core system of the FPGA, the FPGA of Xilinx company provides a dual-core system, namely two on-chip microprocessor soft cores Microblaze (a 32-bit microprocessor with strong functions and optimized aiming at Xilinx FPGA devices and the fastest soft processor IP core solution in the industry) can be embedded in one FPGA to perform multi-task cooperation and parallel calculation, and the response speed of the system is greatly improved.
In recent years, researchers at home and abroad have conducted a lot of research on an embedded system based on an FPGA, and the dawn of the university of Harbin industry introduces several methods for communication between dual cores in the context of 'design of an embedded dual-core system based on an FPGA'. The Baiyu of Nanjing science and technology provides a design scheme of an embedded control system based on a platform of Virtex-5FXT FPGA (field programmable gate array) of Xilinx company, wherein the design scheme is mainly based on research related to development and application of VxWorks software of an embedded real-time operating system, and a PowerPC440 hard core processor is mentioned in the text and does not adopt a Microblaze soft core processor. The Yao Ming of Xian university provides a Virtex-II Pro development board based on Xilinx to realize the construction of a dual-core embedded system in the 'dual-core embedded system construction based on FPGA' and provides a construction method and a principle of the dual-core system, and the construction method mainly adopts a hard core processor framework of PowerPC 405.
In the patent application "autonomous configuration method of embedded dual-core system based on FPGA" (CN201410047913.9), the problem of autonomous configuration and loading of the dual-core system is proposed. The patent application "embedded dual-core relay protection system based on FPGA" (cn201510107412.x) proposes a dual-core design method based on an NIOS II soft-core processor. The patent application "a robot vision control method and a robot controller and a robot control system" (CN201610122709.8) proposes the application of an embedded dual-core microprocessor in image processing and motion control. In the prior art, no design method related to an embedded dual-core antenna servo controller based on SOPC is found.
At present, a single-core digital servo control system based on an FPGA adopts a single main thread, and multi-task scheduling needs to adopt a mode of inquiry or interruption, so that the waiting time in a blocking state is prolonged, the period of data updating is prolonged, and parallel processing in an absolute sense is avoided. In the case of the practical problems of multitasking, large data volume and the like, the disadvantages of long execution time and incapability of parallel processing of the single-core processor are gradually revealed, and the real-time performance and the algorithm precision of control cannot be guaranteed.
Disclosure of Invention
In order to solve the problems in the prior art, the invention aims to provide an embedded dual-core servo controller based on an SOPC, which improves the cooperative processing capability of the controller and has the advantages of rich resources, strong expandability, high reliability, low cost and easy design. The invention also provides a design method of the embedded dual-core servo controller based on the SOPC.
In order to achieve the above object, an embodiment of the present invention provides an embedded dual-core servo controller based on an SOPC, comprising:
the FPGA is used as a main controller, and the following modules are in signal connection with the FPGA:
the power supply system supplies power to the FPGA and other modules;
the program FLASH stores the program for the FPGA to read the program;
the data FLASH stores the control parameters for the FPGA to read the control parameters;
the data instruction communication unit is used for realizing data instruction communication between the FPGA and an external device;
the sensor data reading unit is used for acquiring sensor data and providing the sensor data to the FPGA;
the driver drives the execution device according to the driving signal provided by the FPGA;
the FPGA is provided with two Microblaze soft core processors for dual-core parallel computation; the plurality of IP soft cores are in signal connection through PLB buses, and each Microblaze soft core processor performs data interaction with each IP soft core through the PLB buses; and dual-core data communication is carried out between the two Microblaze soft-core processors.
Preferably, the first soft-core processor Microblaze0 receives and sends data instructions, reads sensor data and preprocesses the data instructions, and shares the data with the second soft-core processor Microblaze1 through dual-core data communication; the second soft core processor Microblaze1 is electrified to read control parameters, the calculation of a servo control algorithm is completed according to shared data, and a driving signal is sent to a driver, so that the established function of the servo system is realized.
Preferably, the first soft-core processor Microblaze0 interacts data with the timer IP core, the interrupt control IP core and the sensor reading IP core through the first PLB bus; the second soft-core processor Microblaze1 interacts data with the timer IP core, the interrupt control IP core, the data instruction reading IP core, the driver control IP core and the control parameter storage IP core through a second PLB bus.
Preferably, the dual-core data communication between the two Microblaze soft-core processors is realized based on a Shared BRAM or MailBox mode.
Preferably, the Shared BRAM mode also arbitrates by mutually exclusive access to the IP core Mutex.
Preferably, when the data sharing amount is larger than 1000 bytes, the dual-core data communication selects a Shared BRAM mode, otherwise, the dual-core data communication selects Mailbox.
Another technical solution of the present invention is to provide a design method of an embedded dual-core servo controller based on an SOPC, which is suitable for any one of the above embedded dual-core servo controllers based on an SOPC.
Preferably, the design method comprises the steps of:
s1, constructing a control loop according to the requirement of the established function of the servo system;
s2, determining a hardware architecture of the embedded dual-core servo controller according to the control loop, wherein the hardware architecture comprises an FPGA, and a power supply system, a program FLASH, a data FLASH, a driver, a data instruction communication unit and a sensor data reading unit which are in signal connection with the FPGA;
s3, determining an IP soft core required by the bottom layer of the embedded dual-core servo controller according to a hardware architecture and a control strategy, wherein the IP soft core comprises a timer IP core, an interrupt control IP core, a sensor reading IP core, a data instruction reading IP core, a driver control IP core and a control parameter storage IP core; each IP soft core opens corresponding data port to connect with PLB bus;
s4, building a bottom layer software platform based on the IP soft core in the XPS:
according to the selected FPGA model, a bottom layer software platform with two Microblaze soft-core processors is created; adding an IP soft core into a bottom layer software platform to be connected with a PLB bus, distributing an internal clock, an external port and an address, and compiling a bottom layer software architecture;
and S5, exporting a top interface file to the SDK for top-level development of the control system after the bottom-level architecture of the software built by the XPS is compiled.
The invention provides an embedded dual-core servo controller based on SOPC and a design method thereof, wherein a dual MicroBlaze soft core processor based on an FPGA of Xilinx (Sailing corporation) is adopted to complete the parallel calculation and the cooperative work of a digital controller, improve the running speed and realize high-precision, high-real-time, multi-task and other high-requirement servo control.
Determining a hardware architecture and an interface type according to the functional requirements of a control system, then determining a software bottom architecture, compiling by using an XPS tool, exporting a top interface file, and designing and developing a top soft core controller in an SDK platform.
The invention brings the following beneficial effects:
(1) high real-time performance: according to the design method, two Microblaze embedded soft-core processors are adopted, synchronous operation of a control algorithm and data preprocessing can be achieved, and instantaneity is greatly improved.
(2) The cost is low: the design method adopts a single FPGA to realize all functions of the original DSP + FPGA scheme, and can realize low-cost design.
(3) The flexibility is high: the embedded system Microbalze operation control algorithm and data preprocessing are adopted, online operation debugging can be realized, operation data can be monitored, and the complicated debugging mode of the traditional FPGA is changed. Moreover, the control parameters can be electrically read, and can be flexibly adjusted according to the difference of the servo system.
(4) The stability is good: experiments prove that the system can still stably run under repeated electrification, long-time high-low temperature environment tests and vibration tests.
Drawings
FIG. 1 is a schematic diagram of a hardware architecture of an embedded dual-core servo controller based on an SOPC;
FIG. 2 is a diagram of a parameterized debugging hardware platform of a dual-core architecture in the present invention;
FIG. 3 is a schematic diagram of the process of the present invention for changing the parameters of the state machine based controller;
FIG. 4 is a schematic view of a stabilization loop of an angular rate gyroscopically stabilized platform in an embodiment of the present invention;
FIG. 5 is a diagram illustrating a hardware architecture of an angular rate gyroscopically stabilized platform in an embodiment of the present invention;
FIG. 6 is a diagram illustrating the underlying software architecture of an angular rate gyroscopic stabilization platform in an embodiment of the present invention.
Detailed Description
The dual-core control system based on the SOPC is based on an FPGA of Xilinx company as a core processor, and realizes dual-core parallel computation of a digital controller by utilizing two MicroBlaze soft core processors on a chip. The FPGA contains abundant logic design resources, can complete complex logic and data processing functions, and has the advantages of repeatable programming, short design period, low research and development cost and the like.
The hardware architecture of the dual-core control system based on the SOPC is shown in FIG. 1 and comprises an FPGA main controller, a power supply system, a program FLASH, data instruction communication, a sensor data reading unit, a driver, a data FLASH and the like. The power supply system mainly provides power for the FPGA and other modules, the program FLASH is mainly used for storing programs, the data FLASH is mainly used for storing control parameters, the driver is mainly used for driving the execution device, and the FPGA main controller is used for finishing the functions of reading programs, sensor data, operating control algorithms, outputting driving signals and the like.
An internal software architecture of a dual-core control system FPGA is shown in FIG. 2 and comprises two Microblaze soft-core processors, dual-core data communication is realized based on Shared BRAM (Shared memory mode) or MailBox (MailBox), a memory IP core, a timer IP core, an interrupt control IP core, an external function IP core, a data instruction communication IP core, a driver control IP core, a control parameter storage IP core and the like, the IP soft cores are connected through PLB buses, and the Microblaze soft-core processors perform data interaction with the soft cores through PLB buses.
Currently, FPGA dual-core communication mainly comprises 2 modes: shared BRAM and Mailbox. The dual-core communication mode based on Shared BRAM is relatively simple, is suitable for the situation of large data volume sharing, has high reading speed and is simple to realize, but the two Microblaze processors have the situation of simultaneous reading and writing, and must arbitrate through an internal Mutex (provided by XPS for processing the mutual exclusion access IP core of the multithread work for sharing resources) to realize the mutual exclusion access, and the dual-core does not have real-time data exchange. The soft core based on the Mailbox establishes communication between the two soft cores, and each Mailbox is provided with a data sending FIFO and a data receiving FIFO, so that data can be directly interacted in real time, and the method is suitable for frequent data frame exchange. The above two communication methods have advantages and disadvantages, and the present invention is not limited to which method is used for data communication. In a preferred example, the selection can be made according to the data sharing amount, if the data sharing amount is larger than 1000 bytes, the Shared BRAM is selected, otherwise, the Mailbox is recommended to be selected.
The operation scheme of the dual-core control system based on the SOPC is shown in FIG. 3, the stable realization of the control algorithm in the servo control field is established on the time domain operation of a fixed period T, and the control period is far shorter than the response period of the servo system. In the field of high-precision, high-real-time and multi-task servo control, in order to obtain higher calculation precision of a controller, the control period is required to be very short, and sensor preprocessing and a complex control algorithm consume a large amount of operation time at the same time, so that a dual-core system is required to be adopted to better solve the problems.
The soft core Microblaze0 is used for sensor reading and instruction receiving and sending functions, data preprocessing is carried out according to requirements, and data are Shared with the soft core Microblaze1 through a Mailbox or a Shared RAM; the soft core Microblaze1 is electrified to read control parameters, the calculation of a servo control algorithm is completed according to shared data, and a driving signal is sent to a driver, so that the established function of the servo system is realized.
Taking a two-axis high-precision space-stabilized platform as an example, the design method of the embedded dual-core servo controller based on the SOPC provided by the invention is described in detail as follows:
1. constructing a control loop according to the functional requirements of the servo system
The construction of the control loop is determined according to different control function requirements, and the stable loop of the current angular rate gyro type stable platform is mainly formed by a controller Gc(s) comprises a motor power amplifier, a motor and a driving mechanism G(s) of the mechanism, a rate gyro T(s), a tachometer and the like, and is shown in figure 4. An inner loop formed by a tachometer is mainly used for improving the rigidity of the system, and an outer loop formed by a rate gyro is mainly used for isolating disturbance and realizing space stability.
2. Determining an overall hardware controller architecture based on a control loop
According to the constructed control loop and the hardware architecture of the controller, as shown in fig. 5, based on the FPGA, RS422 is used for data instruction communication, AD signal reading is performed on the tachometer, signal reading is performed on the gyro by RS422, a PWM signal is output to the driver, and SPI signal reading and writing are performed with data Flash. In this embodiment, the problems of selecting a tachometer, a driver type, a gyro interface type, and the like are not discussed, and the problems can be solved according to the known technology in the art.
3. Determining IP soft core needed by bottom layer according to whole hardware controller structure and control
From the controller hardware architecture, it can be determined that the underlying software architecture of the controller requires: as shown in fig. 6, because the data communication and sensor data amount mentioned in the present example does not exceed 1000 bytes, the communication mode between the two cores is the Mailbox mode. And opening a corresponding data port to be connected with the PLB bus according to the requirement in the writing process of the IP soft core.
4. Building bottom layer software platform based on IP soft core in XPS
XPS (Xilinx Platform studio) is a programming tool based on an IP soft core provided by Xilinx corporation, a bottom layer double Microblaze Platform is created through XPS according to a selected FPGA model, the IP soft core is added into the XPS Platform according to a software architecture determined in fig. 6, the XPS Platform is connected to a PLB bus, an internal clock and an external port are distributed, then an address is distributed, and the bottom layer software architecture is compiled.
5. Control system design in SDK
SDK (software development kit) is an embedded platform development tool provided by Xilinx corporation, is mainly used for specific implementation and algorithm of a development system, and is convenient and flexible to debug. After the software bottom framework built by the XPS is compiled, the software bottom framework can be exported to an SDK platform for top-level development. The design method of the IP core is not described herein.
As shown in fig. 3, the soft core Microblaze0 completes gyro data reading and tachometer data reading during timer interruption, performs data preprocessing, and performs data interaction with the Microblaze1 through a Mailbox; the Microblaze1 mainly completes data interaction with Microblaze0, control algorithm operation, drive control and parameter reading and storing in timer interruption.
Microblaze1 timer interrupt period T1Mainly determined by the response characteristics of the control loop, the following formula should be satisfied:
T≤1/10/fbw
in the formula fbwThe response bandwidth required by the control system.
Microblaze0 timer interrupt period T0Is T1More than 2 times of the total weight of the composition.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (6)
1. An embedded dual-core servo controller based on SOPC is characterized by comprising:
the FPGA is used as a main controller, and the following modules are in signal connection with the FPGA:
the power supply system supplies power to the FPGA and other modules;
the program FLASH stores the program for the FPGA to read the program;
the data FLASH stores the control parameters for the FPGA to read the control parameters;
the data instruction communication unit is used for realizing data instruction communication between the FPGA and an external device;
the sensor data reading unit is used for acquiring sensor data and providing the sensor data to the FPGA;
the driver drives the execution device according to the driving signal provided by the FPGA;
the FPGA is provided with two Microblaze soft core processors for dual-core parallel computation; the plurality of IP soft cores are in signal connection through PLB buses, and each Microblaze soft core processor performs data interaction with each IP soft core through the PLB buses; carrying out dual-core data communication between the two Microblaze soft-core processors;
the first soft-core processor Microblaze0 receives and sends data instructions, reads sensor data and preprocesses the data in timer interruption, and shares the data with the second soft-core processor Microblaze1 through dual-core data communication; the second soft-core processor Microblaze1 is powered on to read control parameters, the calculation of a servo control algorithm is completed according to shared data in timer interruption, and a driving signal is sent to a driver, so that the established function of a servo system is realized;
the first soft-core processor Microblaze0 interacts data with the timer IP core, the interrupt control IP core and the sensor reading IP core through a first PLB bus; the second soft-core processor Microblaze1 interacts data with the timer IP core, the interrupt control IP core, the data instruction reading IP core, the driver control IP core and the control parameter storage IP core through a second PLB bus;
period T of timer interrupt of Microblaze1 of second soft-core processor1Determined by the response characteristics of the control loop, the following equation is satisfied:
T1≤1/10/fbw
in the formula (f)bwControlling the response bandwidth required by the system;
period T of timer interrupt of first soft core processor Microblaze00Is T1More than 2 times of the total weight of the composition.
2. The SOPC-based embedded dual-core servo controller of claim 1, wherein dual-core data communication between two Microblaze soft-core processors is implemented based on a Shared BRAM or MailBox approach.
3. The SOPC-based embedded dual-core servo controller of claim 2, wherein the Shared BRAM mode further arbitrates by mutually exclusive access to the IP core Mutex.
4. The SOPC-based embedded dual-core servo controller of claim 3,
when the data sharing quantity is larger than 1000 bytes, the dual-core data communication selects a Shared BRAM mode, otherwise, the dual-core data communication selects a Mailbox.
5. A design method of an embedded dual-core servo controller based on SOPC is characterized by comprising the following steps:
s1, constructing a control loop according to the requirement of the established function of the servo system;
s2, determining a hardware architecture of the embedded dual-core servo controller according to the control loop, wherein the hardware architecture comprises an FPGA, and a power supply system, a program FLASH, a data FLASH, a driver, a data instruction communication unit and a sensor data reading unit which are in signal connection with the FPGA;
s3, determining an IP soft core required by the bottom layer of the embedded dual-core servo controller according to a hardware architecture and a control strategy, wherein the IP soft core comprises a timer IP core, an interrupt control IP core, a sensor reading IP core, a data instruction reading IP core, a driver control IP core and a control parameter storage IP core; each IP soft core opens corresponding data port to connect with PLB bus;
s4, building a bottom layer software platform based on the IP soft core in the XPS:
building a bottom layer software platform with two Microblaze soft-core processors according to the selected FPGA model; adding the IP soft cores to a bottom layer software platform to be connected with a PLB bus, carrying out data interaction on each Microblaze soft core processor and each IP soft core through the PLB bus, distributing an internal clock, an external port and an address, and carrying out bottom layer software architecture compiling;
the dual-core data communication is carried out between the two Microblaze soft-core processors based on a Shared BRAM or MailBox mode;
s5, exporting a top interface file to the SDK for top-level development of the control system after the bottom-level architecture of the software built by the XPS is compiled;
the method comprises the following steps that a first soft-core processor Microblaze0 interacts data with a timer IP core, an interrupt control IP core and a sensor reading IP core, data instruction receiving and sending, sensor data reading and preprocessing are carried out in timer interrupt, and data are shared with a second soft-core processor Microblaze1 through dual-core data communication;
the second soft-core processor Microblaze1 interacts data with the timer IP core, the interrupt control IP core, the data instruction reading IP core, the driver control IP core and the control parameter storage IP core, the control parameter is electrically read, the calculation of a servo control algorithm is completed according to shared data in the timer interrupt, and a driving signal is sent to the driver, so that the set function of the servo system is realized;
wherein, the second soft core processor Microblaze1 timer interrupt period T1Determined by the response characteristics of the control loop, the following equation is satisfied:
T1≤1/10/fbw
in the formula (f)bwControlling the response bandwidth required by the system;
period T of timer interrupt of first soft core processor Microblaze00Is T1More than 2 times of the total weight of the composition.
6. The design method of the embedded dual-core servo controller based on the SOPC as claimed in claim 5, wherein,
when the data sharing amount is larger than 1000 bytes, the Shared BRAM mode is selected for dual-core data communication between the two Microblaze soft-core processors, and otherwise, the Mailbox is selected.
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