CN110543444A

CN110543444A - Multi-processor information processing circuit based on SiP technology

Info

Publication number: CN110543444A
Application number: CN201910675518.8A
Authority: CN
Inventors: 林益锋; 何浩; 杨健; 张晓澈; 阮忠园; 蒋凯
Original assignee: Shanghai Aerospace Control Technology Institute
Current assignee: Shanghai Aerospace Control Technology Institute
Priority date: 2019-07-25
Filing date: 2019-07-25
Publication date: 2019-12-06

Abstract

The invention discloses a multi-processor information processing circuit based on an SiP technology, which integrates a DSP (digital signal processor), an external memory and an FPGA (field programmable gate array) into a single chip by adopting a bare chip stacking mode; the user interface IP interconnects the DSP bus with Microblaze in the FPGA, distributed operation is realized through multiple groups of instantiations, and the DSP is connected with an external memory SRAM and a FLASH through an EMIF; the FPGA chip is connected with a configuration chip; the DSP and the FPGA are connected through the same EMIF. Compared with the prior art, the invention has the following advantages: (1) by adopting the SiP technology, the circuit bare cores are stacked and integrated, and the required volume and mass are obviously reduced. (2) The microbize soft core is used as a plurality of parallel processors, the number can be flexibly adjusted without increasing extra hardware cost.

Description

Multi-processor information processing circuit based on SiP technology

Technical Field

The invention belongs to the technical field of SiP, mainly relates to hardware and software integration of a digital processor, a memory and a Microblaze soft core, and particularly relates to a multiprocessor information processing circuit based on the SiP technology.

Background

With the requirement for light weight and miniaturization of missiles becoming higher and higher, the reduction of the mass and volume of a flight control platform is imperative.

In the prior art, a method for improving data processing capability is to add chips of a digital processor, and the increase of computing power is achieved by increasing hardware, and the cost of the method is undoubtedly increased along with the increase of the number of chips.

Disclosure of Invention

In order to improve the operational capability of the digital processing system, the DSP, the external memory thereof and the FPGA are integrated into a single chip by adopting a bare chip stacking mode; the user interface IP interconnects the DSP bus with Microblaze in the FPGA, and distributed operation is realized through multiple groups of instantiations. The method focuses on increasing the soft cores in the FPGA, and achieves the purpose of improving the computing capacity through the parallel soft cores.

The invention adopts the following technical scheme: a multiprocessor information processing circuit based on the SiP technology integrates a DSP, an external memory and an FPGA into a single chip by adopting a bare chip stacking mode; the user interface IP interconnects the DSP bus with Microblaze in the FPGA, and distributed operation is realized through multiple groups of instantiations; the DSP is connected with the external memory SRAM and the FLASH through the EMIF; the FPGA chip is connected with a configuration chip; the DSP and the FPGA are connected through the same EMIF.

Furthermore, the digital processor circuit adopts two pieces of 256 Mx 16b SRAM connected in parallel to realize parallel 32b storage, and uses an external chip selection signal TCE0nA of the DSP.

Further, a 1 Mx 16b FLASH is adopted to realize parallel 16b storage, and an external chip selection signal TCE1nA of the DSP is used; an FPGA uses external chip selection signals TCE2nA and TCE3nA of the DSP; EMIF adopts asynchronous read-write mode; a PROM configuration chip is set to be in a parallel data loading mode.

Further, the user interface IP is connected to the EMIF of the DSP and the PLB bus of Microblaze, and includes a data buffer for data exchange between the DSP and the Microblaze.

Further, the processing circuit may instantiate one or more Microblaze soft cores, each soft core being provided with a user interface IP; each soft core receives the same or different data of the DSP, performs data operation by the same or different built-in programs, and feeds back the result to the DSP to realize parallel distributed data operation.

Compared with the prior art, the invention has the following advantages:

(1) by adopting the SiP technology, the circuit bare cores are stacked and integrated, and the required volume and mass are obviously reduced.

(2) The microbize soft core is used as a plurality of parallel processors, the number can be flexibly adjusted without increasing extra hardware cost.

drawings

The invention will be further explained with reference to the drawings and examples.

FIG. 1 is a block diagram of a SiP technology based multiprocessor information processing circuit of the present invention;

FIG. 2 is a schematic diagram of the DSP EMIF of the present invention;

FIG. 3 is a schematic diagram of the SRAM and FLASH connection of the present invention;

FIG. 4 is a schematic diagram of a PROM configuration chip connection of the present invention;

Figure 5 is a schematic block diagram of the user interface and Micorblaze of the present invention.

Detailed Description

Embodiments of the present invention are described below with reference to the accompanying drawings:

The invention discloses a multi-processor information processing circuit based on an SiP technology, which integrates a DSP (digital signal processor), an external memory and an FPGA (field programmable gate array) into a single chip by adopting a bare chip stacking mode; the user interface IP interconnects the DSP bus with Microblaze in the FPGA, and distributed operation is realized through multiple groups of instantiations; the DSP is connected with the external memory SRAM and the FLASH through the EMIF; the FPGA chip is connected with a configuration chip; the DSP and the FPGA are connected through the same EMIF.

Referring to fig. 1, the digital processor DSP adopts FT-C6713, SRAM adopts JM64LV25616, FLASH adopts SM29LV160, FPGA adopts JXCSX95T, PROM adopts JXQF 32P.

Referring to FIG. 2, U2A is the EMIF portion of the DSP, including address bus TEA _ A [2..21], data bus TD _ A [0..31], chip select signals TCE0nA TCE3nA, byte enable signals TBE0nA TBE3nA, and control signals TREA, TOEA, TWEA.

Referring to FIG. 3, where U7, U8 are 2-slice SRAMs, U7 is connected only to TD _ A [0..15], TBE0nA, TBE1nA for storing low 16b, U8 is connected only to TD _ A [16..31], TBE2nA, TBE3nA for storing high 16b, and the two chips share TEA _ A [2..21], TREA, TOEA and TWEA. U6 is FLASH, and is connected with TEA _ A [2..21], TD _ A [0..15], TREA, TOEA and TWEA.

Referring to fig. 4, U7 is a PROM configuration chip, D0-D7 are parallel data output pins, OE, CE _ n, CF _ n, and CLK respectively correspond to INIT _ B, DONE, PROGRAM _ B, and CCLK of the FPGA, and TDI, TDO, TMS, and TCK are connected to the JTAG port of the FPGA.

Referring to fig. 5, the bus interface IP includes a logic control unit and a data storage area, the logic control unit decodes the EMIF of the DSP and the PLB bus of Microblaze, stores the data lines of the two sets of buses in the data storage area, and waits for reading from the opposite end.

the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and any simple changes or equivalent substitutions of the technical solutions that can be made obvious by those skilled in the art within the technical scope of the present invention are within the scope of the present invention.

Claims

1. A multiprocessor information processing circuit based on SiP technology is characterized in that: integrating the DSP, the external memory thereof and the FPGA into a single chip by adopting a bare chip stacking mode; the user interface IP interconnects the DSP bus with Microblaze in the FPGA, and distributed operation is realized through multiple groups of instantiations; the DSP is connected with the external memory SRAM and the FLASH through the EMIF; the FPGA chip is connected with a configuration chip; the DSP and the FPGA are connected through the same EMIF.

2. the SiP-based multiprocessor information processing circuit of claim 1, wherein: parallel 32b storage is realized by adopting two pieces of 256 Mx 16b SRAM in parallel, and an external chip selection signal TCE0nA of the DSP is used.

3. The SiP-technology-based multiprocessor information processing circuit according to claim 2, wherein: parallel 16b storage is realized by using a piece of 1 Mx 16b FLASH, and an external chip selection signal TCE1nA of the DSP is used.

4. the SiP-based multiprocessor information processing circuit of claim 3, wherein: an FPGA is adopted to use external chip selection signals TCE2nA and TCE3nA of the DSP; EMIF adopts asynchronous read-write mode; a PROM configuration chip is set to be in a parallel data loading mode.

5. The SiP-technology-based multiprocessor information processing circuit according to claim 4, wherein: the user interface IP is connected with the EMIF of the DSP and the PLB bus of the Microblaze, and the user interface IP comprises a data cache area for data exchange between the DSP and the Microblaze.

6. The SiP-technology-based multiprocessor information processing circuit according to claim 4, wherein: single or multiple Microblaze soft cores can be instantiated, and each soft core is provided with a user interface IP; each soft core receives the same or different data of the DSP, performs data operation by the same or different built-in programs, and feeds back the result to the DSP to realize parallel distributed data operation.