CN107907811A - A kind of open-circuit structure test method for being used to extract double grid GaAs pHEMT device parasitic capacitances - Google Patents

Abstract

An open structure test method for extracting the parasitic capacitance of a double-gate gallium arsenide pHEMT device, comprising step 1: designing an open test structure, and establishing an equivalent circuit of the open test structure; the open test structure includes a double gate gallium arsenide pHEMT device The interconnection line (Interconnect) drawn from the port and the pad (PAD) that is in contact with the probe to apply a bias voltage; Step 2: Measure the three-port S-parameter of the open-circuit test structure; where the S-parameter (scattering parameter) of the open-circuit test structure uses the vector Network analyzer measurements. During the measurement, a vector network analyzer is used to measure the three-port S-parameters of the open circuit structure within the operating frequency range of the device. Step 3: Convert the S parameter measured in Step 1 into a Y parameter, and calculate the value of the parasitic capacitance through the Y parameter. Among them, the conversion of three-port S parameters into Y parameters is carried out through the s2y function in Matlab, and the representation method of Y parameters is obtained by using the equivalent circuit of the open circuit test structure.

Description

An open-circuit structure measurement for extracting parasitic capacitance of dual-gate GaAs pHEMT devices try method

technical field

The invention relates to the field of microwave device testing, and relates to a method for extracting an open-circuit test structure of the parasitic capacitance of a double-gate gallium arsenide pHEMT device.

technical background

Dual-gate devices are widely used in power amplifiers, phase shifters, mixers and monolithic microwave integrated circuits. In the traditional modeling method, the small-signal model is first established to facilitate the subsequent establishment of the large-signal model. Therefore, it is critical to accurately establish a small signal model.

For the small-signal model of a single-gate device, the most commonly used method is to fit the model's S-parameters to the measured S-parameters through numerical optimization. However, for the dual-gate GaAs pHEMT device, its small signal includes external parasitic parameters and two internal intrinsic parameters of the pHEMT, adding up to a total of 29 unknown parameters. Combining is very difficult. In fact, because the double-gate structure is different from the single-gate, it is difficult to directly apply the analysis method of the single-gate device to the double-gate device.

Deng et al [Deng W K, Chu T H.Elements extraction of GaAs dual-gateMESFET small-signal equivalent circuit[J].IEEE Transactions on Microwave Theory&Techniques,1998:2383-2390.] proposed a set of extraction of dual-gate external parasitic parameters and Flow of internal eigenparameters. Using the method of analysis, the value of the parasitic capacitance can be directly obtained by calculating the Y parameter measured under the condition that the device bias is at the cutoff and the test frequency is low frequency. In fact, the capacitance value obtained by this method of measuring at the device cut-off and low frequency usually has a certain change compared with the actual value, and some internal intrinsic parameters are very sensitive to changes in external parasitic parameters, which may make the extracted Internal eigenparameters are negative.

The single-gate open-circuit test structure has been widely used since it was first invented by Dr. Wijinen in 1987. The application of the single-gate test structure can accurately extract parasitic capacitance parameters. L Shen et al [Sun L, Gao J, Shen L. Direct Extraction of Equivalent Circuit Parameters for GaAs pHEMT[J].Journal ofComputational&Theoretical Nanoscience,2015,12(6):996-1001(6).]The effective frequency of small signal modeling is up to 110GHz by using analytical method and open circuit test structure method. It can be seen that the open-circuit test structure of the single-gate GaAs pHEMT device can achieve very good accuracy, however, no one has proposed the open-circuit test structure and method for the double-gate GaAs pHEMT device.

In order to overcome the above-mentioned shortcomings of the prior art, the present invention proposes an open-circuit test structure applied to a double-gate GaAs pHEMT device, which is used to extract the external parasitic capacitance of the double-gate GaAs pHEMT device.

Contents of the invention

The present invention overcomes the above-mentioned shortcomings of the prior art, and provides a method for directly and accurately extracting external parasitic capacitance applied to a double-gate gallium arsenide pHEMT device.

In order to achieve the above object, a kind of open-circuit structure testing method for extracting the parasitic capacitance of double-gate gallium arsenide pHEMT device provided by the present invention comprises the following steps:

Step 1: Design the open-circuit test structure and establish the equivalent circuit of the open-circuit test structure;

Step 2: measuring the three-port S-parameters of the open circuit test structure;

Step 3: Convert the S parameters measured in Step 2 into Y parameters, and calculate the value of the parasitic capacitance through the Y parameters.

In the first step, the designed open-circuit structure is shown in FIG. 2 , which is similar to the test structure of the device under test, but does not include the double-gate GaAs pHEMT device of the device under test. The open-circuit test structure includes an interconnection line (Interconnect) leading out the port of the double-gate GaAs pHEMT device and a pad (PAD) that is in contact with the probe to apply a bias voltage. The equivalent circuit of the open circuit test structure is shown in FIG. 3 , including a pad parasitic capacitance part 100 and an inter-pad coupling capacitance part 200;

The pad parasitic capacitance part 100 is composed of a first gate parasitic capacitance Cpg1, a second gate parasitic capacitance Cpg2 and a drain parasitic capacitance Cpd, wherein: one end of the first gate parasitic capacitance Cpg1 is connected to the first gate node G1 connected, the other end is connected to the first source node S; one end of the second gate parasitic capacitance Cpg2 is connected to the second gate node G2, and the other end is connected to the first source node S; the drain parasitic capacitance One end of Cpd is connected to the second drain node D, and the other end is connected to the first source node S;

The inter-pad coupling capacitance part 200 is composed of the coupling capacitance Cg1g2 between the first gate and the second gate, the coupling capacitance Cg1d between the first gate and the drain, and the coupling capacitance Cg2d between the second gate and the drain, Among them: one end of the coupling capacitance Cg1g2 between the first gate and the second gate is connected to the first gate node G1, and the other end is connected to the second gate node G2; the coupling capacitance Cg1d between the first gate and the drain One end of Cg2d is connected to the first gate node G1, and the other end is connected to the second drain node D; one end of the second gate-drain coupling capacitor Cg2d is connected to the second gate node G2, and the other end is connected to the second gate node G2. The second drain node D is connected.

In the second step, the S-parameter (scattering parameter) of the open circuit test structure is measured by using a vector network analyzer. During the measurement, a vector network analyzer is used to measure the three-port S-parameters of the open circuit structure within the working frequency range of the device, for example, 10MHz to 40GHz.

In the step 3, the three-port S parameter measured in the step 2 is converted into a Y parameter through the s2y function in Matlab. Obtain the Y parameter matrix from the equivalent circuit established in step 1, and obtain the value of each parasitic capacitance through the imaginary part of the Y parameter, the formula is as follows:

Y ₁₁ ＝jω(C _pg1 +C _pg1d +C _pg1g2 )

Y ₂₂ =jω(C _pg2 +C _pg2d )

Y ₃₃ ＝jω(C _pd +C _pg1d +C _pg2d )

Y ₁₂ ＝Y ₂₁ ＝-jωC _pg1g2

Y ₁₃ ＝Y ₃₁ ＝-jωC _pg1d

Y ₂₃ ＝Y ₃₂ ＝-jωC _pg2d

The accurate value of the parasitic capacitance can be obtained by calculating the Y parameter:

Among them, YPAD represents the admittance parameter of the equivalent circuit of the open circuit test structure, assuming that the port number of the first gate node G1 is 1, the port number of the second gate node G2 is 2, and the port number of the second drain node D is 3, then Y11, Y22, and Y33 represent the input admittance of ports 1, 2, and 3, respectively, Y12 represents the transfer admittance from port 2 to port 1, Y13 represents the transfer admittance from port 3 to port 1, and Y23 represents the transfer admittance from port 3 to port 2. transfer admittance.

Among them, Cpg1 represents the parasitic capacitance of the first gate, Cpg2 represents the parasitic capacitance of the second gate, Cpd represents the parasitic capacitance of the drain, Cg1g2 represents the coupling capacitance between the first gate and the second gate, and Cg1d represents the capacitance between the first gate and the drain. The inter-electrode coupling capacitance, Cg2d, represents the coupling capacitance between the second gate and the drain. The value of each parasitic capacitance can be obtained through the above calculation.

The beneficial effects of the present invention are:

The present invention aims at the inaccurate capacitance value and internal intrinsic parameters obtained by means of device cut-off and low-frequency measurement in the current method for directly extracting the parasitic capacitance of a double-gate gallium arsenide pHEMT device, and proposes a method for double-gate The parasitic capacitance extraction method of the open-circuit test structure of the GaAs pHEMT device. The parasitic capacitance extracted by this method has clear physical meaning, simple extraction method and high accuracy, and can effectively improve the accuracy of the small-signal model of the double-gate GaAs pHEMT device.

Description of drawings

Figure 1 is the small-signal equivalent circuit of a double-gate gallium arsenide pHEMT;

Fig. 2 is the used open circuit test structure of the present invention;

Fig. 3 is the equivalent circuit of the open circuit test structure;

Fig. 4 is the flow chart of extracting parasitic capacitance of open circuit test structure;

Detailed ways

The technical solutions in the examples of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the examples of the present invention. Without departing from the spirit and scope of the inventive concept, changes and advantages conceivable by those skilled in the art are all included in the present invention, and the scope of protection is defined by the appended claims. The process, conditions, experimental methods, etc. for implementing the present invention, except for the content specifically mentioned below, are common knowledge and common knowledge in this field, and the present invention has no special limitation content.

A kind of open-circuit structure testing method for extracting the parasitic capacitance of double-gate gallium arsenide pHEMT device provided by the present invention comprises the following steps:

Step 1: Design the open-circuit test structure and establish the equivalent circuit of the open-circuit test structure;

Step 2: measuring the three-port S-parameters of the open circuit test structure;

Step 3: Convert the S parameters measured in Step 2 into Y parameters, and calculate the value of the parasitic capacitance through the Y parameters.

In the first step, the designed open-circuit structure is shown in FIG. 2 , which is similar to the test structure of the device under test, but does not include the double-gate GaAs pHEMT device of the device under test. The open-circuit test structure includes an interconnection line (Interconnect) leading out the port of the double-gate GaAs pHEMT device and a pad (PAD) that is in contact with the probe to apply a bias voltage. The equivalent circuit of the open circuit test structure is shown in FIG. 3 , including a pad parasitic capacitance part 100 and an inter-pad coupling capacitance part 200;

The pad parasitic capacitance part 100 is composed of a first gate parasitic capacitance Cpg1, a second gate parasitic capacitance Cpg2 and a drain parasitic capacitance Cpd, wherein: one end of the first gate parasitic capacitance Cpg1 is connected to the first gate node G1 connected, the other end is connected to the first source node S; one end of the second gate parasitic capacitance Cpg2 is connected to the second gate node G2, and the other end is connected to the first source node S; the drain parasitic capacitance One end of Cpd is connected to the second drain node D, and the other end is connected to the first source node S;

The inter-pad coupling capacitance part 200 is composed of the coupling capacitance Cg1g2 between the first gate and the second gate, the coupling capacitance Cg1d between the first gate and the drain, and the coupling capacitance Cg2d between the second gate and the drain, Among them: one end of the coupling capacitance Cg1g2 between the first gate and the second gate is connected to the first gate node G1, and the other end is connected to the second gate node G2; the coupling capacitance Cg1d between the first gate and the drain One end of Cg2d is connected to the first gate node G1, and the other end is connected to the second drain node D; one end of the second gate-drain coupling capacitor Cg2d is connected to the second gate node G2, and the other end is connected to the second gate node G2. The second drain node D is connected.

In the second step, the S-parameter (scattering parameter) of the open circuit test structure is measured by using a vector network analyzer. During the measurement, a vector network analyzer is used to measure the three-port S-parameters of the open circuit structure within the working frequency range of the device, for example, 10MHz to 40GHz.

In the step 3, the three-port S parameter measured in the step 2 is converted into a Y parameter through the s2y function in Matlab. Obtain the Y parameter matrix from the equivalent circuit established in step 1, and obtain the value of each parasitic capacitance through the imaginary part of the Y parameter, the formula is as follows:

Y ₁₁ ＝jω(C _pg1 +C _pg1d +C _pg1g2 )

Y ₂₂ =jω(C _pg2 +C _pg2d )

Y ₃₃ ＝jω(C _pd +C _pg1d +C _pg2d )

Y ₁₂ ＝Y ₂₁ ＝-jωC _pg1g2

Y ₁₃ ＝Y ₃₁ ＝-jωC _pg1d

Y ₂₃ ＝Y ₃₂ ＝-jωC _pg2d

The accurate value of the parasitic capacitance can be obtained by calculating the Y parameter:

Among them, YPAD represents the admittance parameter of the equivalent circuit of the open circuit test structure, assuming that the port number of the first gate node G1 is 1, the port number of the second gate node G2 is 2, and the port number of the second drain node D is 3, then Y11, Y22, and Y33 represent the input admittance of ports 1, 2, and 3, respectively, Y12 represents the transfer admittance from port 2 to port 1, Y13 represents the transfer admittance from port 3 to port 1, and Y23 represents the transfer admittance from port 3 to port 2. transfer admittance.

Among them, Cpg1 represents the parasitic capacitance of the first gate, Cpg2 represents the parasitic capacitance of the second gate, Cpd represents the parasitic capacitance of the drain, Cg1g2 represents the coupling capacitance between the first gate and the second gate, and Cg1d represents the capacitance between the first gate and the drain. The inter-electrode coupling capacitance, Cg2d, represents the coupling capacitance between the second gate and the drain. The value of each parasitic capacitance can be obtained through the above calculation.

Claims (1)

1. a kind of open-circuit structure test method for being used to extract double grid GaAs pHEMT device parasitic capacitances, includes the following steps：

Step 1：Open test structure is designed, and establishes open test structure equivalent circuit；

Step 2：Measure three port S parameters of open test structure；

Step 3：The S parameter measured in step 2 is converted into Y parameter, parasitic capacitance is calculated by Y parameter Value；

In the step 1, open test structure is identical with the test structure of device under test, but not comprising tested double grid GaAs PHEMT devices；Open test structure include by double grid GaAs pHEMT device interfaces draw interconnection line Interconnect and With probe contact come the pad PAD that is biased；Open test structure equivalent circuit include pad parasitic capacitance portion (100) and Coupling capacitor part (200) between pad；

The pad parasitic capacitance portion (100) is by first grid parasitic capacitance Cpg1, second grid parasitic capacitance Cpg2 and leakage Pole parasitic capacitance Cpd is formed, wherein：One end of first grid parasitic capacitance Cpg1 is connected with first grid node G1, another End is connected with the first source node S-phase；One end of second grid parasitic capacitance Cpg2 is connected with second grid node G2, another End is connected with the first source node (S)；One end of drain parasitic capacitance Cpd is connected with the second drain node D, the other end with First source node S-phase connects；

Coupling capacitor part (200) is by coupled capacitor Cg1g2, first grid between first grid and second grid between the pad Coupled capacitor Cg2d is formed between coupled capacitor Cg1d and second grid and drain electrode between drain electrode, wherein：First grid and second gate One end of interpolar coupled capacitor Cg1g2 is connected with first grid node G1, and the other end is connected with second grid node G2；The One end of coupled capacitor Cg1d is connected with first grid node G1 between one grid and drain electrode, the other end and the second drain node D It is connected；One end of coupled capacitor Cg2d is connected with second grid node G2 between second grid and drain electrode, the other end and second Drain node D is connected；

In the step 2, the S parameter (scattering parameter) of vector network analyzer measurement open test structure is utilized；During measurement, Three port S parameters of open-circuit structure are measured in the range of the working frequency range of device using vector network analyzer, such as 10MHz is arrived 40GHz；

In the step 3, three port S parameters measured in step 2 are converted into Y parameter by s2y functions in Matlab；From The equivalent circuit established in step 1 obtains Y parameter matrix, the value of each parasitic capacitance is tried to achieve by the imaginary part of Y parameter, formula is such as Shown in lower：

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Y₁₁=j ω (C_pg1+C_pg1d+C_pg1g2)

Y₂₂=j ω (C_pg2+C_pg2d)

Y₃₃=j ω (C_pd+C_pg1d+C_pg2d)

Y₁₂=Y₂₁=-j ω C_pg1g2

Y₁₃=Y₃₁=-j ω C_pg1d

Y₂₃=Y₃₂=-j ω C_pg2d

The exact value of parasitic capacitance can be obtained by being calculated by Y parameter：

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Wherein, Y_PADRepresenting the admittance parameter of open test structure equivalent circuit, it is assumed that first grid node G1 port numbers are 1, the Two gate node G2 port numbers are 2, and the second drain node D port numbers are 3, then Y11, Y22, Y33 represent 1,2,3 ports respectively Input admittance, Y12 represent that the transfer admittance of port 1 is arrived in port 2, and Y13 represents that the transfer admittance of port 1 is arrived in port 3, and Y23 is represented The transfer admittance of port 2 is arrived in port 3；

Wherein, Cpg1 represents that first grid parasitic capacitance, Cpg2 represent that second grid parasitic capacitance, Cpd represent drain parasitic electricity Hold, Cg1g2 represent coupled capacitor between first grid and second grid, Cg1d represent coupled capacitor between first grid and drain electrode, Cg2d represents coupled capacitor between second grid and drain electrode；The value of each parasitic capacitance can be obtained by being calculated more than.