CN107907811A - A kind of open-circuit structure test method for being used to extract double grid GaAs pHEMT device parasitic capacitances - Google Patents
A kind of open-circuit structure test method for being used to extract double grid GaAs pHEMT device parasitic capacitances Download PDFInfo
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- CN107907811A CN107907811A CN201710887326.4A CN201710887326A CN107907811A CN 107907811 A CN107907811 A CN 107907811A CN 201710887326 A CN201710887326 A CN 201710887326A CN 107907811 A CN107907811 A CN 107907811A
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- G—PHYSICS
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Abstract
A kind of open-circuit structure test method for being used to extract double grid GaAs pHEMT device parasitic capacitances, including step 1：Open test structure is designed, and establishes open test structure equivalent circuit；Open test structure includes the interconnection line (Interconnect) for drawing double grid GaAs pHEMT device interfaces and with probe contact come the pad (PAD) that is biased；Step 2：Measure three port S parameters of open test structure；Wherein the S parameter (scattering parameter) of open test structure is measured using vector network analyzer.During measurement, three port S parameters of open-circuit structure are measured in the range of the working frequency range of device using vector network analyzer.Step 3：The S parameter measured in step 1 is converted into Y parameter, the value of parasitic capacitance is calculated by Y parameter.Wherein, three port S parameters are converted to Y parameter and are carried out by s2y functions in Matlab, and Y parameter method for expressing is obtained using the equivalent circuit of open test structure.
Description
Technical field
The present invention relates to microwave device testing field, is related to a kind of one kind of double grid GaAs pHEMT device parasitic capacitances
Open test structure extraction method.
Technical background
Double-gated devices are widely used in power amplifier, phase shifter, frequency mixer and monolithic integrated microwave circuit.Traditional
In modeling method, small-signal model is preferentially established to facilitate the foundation of subsequent large-signal model.So accurately establish small
Signal model is very crucial.
For the small-signal model of single gate device, most-often used method be by numerical optimization make the S parameter of model with
The S parameter fitting measured.But contain ectoparasitism parameter and two for double grid GaAs pHEMT devices, its small-signal
The inside intrinsic parameters of pHEMT, add up 29 unknown parameters altogether, therefore, it is desirable to the measurement data by three port S parameters
It is extremely difficult to be fitted.In fact, since double-gate structure is different from single grid, it is difficult to directly by the analysis side of single gate device
Method is directly applied in double-gated devices.
Deng et al. [Deng W K, Chu T H.Elements extraction of GaAs dual-gate
MESFET small-signal equivalent circuit[J].IEEE Transactions on Microwave
Theory&Techniques,1998:2383-2390.] propose a set of extraction double grid ectoparasitism parameter and internal intrinsic ginseng
Several flows.Using the method for analysis, by the way that in device bias, under cut-off condition, test frequency is to measure in the case of low frequency
Y parameter is calculated, so as to directly obtain the value of parasitic capacitance.And in fact, by it is this end in device, low frequency measurement
The capacitance that method obtains usually has certain change compared with actual value, and some internal intrinsic parameters are joined for ectoparasitism
Several changes is very sensitive, and the inside intrinsic parameters that may be such that extraction are negative value.
The open test structure of single grid just extensive use after doctor's Wijinen invention first in 1987, using single grid
Test structure can accurately extract parasitic capacitance parameter, L Shen et al. [Sun L, Gao J, Shen L.Direct
Extraction of Equivalent Circuit Parameters for GaAs pHEMT[J].Journal of
Computational&Theoretical Nanoscience,2015,12(6):996-1001 (6)] using analysis method and
Open test structural approach makes the effective frequency of small-signal modeling be up to 110GHz.It can be seen that single grid GaAs pHEMT devices are opened
Road test structure can reach good precision, however, open test structure and method for double grid GaAs pHEMT devices
Itd is proposed still without people.
In order to overcome the disadvantages mentioned above of the prior art, the present invention proposes one kind and is applied to double grid GaAs pHEMT devices
Open test structure, for extracting the external parasitic capacitances of double grid GaAs pHEMT devices.
The content of the invention
The present invention will overcome the disadvantages mentioned above of the prior art, there is provided it is a kind of applied to double grid GaAs pHEMT devices can
In the method for direct, accurate extraction external parasitic capacitances.
To achieve the above object, it is provided by the present invention a kind of for extracting double grid GaAs pHEMT device parasitic capacitances
Open-circuit structure test method, include the following steps：
Step 1：Open test structure is designed, and establishes open test structure equivalent circuit；
Step 2：Measure three port S parameters of open test structure；
Step 3：The S parameter measured in step 2 is converted into Y parameter, parasitic capacitance is calculated by Y parameter
Value.
In the step 1, designed open-circuit structure as shown in Fig. 2, the structure is similar to device under test test structure,
But measured device double grid GaAs pHEMT devices are not included.Open test structure is included double grid GaAs pHEMT device interfaces
The interconnection line (Interconnect) of extraction and with probe contact come the pad (PAD) that is biased.Open test structure is equivalent
Circuit is as shown in figure 3, including coupling capacitor part 200 between pad parasitic capacitance portion 100 and pad；
The pad parasitic capacitance portion 100 by first grid parasitic capacitance Cpg1, second grid parasitic capacitance Cpg2 and
Drain parasitic capacitance Cpd is formed, wherein：One end of first grid parasitic capacitance Cpg1 is connected with first grid node G1, separately
One end is connected with the first source node S-phase；One end of second grid parasitic capacitance Cpg2 is connected with second grid node G2, separately
One end is connected with the first source node S-phase；One end of drain parasitic capacitance Cpd is connected with the second drain node D, the other end with
First source node S-phase connects；
Coupling capacitor part 200 is by coupled capacitor Cg1g2, the first grid between first grid and second grid between the pad
Coupled capacitor Cg2d is formed between coupled capacitor Cg1d and second grid and drain electrode between pole and drain electrode, wherein：First grid and second
One end of coupled capacitor Cg1g2 is connected with first grid node G1 between grid, and the other end is connected with second grid node G2；
One end of coupled capacitor Cg1d is connected with first grid node G1 between first grid and drain electrode, the other end and the second drain node
D is connected；One end of coupled capacitor Cg2d is connected with second grid node G2 between second grid and drain electrode, the other end and second
Drain node D is connected.
In the step 2, the S parameter (scattering parameter) of vector network analyzer measurement open test structure is utilized.Measurement
When, three port S parameters of open-circuit structure are measured in the range of the working frequency range of device using vector network analyzer, such as
10MHz to 40GHz.
In the step 3, three port S parameters measured in step 2 are converted into Y ginsengs by s2y functions in Matlab
Number.The equivalent circuit established from step 1 obtains Y parameter matrix, and the value of each parasitic capacitance is tried to achieve by the imaginary part of Y parameter, public
Formula is as follows：
Y11=j ω (Cpg1+Cpg1d+Cpg1g2)
Y22=j ω (Cpg2+Cpg2d)
Y33=j ω (Cpd+Cpg1d+Cpg2d)
Y12=Y21=-j ω Cpg1g2
Y13=Y31=-j ω Cpg1d
Y23=Y32=-j ω Cpg2d
The exact value of parasitic capacitance can be obtained by being calculated by Y parameter：
Wherein, YPAD represents the admittance parameter of open test structure equivalent circuit, it is assumed that first grid node G1 port numbers
For 1, second grid node G2 port numbers are 2, and the second drain node D port numbers are 3, then Y11, Y22, Y33 represent 1,2,3 respectively
The input admittance of port, Y12 represent that the transfer admittance of port 1 is arrived in port 2, and Y13 represents that the transfer admittance of port 1 is arrived in port 3,
Y23 represents that the transfer admittance of port 2 is arrived in port 3.
Wherein, Cpg1 represents that first grid parasitic capacitance, Cpg2 represent that second grid parasitic capacitance, Cpd represent that drain electrode is posted
Raw capacitance, Cg1g2 represent that first grid represents to couple electricity between first grid and drain electrode with coupled capacitor, Cg1d between second grid
Hold, Cg2d represents coupled capacitor between second grid and drain electrode.The value of each parasitic capacitance can be obtained by being calculated more than.
The beneficial effects of the invention are as follows：
The present invention, which is directed in the method directly extracted for double grid GaAs pHEMT device parasitic capacitances at present, passes through device
The capacitance and this inaccurate defect of internal intrinsic parameters that cut-off, the method for low frequency measurement obtain, it is proposed that one kind is used for double
The open test structure extraction of parasitic capacitance method of grid GaAs pHEMT devices, parasitic capacitance, physical significance are extracted by this method
Clearly, extracting method is simple, and accuracy is high, can effectively improve the precision of double grid GaAs pHEMT device small-signal models.
Brief description of the drawings
Fig. 1 is double grid GaAs pHEMT small-signal equivalent circuits；
Fig. 2 is the open test structure used in the present invention；
Fig. 3 is the equivalent circuit of open test structure；
Fig. 4 is the flow chart of open test structure extraction parasitic capacitance；
Embodiment
Below in conjunction with the attached drawing in present example, the technical solution in present example is carried out clear, complete
Description.In without departing substantially from inventive concept spirit and scope, various changes and advantages that will be apparent to those skilled in the art are included in
In the present invention, and with the big protection domain of appended claims.Implement procedures, conditions, experimental methods of the present invention etc., remove
Outside the content specially referred to below, it is among the general principles and common general knowledge in the art, content is not particularly limited in the present invention.
A kind of open-circuit structure test side for being used to extract double grid GaAs pHEMT device parasitic capacitances provided by the invention
Method, includes the following steps：
Step 1：Open test structure is designed, and establishes open test structure equivalent circuit；
Step 2：Measure three port S parameters of open test structure；
Step 3：The S parameter measured in step 2 is converted into Y parameter, parasitic capacitance is calculated by Y parameter
Value.
In the step 1, designed open-circuit structure as shown in Fig. 2, the structure is similar to device under test test structure,
But measured device double grid GaAs pHEMT devices are not included.Open test structure is included double grid GaAs pHEMT device interfaces
The interconnection line (Interconnect) of extraction and with probe contact come the pad (PAD) that is biased.Open test structure is equivalent
Circuit is as shown in figure 3, including coupling capacitor part 200 between pad parasitic capacitance portion 100 and pad；
The pad parasitic capacitance portion 100 by first grid parasitic capacitance Cpg1, second grid parasitic capacitance Cpg2 and
Drain parasitic capacitance Cpd is formed, wherein：One end of first grid parasitic capacitance Cpg1 is connected with first grid node G1, separately
One end is connected with the first source node S-phase；One end of second grid parasitic capacitance Cpg2 is connected with second grid node G2, separately
One end is connected with the first source node S-phase；One end of drain parasitic capacitance Cpd is connected with the second drain node D, the other end with
First source node S-phase connects；
Coupling capacitor part 200 is by coupled capacitor Cg1g2, the first grid between first grid and second grid between the pad
Coupled capacitor Cg2d is formed between coupled capacitor Cg1d and second grid and drain electrode between pole and drain electrode, wherein：First grid and second
One end of coupled capacitor Cg1g2 is connected with first grid node G1 between grid, and the other end is connected with second grid node G2；
One end of coupled capacitor Cg1d is connected with first grid node G1 between first grid and drain electrode, the other end and the second drain node
D is connected；One end of coupled capacitor Cg2d is connected with second grid node G2 between second grid and drain electrode, the other end and second
Drain node D is connected.
In the step 2, the S parameter (scattering parameter) of vector network analyzer measurement open test structure is utilized.Measurement
When, three port S parameters of open-circuit structure are measured in the range of the working frequency range of device using vector network analyzer, such as
10MHz to 40GHz.
In the step 3, three port S parameters measured in step 2 are converted into Y ginsengs by s2y functions in Matlab
Number.The equivalent circuit established from step 1 obtains Y parameter matrix, and the value of each parasitic capacitance is tried to achieve by the imaginary part of Y parameter, public
Formula is as follows：
Y11=j ω (Cpg1+Cpg1d+Cpg1g2)
Y22=j ω (Cpg2+Cpg2d)
Y33=j ω (Cpd+Cpg1d+Cpg2d)
Y12=Y21=-j ω Cpg1g2
Y13=Y31=-j ω Cpg1d
Y23=Y32=-j ω Cpg2d
The exact value of parasitic capacitance can be obtained by being calculated by Y parameter：
Wherein, YPAD represents the admittance parameter of open test structure equivalent circuit, it is assumed that first grid node G1 port numbers
For 1, second grid node G2 port numbers are 2, and the second drain node D port numbers are 3, then Y11, Y22, Y33 represent 1,2,3 respectively
The input admittance of port, Y12 represent that the transfer admittance of port 1 is arrived in port 2, and Y13 represents that the transfer admittance of port 1 is arrived in port 3,
Y23 represents that the transfer admittance of port 2 is arrived in port 3.
Wherein, Cpg1 represents that first grid parasitic capacitance, Cpg2 represent that second grid parasitic capacitance, Cpd represent that drain electrode is posted
Raw capacitance, Cg1g2 represent that first grid represents to couple electricity between first grid and drain electrode with coupled capacitor, Cg1d between second grid
Hold, Cg2d represents coupled capacitor between second grid and drain electrode.The value of each parasitic capacitance can be obtained by being calculated more than.
Claims (1)
1. a kind of open-circuit structure test method for being used to extract double grid GaAs pHEMT device parasitic capacitances, includes the following steps：
Step 1：Open test structure is designed, and establishes open test structure equivalent circuit；
Step 2：Measure three port S parameters of open test structure；
Step 3：The S parameter measured in step 2 is converted into Y parameter, parasitic capacitance is calculated by Y parameter
Value；
In the step 1, open test structure is identical with the test structure of device under test, but not comprising tested double grid GaAs
PHEMT devices；Open test structure include by double grid GaAs pHEMT device interfaces draw interconnection line Interconnect and
With probe contact come the pad PAD that is biased；Open test structure equivalent circuit include pad parasitic capacitance portion (100) and
Coupling capacitor part (200) between pad；
The pad parasitic capacitance portion (100) is by first grid parasitic capacitance Cpg1, second grid parasitic capacitance Cpg2 and leakage
Pole parasitic capacitance Cpd is formed, wherein：One end of first grid parasitic capacitance Cpg1 is connected with first grid node G1, another
End is connected with the first source node S-phase；One end of second grid parasitic capacitance Cpg2 is connected with second grid node G2, another
End is connected with the first source node (S)；One end of drain parasitic capacitance Cpd is connected with the second drain node D, the other end with
First source node S-phase connects；
Coupling capacitor part (200) is by coupled capacitor Cg1g2, first grid between first grid and second grid between the pad
Coupled capacitor Cg2d is formed between coupled capacitor Cg1d and second grid and drain electrode between drain electrode, wherein：First grid and second gate
One end of interpolar coupled capacitor Cg1g2 is connected with first grid node G1, and the other end is connected with second grid node G2；The
One end of coupled capacitor Cg1d is connected with first grid node G1 between one grid and drain electrode, the other end and the second drain node D
It is connected；One end of coupled capacitor Cg2d is connected with second grid node G2 between second grid and drain electrode, the other end and second
Drain node D is connected；
In the step 2, the S parameter (scattering parameter) of vector network analyzer measurement open test structure is utilized；During measurement,
Three port S parameters of open-circuit structure are measured in the range of the working frequency range of device using vector network analyzer, such as 10MHz is arrived
40GHz；
In the step 3, three port S parameters measured in step 2 are converted into Y parameter by s2y functions in Matlab；From
The equivalent circuit established in step 1 obtains Y parameter matrix, the value of each parasitic capacitance is tried to achieve by the imaginary part of Y parameter, formula is such as
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Y11=j ω (Cpg1+Cpg1d+Cpg1g2)
Y22=j ω (Cpg2+Cpg2d)
Y33=j ω (Cpd+Cpg1d+Cpg2d)
Y12=Y21=-j ω Cpg1g2
Y13=Y31=-j ω Cpg1d
Y23=Y32=-j ω Cpg2d
The exact value of parasitic capacitance can be obtained by being calculated by Y parameter：
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Wherein, YPADRepresenting the admittance parameter of open test structure equivalent circuit, it is assumed that first grid node G1 port numbers are 1, the
Two gate node G2 port numbers are 2, and the second drain node D port numbers are 3, then Y11, Y22, Y33 represent 1,2,3 ports respectively
Input admittance, Y12 represent that the transfer admittance of port 1 is arrived in port 2, and Y13 represents that the transfer admittance of port 1 is arrived in port 3, and Y23 is represented
The transfer admittance of port 2 is arrived in port 3；
Wherein, Cpg1 represents that first grid parasitic capacitance, Cpg2 represent that second grid parasitic capacitance, Cpd represent drain parasitic electricity
Hold, Cg1g2 represent coupled capacitor between first grid and second grid, Cg1d represent coupled capacitor between first grid and drain electrode,
Cg2d represents coupled capacitor between second grid and drain electrode；The value of each parasitic capacitance can be obtained by being calculated more than.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710887326.4A CN107907811B (en) | 2017-09-27 | 2017-09-27 | It is a kind of for extracting the open-circuit structure test method of double grid GaAs pHEMT device parasitic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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