CN104298837A - Device equivalent circuit model parameter extracting method and bonding pad parasitic parameter extracting method - Google Patents

Abstract

The invention discloses a device equivalent circuit model parameter extracting method and mainly aims at solving the problems in the prior art, such as complicated extracting process and inaccurate extracting results. The parasitic parameter extracting method comprises the following steps: dividing a short-circuit bonding pad equivalent circuit from which a parasitic capacitor is de-embedded into independent networks for further analysis, and synchronously extracting parasitic resistance and parasitic inductance parameters. The invention further discloses a bonding pad parasitic parameter extracting method applying the equivalent circuit parameter extracting method. Simulation results show that parasitic parameter extracting results are highly matched with scattering parameters of actual device test results, and the parameters are more accurately and rapidly extracted.

Description

Device equivalent circuit model parameter extracting method and pad parasitic parameter extraction method

Technical field

The present invention relates to a kind of device equivalent circuit model parameter extracting method and a kind ofly go outer transistor device testing weld pad parasitic parameter extraction method, belonging to technical field of integrated circuits.

Background technology

Transistor model mainly comprises two large type, physical model and equivalent-circuit models.Wherein, equivalent-circuit model is general, the effective model of one transistor being carried out to analog simulation, setting up equivalent-circuit model is accurately that circuit design is successfully crucial, is also to improve circuit performance, shorten the lead time, improve the central factor being designed to power and yield rate, reduction development and production cost.

For transistor device model, go outer, the topological structure of equivalent electrical circuit and the extracting method etc. of parameter of the calibration of testing apparatus, pad parasitism all can affect model accuracy (Erickson N, Shringarpure K, Fan J, et al.De-embedding techniques for transmission lines:An exploration, review, and proposal [C] .Electromagnetic Compatibility, 2013IEEE International Symposium on.IEEE, 2013:840-845. list of references 1).And as the first step of model parameter extraction, what pad parasitic parameter extracted whether accurately having a significant impact the work of subsequent device model parameter extraction.Conventional parasitic parameter is peeled off and is adopted open, short (open-short) pad test structure.Test structure needed for the method is simple, good De-embedding effect can be reached with lower cost, be often used as industry standard approach (Tiemeijer L F, Havens R J, Jansman A B M, et al.Comparison of the " pad-open-short " and " open-short-load " deembedding techniques for accurate on-wafer RF characterization of high-quality passives [J] .IEEE Tras Microwave Theory Tech, 2005, 53 (2): 723-729. lists of references 2).

Traditional open, short pad parasitic parameter extraction method extracts independent for the electric capacity of parasitism, resistance and inductance parameters substep, and carry out peeling off (Koolen M, Geelen J A M, Versleijen M.An improved de-embedding technique for on-wafer high-frequency characterization [C] .Bipolar Circuits and Technology Meeting, 1991, Proceedings of the 1991.IEEE, 1991:188-191., list of references 3).But there is certain defect in this method, because stray capacitance parameter is difficult to peel off completely, subsequently when the curve making Z parameter real part and frequency is to extract dead resistance parameter, the curve of Z parameter real part and resistance there will be the dependence to frequency, also can affect degree of accuracy (the Gu D that Z parameter imaginary part extracts inductance simultaneously, Wallis T M, Blanchard P, et al.De-embedding parasitic elements of GaN nanowire metal semiconductor field effect transistors by use of microwave measurements [J] .Applied Physics Letters, 2011, 98 (22): 223109. lists of references 4).Larger error will be had.

Equivalent electrical circuit is divided into independently network and further analyzes by equivalent circuit parameter extracting method of the present invention, and synchronous extraction dead resistance and stray inductance parameter, avoid the frequency dependence that there will be when using traditional method for extracting dead resistance parameter.

The present invention is based on traditional open, short pad structure, propose a kind of pad parasitic parameter extraction method, what effectively solve stray capacitance does not peel off the impact brought follow-up parasitic parameter extraction work completely, and avoid the frequency dependence that there will be when using traditional method for extracting dead resistance parameter, improve the precision and speed of extracting result.

Summary of the invention

For above-mentioned the deficiencies in the prior art, the present invention proposes a kind of device equivalent circuit model parameter extracting method and the pad parasitic parameter extraction method that can avoid the frequency dependence that there will be when extracting dead resistance parameter.

The technical solution used in the present invention is: a kind of device equivalent circuit model parameter extracting method, comprises the following steps:

(1) connect in equivalent electrical circuit a resistance and an inductance are divided into a unit, its admittance is Y; If have resistance and the inductance of many group series connection, be then divided into multiple unit, its admittance is Y ₁, Y ₂, Y ₃,

(2) record device scattering parameter S, calculated the admittance of each unit by S parameter, draw the imaginary part of each unit admittance;

(3) angular frequency-unit admittance imaginary part curve map is made;

(4) formula is passed through $\left\{\begin{array}{c}Y=\frac{1}{R+\mathrm{jwL}}=\frac{R}{R^2+w^2{L}^2}-j\frac{\mathrm{wL}}{R^2+w^2{L}^2}\\ \mathrm{imag}\left(Y\right)=-\frac{L}{\frac{R^2}{w}+w{L}^2}\end{array}\right.$ Drawing as angular frequency w=R/L, there is minimum value in the admittance imaginary part imag (Y) of each unit make angular frequency-unit admittance imaginary part curve map, read the minimum value of each unit admittance imaginary part, and the angular frequency w of correspondence _min; Calculate the stray inductance value of each unit respectively with parasitic resistance values

Described device equivalent circuit model parameter extracting method is applicable to field effect transistor transistor equivalent circuit, or the equivalent electrical circuit of connecting of resistance and inductance in passive device.

Application rights requires a pad parasitic parameter extraction method for the device equivalent circuit model parameter extracting method described in 1, comprises the following steps:

(1) the scattering parameter S under open-circuit structure is measured _o, and be transformed to admittance parameter Y _o, $Y_o=\left(\begin{array}{cc}{Y}_{o11}& Y_{o12}\\ Y_{o21}& Y_{o22}\end{array}\right),$ Pass through formula $\left\{\begin{array}{c}\mathrm{imag}\left(Y_{o11}\right)=w\·(C_{\mathrm{pg}}+C_{\mathrm{pgd}})\\ \mathrm{imag}\left(Y_{o12}\right)=\mathrm{imag}\left(Y_{o21}\right)=-w\·{\mathrm{Cp}}_{\mathrm{pgd}}\\ \mathrm{imag}\left(Y_{o22}\right)=w\·(C_{\mathrm{pd}}+C_{\mathrm{pgd}})\end{array}\right.$ Calculate peripheral stray capacitance C _pg, C _pdand C _pgdnumerical value be respectively $C_{\mathrm{pgd}}=-\frac{\mathrm{imag}\left(Y_{021}\right)+\mathrm{imag}\left(Y_{012}\right)}{w},C_{\mathrm{pg}}=\frac{\mathrm{imag}\left(Y_{011}\right)}{w}-C_{\mathrm{pgd}},$ $C_{\mathrm{pd}}=\frac{\mathrm{imag}\left(Y_{022}\right)}{w}-C_{\mathrm{pgd}};$

(2) the scattering parameter S under short-circuit structure is measured _s, and be transformed to admittance parameter Y _s, $Y_s=\left(\begin{array}{cc}{Y}_{s11}& Y_{s12}\\ Y_{s21}& Y_{s22}\end{array}\right),$ By the admittance parameter Y under short-circuit structure _sadmittance parameter Y is obtained after peeling off stray capacitance _m, $Y_m=\left(\begin{array}{cc}{Y}_{m11}& Y_{m12}\\ Y_{m21}& Y_{m22}\end{array}\right);$

Further comprising the steps of:

(3) equivalent-circuit model of the short-circuit structure after stripping stray capacitance is divided into three unit; Gate series parasitic parameter is comprised parasitic gate resistance R _gwith stray inductance L _gbe divided into unit 1, admittance is designated as Y1; Drain series parasitic parameter is comprised drain parasitic resistance R _dwith stray inductance L _dbe divided into unit 2, admittance is designated as Y ₂; Source series parasitic parameter is comprised source electrode dead resistance R _swith stray inductance L _sbe divided into unit 3, admittance is designated as Y ₃; Under then utilizing Two-port Network Parameters, list admittance parameter Y _mand the relational expression between each unit admittance $\left\{\begin{array}{c}{Y}_{m11}=\frac{1}{\frac{1}{Y_1}+\frac{1}{Y_2+Y_3}}\\ Y_{m12}=Y_{m21}=-\frac{Y_1{Y}_2}{Y_1+Y_2+Y_3}\\ Y_{m22}=\frac{1}{\frac{1}{Y_2}+\frac{1}{Y_1+Y_3}}\end{array}\right.;$

The admittance of each unit can by admittance parameter Y _mcalculate, $\left\{\begin{array}{c}{Y}_3=Y_{m12}-\frac{Y_{m11}{Y}_{m22}}{Y_{m12}}\\ Y_2=\frac{Y_{m11}{Y}_{m22}-Y_{m12}^2}{Y_{m11}+Y_{m21}}\\ Y_1=\frac{Y_{m11}{Y}_{m22}-Y_{m12}^2}{Y_{m22}+Y_{m12}}\end{array}\right.,$ Draw the imaginary part of each unit admittance;

(4) angular frequency-unit admittance imaginary part curve map is made;

(5) formula is passed through $\left\{\begin{array}{c}Y=\frac{1}{R+\mathrm{jwL}}=\frac{R}{R^2+w^2{L}^2}-j\frac{\mathrm{wL}}{R^2+w^2{L}^2}\\ \mathrm{imag}\left(Y\right)=-\frac{L}{\frac{R^2}{w}+w{L}^2}\end{array}\right.$ Drawing as angular frequency w=R/L, there is minimum value in the admittance imaginary part imag (Y) of each unit read the minimum value of each unit admittance imaginary part imag (Y), and the angular frequency w of correspondence _min; Calculate the stray inductance value of each unit respectively $L=-\frac{1}{2w_{\min }{Y}_{\min }}$ With parasitic resistance values $R=-\frac{1}{2Y_{\min }}.$

Described pad parasitic parameter extraction method is applicable to field effect transistor, comprises metal-oxide semiconductor transistor, metal-semiconductor transistor, High Electron Mobility Transistor and counterfeit High Electron Mobility Transistor.

Described field effect transistor is prepared by silicon, germanium silicon, gallium arsenide, indium phosphide, silit or gallium nitride material.

Described pad parasitic parameter extraction method is applicable to bipolar transistor, comprises all homojunction bipolar transistors and hetero-junction bipolar transistor.

Described bipolar transistor is prepared by silicon, germanium silicon, gallium arsenide, indium phosphide, silit or gallium nitride material.

Beneficial effect:

The present invention adopts open circuit pad to extract stray capacitance, then the short circuit pad equivalent electrical circuit having peeled off stray capacitance is divided into independently network further to analyze, synchronous extraction dead resistance and stray inductance parameter, avoid the frequency dependence that there will be when using traditional method for extracting dead resistance parameter, improve the precision and speed of extracting result.The scattering parameter goodness of fit that the present invention extracts the result that parasitic parameter result and practical devices are tested is higher, and extracting parameter more accurately and fast.

Accompanying drawing illustrates:

The device detection equivalent circuit diagram adopted in the pad parasitic parameter extraction method that Fig. 1 is the embodiment of the present invention;

Fig. 2 is the equivalent-circuit model topological diagram extracted in the pad parasitic parameter extraction method of the embodiment of the present invention under the pad open-circuit structure of peripheral stray capacitance parameter;

Fig. 3 is the equivalent-circuit model topological diagram extracted in the pad parasitic parameter extraction method of the embodiment of the present invention under the pad short-circuit structure of dead resistance parameter and stray inductance parameter;

Fig. 4 is the equivalent-circuit model topological diagram under the pad short-circuit structure after peeling off stray capacitance in the pad parasitic parameter extraction method of the embodiment of the present invention;

For extracting angular frequency-admittance imaginary part curve map that dead resistance and stray inductance are done in the device equivalent circuit model parameter extracting method that Fig. 5 is the embodiment of the present invention;

Fig. 6 is the improvement situation comparison diagram of S parameter after employing pad parasitic parameter extraction method of the present invention.

Embodiment:

Below in conjunction with the drawings and specific embodiments, the present invention will be further described.

The device detection equivalent circuit diagram of Fig. 1 for adopting in embodiment of the present invention pad parasitic parameter extraction method, this equivalent circuit diagram comprises peripheral stray capacitance C _pg, C _pd, C _pgd, series parasitic resistance R _g, R _d, R _swith series connection parasitic inductances in series L _g, L _d, L _s.Here the method for parameter extraction is also how to extract to above-mentioned parameter in this equivalent circuit diagram the explanation carried out.

Fig. 2 is the equivalent-circuit model topological diagram extracted in embodiment of the present invention pad parasitic parameter extraction method under the pad open-circuit structure of peripheral stray capacitance parameter, comprises three peripheral stray capacitance parameter C _pg, C _pd, C _pgd.

According to the equivalent-circuit model topological diagram of Fig. 2 under pad open-circuit structure, the scattering parameter S under open-circuit structure can be obtained _o, and be transformed to admittance parameter Y _o, $Y_o=\left(\begin{array}{cc}{Y}_{o11}& Y_{o12}\\ Y_{o21}& Y_{o22}\end{array}\right);$

Pass through formula $\left\{\begin{array}{c}\mathrm{imag}\left(Y_{o11}\right)=w\·(C_{\mathrm{pg}}+C_{\mathrm{pgd}})\\ \mathrm{imag}\left(Y_{o12}\right)=\mathrm{imag}\left(Y_{o21}\right)=-w\·{\mathrm{Cp}}_{\mathrm{pgd}}\\ \mathrm{imag}\left(Y_{o22}\right)=w\·(C_{\mathrm{pd}}+C_{\mathrm{pgd}})\end{array}\right.,$ Calculate peripheral stray capacitance C _pg, C _pdand C _pgdnumerical value be respectively $C_{\mathrm{pgd}}=-\frac{\mathrm{imag}\left(Y_{021}\right)+\mathrm{imag}\left(Y_{012}\right)}{w},C_{\mathrm{pg}}=\frac{\mathrm{imag}\left(Y_{011}\right)}{w}-C_{\mathrm{pgd}},$ $C_{\mathrm{pd}}=\frac{\mathrm{imag}\left(Y_{022}\right)}{w}-C_{\mathrm{pgd}}.$

Fig. 3 is the equivalent-circuit model topological diagram extracted in embodiment of the present invention pad parasitic parameter extraction method under the pad short-circuit structure of dead resistance parameter and stray inductance parameter.According to the equivalent-circuit model topological diagram of Fig. 3 under pad short-circuit structure, the scattering parameter S under short-circuit structure can be obtained _s, and be transformed to admittance parameter Y _s, $Y_s=\left(\begin{array}{cc}{Y}_{s11}& Y_{s12}\\ Y_{s21}& Y_{s22}\end{array}\right),$ By the admittance parameter Y under short-circuit structure _sdeduct the admittance parameter Y under open-circuit structure _o, obtain the admittance parameter Y after peeling off stray capacitance _m, $Y_m=\left(\begin{array}{cc}{Y}_{m11}& Y_{m12}\\ Y_{m21}& Y_{m22}\end{array}\right).$

Fig. 4 is the equivalent-circuit model topological diagram under the pad short-circuit structure after peeling off stray capacitance in embodiment of the present invention pad parasitic parameter extraction method, and the admittance parameter of its correspondence is Y _m.

Equivalent-circuit model Fig. 4 being peeled off the short-circuit structure after stray capacitance is divided into three unit; Gate series parasitic parameter is comprised parasitic gate resistance R _gwith stray inductance L _gbe divided into unit 1, admittance is designated as Y ₁(impedance is designated as Z ₁); Drain series parasitic parameter is comprised drain parasitic resistance R _dwith stray inductance L _dbe divided into unit 2, admittance is designated as Y ₂(impedance is designated as Z ₂); Source series parasitic parameter is comprised source electrode dead resistance R _swith stray inductance L _sbe divided into unit 3, admittance is designated as Y ₃(impedance is designated as Z ₃);

Under utilizing Two-port Network Parameters, list admittance parameter Y _mand the relational expression between each unit admittance.So the Y of the equivalent-circuit model of short-circuit structure after stripping stray capacitance _mparameter can be expressed as

$\left\{\begin{array}{c}{Y}_{m11}=\frac{1}{\frac{1}{Y_1}+\frac{1}{Y_2+Y_3}}\\ Y_{m12}=Y_{m21}=-\frac{Y_1{Y}_2}{Y_1+Y_2+Y_3}\\ Y_{m22}=\frac{1}{\frac{1}{Y_2}+\frac{1}{Y_1+Y_3}}\end{array}\right.$

Calculate the admittance of each unit $\left\{\begin{array}{c}{Y}_3=Y_{m12}-\frac{Y_{m11}{Y}_{m22}}{Y_{m12}}\\ Y_2=\frac{Y_{m11}{Y}_{m22}-Y_{m12}^2}{Y_{m11}+Y_{m21}}\\ Y_1=\frac{Y_{m11}{Y}_{m22}-Y_{m12}^2}{Y_{m22}+Y_{m12}}\end{array}\right..$

In the specific embodiment of the invention, equivalent-circuit model of the present invention has three groups of dead resistances and stray inductance, but the present invention more than that, device equivalent circuit model parameter extracting method of the present invention can be used for the parameter extraction of the equivalent electrical circuit of resistance and inductance unit in series.In the equivalent electrical circuit of resistance and inductance unit in series, connect in equivalent electrical circuit a resistance and an inductance are divided into a unit, and its admittance is Y; If have resistance and the inductance of many group series connection, be then divided into multiple unit, its admittance is Y ₁, Y ₂, Y ₃...

Record device scattering parameter S, test is automatically completed by instrument, pointwise test from low to high.Calculated the admittance of each unit by S parameter, draw the imaginary part of each unit admittance; Utilize the admittance imaginary values different when different angular frequency of testing and obtaining, make angular frequency-unit admittance imaginary part curve map.

In the present invention, measure scattering parameter S and be transformed to admittance parameter Y _s, $Y_s=\left(\begin{array}{cc}{Y}_{s11}& Y_{s12}\\ Y_{s21}& Y_{s22}\end{array}\right).$ But S parameter also more than that, after drawing S parameter, can be transformed to admittance parameter Y or impedance parameter Z by the present invention.Analyze the structure of concrete equivalent electrical circuit, comprise the connection of unit, admittance parameter Y or the relational expression between impedance parameter Z and unit admittance between each port is listed according to the definition of admittance parameter Y or impedance parameter Z and basic circuit theory such as Kirchhoff's second law or Kirchhoff's current law (KCL), the expression formula of the admittance of each unit is drawn by this relational expression, this expression formula is an equation about admittance parameter or impedance parameter, and then draws the imaginary part of each unit admittance.If also have other elements in equivalent electrical circuit except resistance and inductance unit in series, then before listing above-mentioned relation formula, in admittance parameter Y or impedance parameter Z, remove the complexity that these elements may reduce relational expression, more easily draw the expression formula of the admittance of each unit.Device equivalent circuit model parameter extracting method of the present invention is applicable to field effect transistor transistor equivalent circuit, or comprises the passive device equivalent electrical circuit of resistance and inductance series unit.

Fig. 5 in embodiment of the present invention device equivalent circuit model parameter extracting method for extracting angular frequency-admittance imaginary part curve map that dead resistance and stray inductance are done.Each minimum value of unit admittance imaginary part and the angular frequency of correspondence conveniently can be read from figure.

Pass through formula $\left\{\begin{array}{c}Y=\frac{1}{R+\mathrm{jwL}}=\frac{R}{R^2+w^2{L}^2}-j\frac{\mathrm{wL}}{R^2+w^2{L}^2}\\ \mathrm{imag}\left(Y\right)=-\frac{L}{\frac{R^2}{w}+w{L}^2}\end{array}\right.$

Wherein, in formula, R is parasitic resistance values, and L is parasitic capacitance value, and w is angular frequency, and imag (Y) is admittance imaginary part.

Can draw as angular frequency w=R/L, there is minimum value in the admittance imaginary part imag (Y) of each unit the minimum value of each unit admittance imaginary part imag (Y) is read from Fig. 5, and the angular frequency w of correspondence _min; Calculate the stray inductance value of each unit respectively with parasitic resistance values $R=-\frac{1}{2Y_{\min }}.$

Table 1

Cpg＝5.78fF	Cpd＝4.60fF	Cpgd＝1.69fF
			Rg＝0.35Ω	Rd＝0.33Ω	Rs＝0.09Ω
Lg＝29.6pH	Ld＝38.1pH	Ls＝5.2pH

Table 1 is all parasitic parameter values of institute's extraction device in embodiment of the present invention pad parasitic parameter extraction method.This table 1 is the parameter extracted for the device detection equivalent circuit diagram of accompanying drawing 1.The transistor adopted is based on 0.15 μm of GaN HEMT technique.Testing weld pad is of a size of 53 μm * 45 μm, and spacing is about 100 μm.Test data is derived from tests transistor open, short test pad structure with Agilent E8363B network analyzer, and test frequency scope is 100MHz ~ 50GHz.

First, according to formula $\left\{\begin{array}{c}\mathrm{imag}\left(Y_{o11}\right)=w\·(C_{\mathrm{pg}}+C_{\mathrm{pgd}})\\ \mathrm{imag}\left(Y_{o12}\right)=\mathrm{imag}\left(Y_{o21}\right)=-w\·{\mathrm{Cp}}_{\mathrm{pgd}}\\ \mathrm{imag}\left(Y_{o22}\right)=w\·(C_{\mathrm{pd}}+C_{\mathrm{pgd}})\end{array}\right.$ Extraction obtains 3 parasitic capacitance values, i.e. Cpg=5.78fF, Cpd=4.60fF, Cpgd=1.69fF.

Secondly, obtain admittance parameter Ym after the admittance parameter Ys under short-circuit structure is peeled off stray capacitance, peel off the equivalent electrical circuit after family planning electric capacity as Fig. 4, according to formula $\left\{\begin{array}{c}{Y}_3=Y_{m12}-\frac{Y_{m11}{Y}_{m22}}{Y_{m12}}\\ Y_2=\frac{Y_{m11}{Y}_{m22}-Y_{m12}^2}{Y_{m11}+Y_{m21}}\\ Y_1=\frac{Y_{m11}{Y}_{m22}-Y_{m12}^2}{Y_{m22}+Y_{m12}}\end{array}\right.$ Obtain 3 unit admittance value expression formula separately.

Utilize test data, make angular frequency-unit admittance value imaginary part figure, as shown in Figure 5.Find the minimum point in curve, read the w of this some correspondence _minwith imag (Y _min), it the results are shown in Table 2.

Table 2

Element number	Imag(Y)	w(10 <sup>10</sup>rad/s)
			1	-1.41640018	1.19
2	-1.49042965	0.88
			3	-5.27287126	1.82

Obtain the w of each unit _minwith imag (Y _min) after, solve respectively and obtain stray inductance in unit and parasitic resistance values, its detailed results is in Table 1.

Fig. 6 is the improvement situation comparison diagram after employing pad parasitic parameter extraction method of the present invention in S parameter.As can be seen from Figure 6, after adopting method of the present invention, extraction result more identical test data in whole frequency band of parasitic parameter, improves successful.

In the present invention, pad parasitic parameter extraction method of the present invention is applicable to all field effect transistors, includes but not limited to metal-oxide semiconductor transistor (MOSFET), metal-semiconductor transistor (MESFET), High Electron Mobility Transistor (HEMT) and counterfeit High Electron Mobility Transistor (PHEMT); Field effect transistor is prepared by silicon (Si), germanium silicon (SiGe), gallium arsenide (GaAs), indium phosphide (InP), silit (SiC) or gallium nitride (GaN) material.

Pad parasitic parameter extraction method of the present invention can be used for bipolar transistor, is applicable to all homojunction bipolar transistors (BJT) and hetero-junction bipolar transistor (HBT); Bipolar transistor is prepared by Si, SiGe, GaAs, InP, SiC or GaN material.

It should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.The all available prior art of each ingredient not clear and definite in the present embodiment is realized.

Claims (7)

1. a device equivalent circuit model parameter extracting method, is characterized in that: comprise the following steps:

(1) connect in equivalent electrical circuit a resistance and an inductance are divided into a unit, its admittance is Y; If have resistance and the inductance of many group series connection, be then divided into multiple unit, its admittance is Y ₁, Y ₂, Y ₃,

(2) record device scattering parameter S, calculated the admittance of each unit by S parameter, draw the imaginary part of each unit admittance;

(3) angular frequency-unit admittance imaginary part curve map is made;

(4) formula is passed through $\left\{\begin{array}{c}Y=\frac{1}{R+\mathrm{jwL}}=\frac{R}{R^2+w^2{L}^2}-j\frac{\mathrm{wL}}{R^2+w^2{L}^2}\\ \mathrm{imag}\left(Y\right)=-\frac{L}{\frac{R^2}{w}+w{L}^2}\end{array}\right.$ Drawing as angular frequency w=R/L, there is minimum value in the admittance imaginary part imag (Y) of each unit read the minimum value of each unit admittance imaginary part, and the angular frequency w of correspondence _min; Calculate the stray inductance value of each unit respectively $L=-\frac{1}{2w_{\min }{Y}_{\min }}$ With parasitic resistance values $R=-\frac{1}{2Y_{\min }}.$

2. device equivalent circuit model parameter extracting method according to claim 1, it is characterized in that: described device equivalent circuit model parameter extracting method is applicable to field effect transistor transistor equivalent circuit, or comprises the passive device equivalent electrical circuit of resistance and inductance series unit.

3. application rights requires a pad parasitic parameter extraction method for the device equivalent circuit model parameter extracting method described in 1, comprises the following steps:

(1) the scattering parameter S under open-circuit structure is measured _o, and be transformed to admittance parameter Y _o, $Y_o=\left(\begin{array}{cc}{Y}_{o11}& Y_{o12}\\ Y_{o21}& Y_{o22}\end{array}\right),$ Pass through formula $\left\{\begin{array}{c}\mathrm{imag}\left(Y_{o11}\right)=w\·(C_{\mathrm{pg}}+C_{\mathrm{pgd}})\\ \mathrm{imag}\left(Y_{o12}\right)=\mathrm{imag}\left(Y_{o21}\right)=-w\·{\mathrm{Cp}}_{\mathrm{pgd}}\\ \mathrm{imag}\left(Y_{o22}\right)=w\·(C_{\mathrm{pd}}+C_{\mathrm{pgd}})\end{array}\right.$ Calculate peripheral stray capacitance C _pg, C _pdand C _pgdnumerical value be respectively $C_{\mathrm{pg}}=\frac{\mathrm{imag}\left(Y_{011}\right)}{w}-C_{\mathrm{pgd}},C_{\mathrm{pd}}=\frac{\mathrm{imag}\left(Y_{022}\right)}{w}-C_{\mathrm{pgd}};$

(2) the scattering parameter S under short-circuit structure is measured _s, and be transformed to admittance parameter Y _s, $Y_s=\left(\begin{array}{cc}{Y}_{s11}& Y_{s12}\\ Y_{s21}& Y_{s22}\end{array}\right),$ By the admittance parameter Y under short-circuit structure _sdeduct the admittance parameter Y under open-circuit structure _o, obtain the admittance parameter Y after peeling off stray capacitance _m, $Y_m=\left(\begin{array}{cc}{Y}_{m11}& Y_{m12}\\ Y_{m21}& Y_{m22}\end{array}\right);$

It is characterized in that: further comprising the steps of:

(3) in, the equivalent-circuit model of the short-circuit structure after stripping stray capacitance is divided into three unit; Gate series parasitic parameter is comprised parasitic gate resistance R _gwith stray inductance L _gbe divided into unit 1, admittance is designated as Y ₁; Drain series parasitic parameter is comprised drain parasitic resistance R _dwith stray inductance L _dbe divided into unit 2, admittance is designated as Y ₂; Source series parasitic parameter is comprised source electrode dead resistance R _swith stray inductance L _sbe divided into unit 3, admittance is designated as Y ₃;

Under then utilizing Two-port Network Parameters, list admittance parameter Y _mand the relational expression between each unit admittance

$\left\{\begin{array}{c}{Y}_{m11}=\frac{1}{\frac{1}{Y_1}+\frac{1}{Y_2+Y_3}}\\ Y_{m12}=Y_{m21}=-\frac{Y_1{Y}_2}{Y_1+Y_2+Y_3}\\ Y_{m22}=\frac{1}{\frac{1}{Y_2}+\frac{1}{Y_1+Y_3}}\end{array}\right.$

The admittance of each unit can by admittance parameter Y _mcalculate, $\left\{\begin{array}{c}{Y}_3=Y_{m12}-\frac{Y_{m11}{Y}_{m22}}{Y_{m12}}\\ Y_2=\frac{Y_{m11}{Y}_{m22}-Y_{m12}^2}{Y_{m11}+Y_{m21}}\\ Y_1=\frac{Y_{m11}{Y}_{m22}-Y_{m12}^2}{Y_{m22}+Y_{m12}}\end{array}\right.,$

Draw the imaginary part of each unit admittance;

(4) angular frequency-unit admittance imaginary part curve map is made;

(5) formula is passed through $\left\{\begin{array}{c}Y=\frac{1}{R+\mathrm{jwL}}=\frac{R}{R^2+w^2{L}^2}-j\frac{\mathrm{wL}}{R^2+w^2{L}^2}\\ \mathrm{imag}\left(Y\right)=-\frac{L}{\frac{R^2}{w}+w{L}^2}\end{array}\right.$ Drawing as angular frequency w=R/L, there is minimum value in the admittance imaginary part imag (Y) of each unit read the minimum value of each unit admittance imaginary part imag (Y), and the angular frequency w of correspondence _min; Calculate the stray inductance value of each unit respectively $L=-\frac{1}{2w_{\min }{Y}_{\min }}$ With parasitic resistance values $R=-\frac{1}{2Y_{\min }}.$

4. pad parasitic parameter extraction method according to claim 3, it is characterized in that: described pad parasitic parameter extraction method is applicable to field effect transistor, comprises metal-oxide semiconductor transistor, metal-semiconductor transistor, High Electron Mobility Transistor and counterfeit High Electron Mobility Transistor.

5. pad parasitic parameter extraction method according to claim 4, is characterized in that: described field effect transistor is prepared by silicon, germanium silicon, gallium arsenide, indium phosphide, silit or gallium nitride material.

6. pad parasitic parameter extraction method according to claim 3, is characterized in that: described pad parasitic parameter extraction method is applicable to bipolar transistor, comprises all homojunction bipolar transistors and hetero-junction bipolar transistor.

7. pad parasitic parameter extraction method according to claim 6, is characterized in that: described bipolar transistor is prepared by silicon, germanium silicon, gallium arsenide, indium phosphide, silit or gallium nitride material.