CN107907811B - It is a kind of for extracting the open-circuit structure test method of double grid GaAs pHEMT device parasitic capacitor - Google Patents
It is a kind of for extracting the open-circuit structure test method of double grid GaAs pHEMT device parasitic capacitor Download PDFInfo
- Publication number
- CN107907811B CN107907811B CN201710887326.4A CN201710887326A CN107907811B CN 107907811 B CN107907811 B CN 107907811B CN 201710887326 A CN201710887326 A CN 201710887326A CN 107907811 B CN107907811 B CN 107907811B
- Authority
- CN
- China
- Prior art keywords
- grid
- parasitic capacitance
- parameter
- port
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2637—Circuits therefor for testing other individual devices
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
It is a kind of for extracting the open-circuit structure test method of double grid GaAs pHEMT device parasitic capacitor, including step 1: design open test structure, and establish open test structure equivalent circuit；Open test structure includes by the interconnection line (Interconnect) of double grid GaAs pHEMT device interface extraction and the pad (PAD) being biased with probe contact；Step 2: three port S parameters of measurement open test structure；Wherein the S parameter (scattering parameter) of open test structure is measured using vector network analyzer.When measurement, three port S parameters of open-circuit structure are measured within the scope of the working frequency range in device using vector network analyzer.Step 3: the S parameter measured in step 1 is converted into Y parameter, the value of parasitic capacitance is calculated by Y parameter.Wherein, three port S parameters are converted to Y parameter and are carried out by s2y function in Matlab, and Y parameter representation method is obtained using the equivalent circuit of open test structure.
Description
Technical field
The present invention relates to microwave device testing fields, are related to a kind of one kind of double grid GaAs pHEMT device parasitic capacitor
Open test structure extraction method.
Technical background
Double-gated devices are widely used in power amplifier, phase shifter, frequency mixer and monolithic integrated microwave circuit.Traditional
In modeling method, small-signal model is preferentially established the foundation to facilitate subsequent large-signal model.So accurately establishing small
Signal model is very crucial.
For the small-signal model of single gate device, most-often used method be made by numerical optimization the S parameter of model with
The S parameter fitting measured.However for double grid GaAs pHEMT device, small signal contains ectoparasitism parameter and two
The inside intrinsic parameters of pHEMT add up 29 unknown parameters in total, therefore, it is desirable to pass through the measurement data of three port S parameters
It is very difficult for being fitted.In fact, being difficult the analysis side directly by single gate device since double-gate structure is different from single grid
Method directly applies in double-gated devices.
Deng et al. [Deng W K, Chu T H.Elements extraction of GaAs dual-gate
MESFET small-signal equivalent circuit[J].IEEE Transactions on Microwave
Theory&Techniques, 1998:2383-2390.] propose a set of extraction double grid ectoparasitism parameter and internal intrinsic ginseng
Several processes.Using the method for analysis, by the way that in device bias, under cut-off condition, test frequency is to measure in the case of low frequency
Y parameter is calculated, to directly obtain the value of parasitic capacitance.And in fact, by this in device cut-off, low frequency measurement
The capacitance that method obtains usually has certain variation compared with actual value, and internal some intrinsic parameters join ectoparasitism
Several variations is very sensitive, may be such that the inside intrinsic parameters of extraction are negative value.
The open test structure of single grid is just widely applied after doctor's Wijinen invention for the first time in 1987, using single grid
Test structure can accurately extract parasitic capacitance parameter, L Shen et al. [Sun L, Gao J, Shen L.Direct
Extraction of Equivalent Circuit Parameters for GaAs pHEMT[J].Journal of
Computational&Theoretical Nanoscience, 2015,12 (6): 996-1001 (6)] using analysis method and
Open test structural approach makes the effective frequency of small-signal modeling be up to 110GHz.It can be seen that single grid GaAs pHEMT device is opened
Drive test examination structure can achieve good precision, however, for the open test structure and method of double grid GaAs pHEMT device
It is proposed still without people.
In order to overcome the disadvantages mentioned above of the prior art, the invention proposes one kind to be applied to double grid GaAs pHEMT device
Open test structure, for extracting the external parasitic capacitances of double grid GaAs pHEMT device.
Summary of the invention
The present invention will overcome the disadvantages mentioned above of the prior art, provide it is a kind of applied to double grid GaAs pHEMT device can
In direct, the accurate method for extracting external parasitic capacitances.
To achieve the above object, provided by the present invention a kind of for extracting double grid GaAs pHEMT device parasitic capacitor
Open-circuit structure test method, include the following steps:
Step 1: design open test structure, and establish open test structure equivalent circuit；
Step 2: three port S parameters of measurement open test structure；
Step 3: the S parameter measured in step 2 is converted into Y parameter, parasitic capacitance is calculated by Y parameter
Value.
In the step 1, designed open-circuit structure as shown in Fig. 2, the structure and device under test test structure are similar,
But measured device double grid GaAs pHEMT device is not included.Open test structure includes by double grid GaAs pHEMT device interface
The interconnection line (Interconnect) of extraction and the pad (PAD) being biased with probe contact.Open test structure is equivalent
Circuit is as shown in figure 3, include coupling capacitor part 200 between pad parasitic capacitance portion 100 and pad；
The pad parasitic capacitance portion 100 by first grid parasitic capacitance Cpg1, second grid parasitic capacitance Cpg2 and
Drain parasitic capacitance Cpd is constituted, in which: one end of first grid parasitic capacitance Cpg1 is connected with first grid node G1, separately
One end is connected with the first source node S；One end of second grid parasitic capacitance Cpg2 is connected with second grid node G2, separately
One end is connected with the first source node S；One end of drain parasitic capacitance Cpd is connected with the second drain node D, the other end with
First source node S is connected；
Coupling capacitor part 200 is by coupled capacitor Cg1g2, the first grid between first grid and second grid between the pad
Coupled capacitor Cg2d is constituted between coupled capacitor Cg1d and second grid and drain electrode between pole and drain electrode, in which: first grid and second
One end of coupled capacitor Cg1g2 is connected with first grid node G1 between grid, and the other end is connected with second grid node G2；
One end of coupled capacitor Cg1d is connected with first grid node G1 between first grid and drain electrode, the other end and the second drain node
D is connected；One end of coupled capacitor Cg2d is connected with second grid node G2 between second grid and drain electrode, the other end and second
Drain node D is connected.
In the step 2, the S parameter (scattering parameter) of vector network analyzer measurement open test structure is utilized.Measurement
When, three port S parameters of open-circuit structure are measured within the scope of the working frequency range of device using vector network analyzer, such as
10MHz to 40GHz.
In the step 3, three port S parameters measured in step 2 are converted into Y ginseng by s2y function in Matlab
Number.The equivalent circuit established from step 1 obtains Y parameter matrix, and the value of each parasitic capacitance is acquired by the imaginary part of Y parameter, public
Formula is as follows:
Y11=j ω (Cpg1+Cpg1d+Cpg1g2)
Y22=j ω (Cpg2+Cpg2d)
Y33=j ω (Cpd+Cpg1d+Cpg2d)
Y12=Y21=-j ω Cpg1g2
Y13=Y31=-j ω Cpg1d
Y23=Y32=-j ω Cpg2d
The exact value of available parasitic capacitance is calculated by Y parameter:
Wherein, YPAD indicates the admittance parameter of open test structure equivalent circuit, it is assumed that first grid node G1 port numbers
It is 1, second grid node G2 port numbers are 2, and the second drain node D port numbers are 3, then Y11, Y22, Y33 respectively indicate 1,2,3
The input admittance of port, Y12 indicate that the transfer admittance of port 1 is arrived in port 2, and Y13 indicates that the transfer admittance of port 1 is arrived in port 3,
Y23 indicates that the transfer admittance of port 2 is arrived in port 3.
Wherein, Cpg1 indicates that first grid parasitic capacitance, Cpg2 indicate that second grid parasitic capacitance, Cpd indicate that drain electrode is posted
Raw capacitor, Cg1g2 indicate that first grid indicates to couple electricity between first grid and drain electrode with coupled capacitor, Cg1d between second grid
Hold, Cg2d indicates coupled capacitor between second grid and drain electrode.The value of each parasitic capacitance can be obtained by calculating above.
The beneficial effects of the present invention are:
The present invention, which is directed in the method directly extracted for double grid GaAs pHEMT device parasitic capacitor at present, passes through device
Cut-off, the obtained capacitance of method of low frequency measurement and this inaccurate defect of internal intrinsic parameters, propose a kind of for double
The open test structure extraction of parasitic capacitance method of grid GaAs pHEMT device extracts parasitic capacitance, physical significance by this method
Clear, extracting method is simple, and accuracy is high, can effectively improve the precision of double grid GaAs pHEMT device small-signal model.
Detailed description of the invention
Fig. 1 is double grid GaAs pHEMT small-signal equivalent circuit；
Fig. 2 is open test structure used in the present invention；
Fig. 3 is the equivalent circuit of open test structure；
Fig. 4 is the flow chart of open test structure extraction parasitic capacitance；
Specific embodiment
Below in conjunction with the attached drawing in present example, the technical solution in present example is carried out clear, complete
Description.In without departing substantially from inventive concept spirit and scope, various changes and advantages that will be apparent to those skilled in the art are included in
In the present invention, and with the big protection scope of appended claims.Implement procedures, conditions, experimental methods etc. of the invention, removes
It except the content specially referred to below, is among the general principles and common general knowledge in the art, there are no special restrictions to content by the present invention.
It is provided by the invention a kind of for extracting the open-circuit structure test side of double grid GaAs pHEMT device parasitic capacitor
Method includes the following steps:
Step 1: design open test structure, and establish open test structure equivalent circuit；
Step 2: three port S parameters of measurement open test structure；
Step 3: the S parameter measured in step 2 is converted into Y parameter, parasitic capacitance is calculated by Y parameter
Value.
In the step 1, designed open-circuit structure as shown in Fig. 2, the structure and device under test test structure are similar,
But measured device double grid GaAs pHEMT device is not included.Open test structure includes by double grid GaAs pHEMT device interface
The interconnection line (Interconnect) of extraction and the pad (PAD) being biased with probe contact.Open test structure is equivalent
Circuit is as shown in figure 3, include coupling capacitor part 200 between pad parasitic capacitance portion 100 and pad；
The pad parasitic capacitance portion 100 by first grid parasitic capacitance Cpg1, second grid parasitic capacitance Cpg2 and
Drain parasitic capacitance Cpd is constituted, in which: one end of first grid parasitic capacitance Cpg1 is connected with first grid node G1, separately
One end is connected with the first source node S；One end of second grid parasitic capacitance Cpg2 is connected with second grid node G2, separately
One end is connected with the first source node S；One end of drain parasitic capacitance Cpd is connected with the second drain node D, the other end with
First source node S is connected；
Coupling capacitor part 200 is by coupled capacitor Cg1g2, the first grid between first grid and second grid between the pad
Coupled capacitor Cg2d is constituted between coupled capacitor Cg1d and second grid and drain electrode between pole and drain electrode, in which: first grid and second
One end of coupled capacitor Cg1g2 is connected with first grid node G1 between grid, and the other end is connected with second grid node G2；
One end of coupled capacitor Cg1d is connected with first grid node G1 between first grid and drain electrode, the other end and the second drain node
D is connected；One end of coupled capacitor Cg2d is connected with second grid node G2 between second grid and drain electrode, the other end and second
Drain node D is connected.
In the step 2, the S parameter (scattering parameter) of vector network analyzer measurement open test structure is utilized.Measurement
When, three port S parameters of open-circuit structure are measured within the scope of the working frequency range of device using vector network analyzer, such as
10MHz to 40GHz.
In the step 3, three port S parameters measured in step 2 are converted into Y ginseng by s2y function in Matlab
Number.The equivalent circuit established from step 1 obtains Y parameter matrix, and the value of each parasitic capacitance is acquired by the imaginary part of Y parameter, public
Formula is as follows:
Y11=j ω (Cpg1+Cpg1d+Cpg1g2)
Y22=j ω (Cpg2+Cpg2d)
Y33=j ω (Cpd+Cpg1d+Cpg2d)
Y12=Y21=-j ω Cpg1g2
Y13=Y31=-j ω Cpg1d
Y23=Y32=-j ω Cpg2d
The exact value of available parasitic capacitance is calculated by Y parameter:
Wherein, YPAD indicates the admittance parameter of open test structure equivalent circuit, it is assumed that first grid node G1 port numbers
It is 1, second grid node G2 port numbers are 2, and the second drain node D port numbers are 3, then Y11, Y22, Y33 respectively indicate 1,2,3
The input admittance of port, Y12 indicate that the transfer admittance of port 1 is arrived in port 2, and Y13 indicates that the transfer admittance of port 1 is arrived in port 3,
Y23 indicates that the transfer admittance of port 2 is arrived in port 3.
Wherein, Cpg1 indicates that first grid parasitic capacitance, Cpg2 indicate that second grid parasitic capacitance, Cpd indicate that drain electrode is posted
Raw capacitor, Cg1g2 indicate that first grid indicates to couple electricity between first grid and drain electrode with coupled capacitor, Cg1d between second grid
Hold, Cg2d indicates coupled capacitor between second grid and drain electrode.The value of each parasitic capacitance can be obtained by calculating above.
Claims (1)
1. it is a kind of for extracting the open-circuit structure test method of double grid GaAs pHEMT device parasitic capacitor, include the following steps:
Step 1: design open test structure, and establish open test structure equivalent circuit；
Step 2: three port S parameters of measurement open test structure；
Step 3: the S parameter measured in step 2 is converted into Y parameter, parasitic capacitance is calculated by Y parameter
Value；
In the step 1, open test structure is identical as the test structure of device under test, but does not include tested double grid GaAs
PHEMT device；Open test structure includes the interconnection line for drawing double grid GaAs pHEMT device interface and comes with probe contact
The pad PAD being biased；Open test structure equivalent circuit includes that electricity is coupled between pad parasitic capacitance portion (100) and pad
Hold part (200)；
The pad parasitic capacitance portion (100) is by first grid parasitic capacitance Cpg1, second grid parasitic capacitance Cpg2 and leakage
Pole parasitic capacitance Cpd is constituted, in which: one end of first grid parasitic capacitance Cpg1 is connected with first grid node G1, another
End is connected with the first source node S；One end of second grid parasitic capacitance Cpg2 is connected with second grid node G2, another
End is connected with the first source node S；One end of drain parasitic capacitance Cpd is connected with the second drain node D, the other end and
One source node S is connected；
Coupling capacitor part (200) is by coupled capacitor Cg1g2, first grid between first grid and second grid between the pad
Coupled capacitor Cg2d is constituted between coupled capacitor Cg1d and second grid and drain electrode between drain electrode, in which: first grid and second gate
One end of interpolar coupled capacitor Cg1g2 is connected with first grid node G1, and the other end is connected with second grid node G2；The
One end of coupled capacitor Cg1d is connected with first grid node G1 between one grid and drain electrode, the other end and the second drain node D
It is connected；One end of coupled capacitor Cg2d is connected with second grid node G2 between second grid and drain electrode, the other end and second
Drain node D is connected；
In the step 2, the S parameter of vector network analyzer measurement open test structure is utilized；When measurement, using vector net
Network analyzer measures three port S parameters of open-circuit structure within the scope of the working frequency range of device；
In the step 3, three port S parameters measured in step 2 are converted into Y parameter by s2y function in Matlab；From
The equivalent circuit established in step 1 obtains Y parameter matrix, the value of each parasitic capacitance is acquired by the imaginary part of Y parameter, formula is such as
Shown in lower:
Y11=j ω (Cpg1+Cpg1d+Cpg1g2)
Y22=j ω (Cpg2+Cpg2d)
Y33=j ω (Cpd+Cpg1d+Cpg2d)
Y12=Y21=-j ω Cpg1g2
Y13=Y31=-j ω Cpg1d
Y23=Y32=-j ω Cpg2d
The exact value of available parasitic capacitance is calculated by Y parameter:
Wherein, YPADIndicating the admittance parameter of open test structure equivalent circuit, it is assumed that first grid node G1 port numbers are 1, the
Two gate node G2 port numbers are 2, and the second drain node D port numbers are 3, then Y11, Y22, Y33 respectively indicate 1,2,3 ports
Input admittance, Y12 indicate that the transfer admittance of port 1 is arrived in port 2, and Y13 indicates that the transfer admittance of port 1 is arrived in port 3, and Y23 is indicated
The transfer admittance of port 2 is arrived in port 3；
Wherein, Cpg1 indicates that first grid parasitic capacitance, Cpg2 indicate that second grid parasitic capacitance, Cpd indicate drain parasitic electricity
Hold, Cg1g2 indicate coupled capacitor between first grid and second grid, Cg1d indicate coupled capacitor between first grid and drain electrode,
Cg2d indicates coupled capacitor between second grid and drain electrode；The value of each parasitic capacitance can be obtained by calculating above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710887326.4A CN107907811B (en) | 2017-09-27 | 2017-09-27 | It is a kind of for extracting the open-circuit structure test method of double grid GaAs pHEMT device parasitic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710887326.4A CN107907811B (en) | 2017-09-27 | 2017-09-27 | It is a kind of for extracting the open-circuit structure test method of double grid GaAs pHEMT device parasitic capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107907811A CN107907811A (en) | 2018-04-13 |
| CN107907811B true CN107907811B (en) | 2019-06-11 |
Family
ID=61841051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710887326.4A Active CN107907811B (en) | 2017-09-27 | 2017-09-27 | It is a kind of for extracting the open-circuit structure test method of double grid GaAs pHEMT device parasitic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107907811B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117272885A (en) * | 2022-06-14 | 2023-12-22 | 长鑫存储技术有限公司 | Circuit noise parameter acquisition method and device and electronic equipment |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102542077B (en) * | 2010-12-15 | 2014-07-16 | 中国科学院微电子研究所 | Parameter extraction method of AlGaN/GaN HEMT small-signal model |
| CN102521447B (en) * | 2011-12-08 | 2013-06-19 | 清华大学 | Parametric modeling method of millimeter wave field effect transistor based on binary combination |
| CN104142436B (en) * | 2013-05-07 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | The test structure of three port radio-frequency devices and method of testing |
| CN103995933A (en) * | 2014-06-18 | 2014-08-20 | 上海傲亚微电子有限公司 | Novel transistor small-signal equivalent circuit model |
| CN104298837B (en) * | 2014-11-12 | 2017-06-13 | 东南大学 | Device equivalent circuit model parameter extracting method and pad parasitic parameter extraction method |
| CN105046066A (en) * | 2015-07-02 | 2015-11-11 | 中航（重庆）微电子有限公司 | AlGaN/GaN HETM small-signal model and parameter extraction method thereof |
| CN105138730B (en) * | 2015-07-27 | 2018-05-18 | 电子科技大学 | GaN high electron mobility transistor small-signal model parameter extracting method |
| CN107167724B (en) * | 2017-06-02 | 2019-08-13 | 厦门市三安集成电路有限公司 | A kind of small measuring signal goes embedding method |
-
2017
- 2017-09-27 CN CN201710887326.4A patent/CN107907811B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107907811A (en) | 2018-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105787210B (en) | GaN high electron mobility transistor small-signal circuit model parameter extracting method | |
| CN105426570B (en) | GaN HEMT large-signal model improved method based on active compensation sub-circuit | |
| CN105138730B (en) | GaN high electron mobility transistor small-signal model parameter extracting method | |
| CN104298837B (en) | Device equivalent circuit model parameter extracting method and pad parasitic parameter extraction method | |
| CN106529102A (en) | AlGaN/GaN HEMT small signal model and parameter extraction method thereof | |
| CN106372357B (en) | A kind of GaN HEMT nonlinear noise method for establishing model | |
| CN105825005B (en) | The construction method of the non-linear scalable model of GaN high electron mobility transistor | |
| CN107167724B (en) | A kind of small measuring signal goes embedding method | |
| US8253421B2 (en) | Impedance measurement method and impedance measurement device | |
| CN105184032A (en) | Establishing method for improved HBT small-signal equivalent circuit model | |
| CN107907811B (en) | It is a kind of for extracting the open-circuit structure test method of double grid GaAs pHEMT device parasitic capacitor | |
| CN105844059A (en) | Modeling method of microwave high-power transistor | |
| CN108037159B (en) | A kind of cytoactive detection method and device based on impedance spectrum integral feature | |
| CN206421387U (en) | AlGaN/GaN HEMT small-signal models | |
| CN101976293A (en) | MOS (Metal Oxide Semiconductor) transistor radio frequency macro model establishing method | |
| CN111679171A (en) | Circuit topological structure based on interconnection line unit and de-embedding method for interconnection line unit cascade | |
| Cho et al. | A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs | |
| CN109683078B (en) | Schottky diode testing method and device | |
| CN108899320A (en) | A kind of MOSFET gate oxide capacitance calibration structure | |
| Stärke et al. | A deembedding method for reciprocal three-port devices demonstrated with 200-GHz baluns | |
| CN106055765B (en) | The noise model method for building up of millimeter wave FET | |
| Huang et al. | A new extraction method of extrinsic elements of GaAs/GaN HEMTs | |
| CN107895089B (en) | Improved method for extracting parameters of test structure of MOSFET (metal-oxide-semiconductor field effect transistor) transistor of integrated circuit | |
| CN110096729A (en) | A kind of method of determining port parasitic inductance and scalable model | |
| CN106250622B (en) | A kind of FET microwave noise method for establishing model |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230323 Address after: 316000 Room 202, 11 Baichuan Road, Lincheng street, Dinghai District, Zhoushan City, Zhejiang Province (centralized office) Patentee after: ZHEJIANG JISU HEXIN TECHNOLOGY CO.,LTD. Address before: 310027 No. 38, Zhejiang Road, Hangzhou, Zhejiang, Xihu District Patentee before: ZHEJIANG University |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230627 Address after: Plant 1, No. 13, Guiyang Avenue, Yantai Economic and Technological Development Zone, Shandong Province, 264000 Patentee after: Yantai Xin Yang Ju Array Microelectronics Co.,Ltd. Address before: 316000 Room 202, 11 Baichuan Road, Lincheng street, Dinghai District, Zhoushan City, Zhejiang Province (centralized office) Patentee before: ZHEJIANG JISU HEXIN TECHNOLOGY CO.,LTD. |
|
| TR01 | Transfer of patent right |