CN111679171B - Circuit topological structure based on interconnection line unit and de-embedding method for interconnection line unit cascade - Google Patents
Circuit topological structure based on interconnection line unit and de-embedding method for interconnection line unit cascade Download PDFInfo
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention provides a circuit topological structure based on interconnection line units and a cascading de-embedding method, which are characterized in that firstly, scattering parameter tests are respectively carried out on a device test structure, an open circuit test structure, a through test structure and a short circuit test structure; dividing the interconnection line in the direct connection test structure into a plurality of adjacent interconnection line units, establishing a topological structure and a cascade model of the circuit unit for the interconnection line units, and calculating scattering parameters of the direct connection interconnection line units, the input interconnection line units and the output interconnection line units; acquiring scattering parameters of a grounding interconnection line and a grounding through hole in a short-circuit test structure; and removing the scattering parameters of the pad, the input interconnection unit, the output interconnection unit, the device grounding interconnection line and the grounding through hole from the testing scattering parameters of the device testing structure to obtain the scattering parameters of the device to be tested. The invention has simple structure, high precision and scalability, and can realize the performance which can be realized respectively only by depending on complex structures or different modes in the traditional technology.
Description
Technical Field
The invention relates to the field of radio frequency device testing, in particular to a circuit topological structure based on interconnection line units and an interconnection line unit cascade connection de-embedding method.
Background
Establishing an accurate equivalent circuit model (modeling for short) for integrated circuit devices (such as transistors, inductors and the like) is an important basis for circuit design and is a core factor for improving the yield and reducing the research and development cost. The test is the basis of equivalent circuit modeling of the device, and when the integrated circuit device is tested on a chip, because the probe cannot be directly connected with the device, embedded structures such as a bonding pad, an interconnection line on an input/output (I/O) chip and the like must be added on an I/O test port. In order to obtain parameters of the equivalent circuit model of the device, the influence of the embedded structure needs to be accurately removed through an external embedding removing (for short, embedding removing) step, and test data of the device itself is obtained.
Document 1(Yunqiu Wu, Ya' nan Hao, Jun Liu, Chenxi Zhao, Yuehang Xu, Wenyan Yin, and Kai Kang, — Improved ultra wide band Open-Short De-Embedding Method Applied up to 220GHz, "IEEE Transactions on Components, Packaging and Manufacturing Technology, vol.8, No.2, pp.269-276, feb.2018) establishes An equivalent circuit model based on elements for the Open and Short circuit test structures, and removes the out-Embedding parasitics introduced by the pads and the interconnect lines by extracting the element parameters of the equivalent circuit model. The method depends on an equivalent circuit model and a specific element structure and parameter values, aiming at a complex equivalent circuit model structure, the extraction of the element parameters (called parameters for short) of the equivalent circuit model by using an analytical method is very difficult, and the extraction of the element parameters of the model by using a numerical method has the problem of multi-value solution, so that the accuracy of removing the external embedding is reduced.
In order to improve the defect of poor De-Embedding precision of a single pass structure, various types of complex pass structures are widely studied, including a double pass structure (document 2: X.S.Loo, K.S.Yeo, K.W.J.Chew, L.H.K.Chan, S.N.Ong, M.A.Do, and C.C.Boon, A new micrometer-Wave fixed Method based On synthesized cable network model, "IEEE Electron Device let, vol.34, 3, pp.447-449, Mar.2013), and a pass/half pass/Short circuit structure (document 3: Xiao Li, Yong Zhang, OupengLi, Tianhao Ren, Fanghou Guo, Chengyan Lu, Wei, Ruhru, and Wahrin, Cha-Device and De-noise, IEEE-Method On, Chapter-Device On, Chapter-noise, Chapter-6-Method On, IEEE.S.S.S.N.E.E.D. 12, and C.C.Boon. The through structures of the complex structures do not depend on a specific equivalent circuit model, have higher precision, but have the defect of no scalability, and when devices with different sizes are more, a corresponding number of through/semi-through test structures need to be tested, so that the chip area is increased, and the cost is increased.
For the problem that the conventional cascaded unit-based de-embedding method does not have scalability, document 4(m. -h.cho, g. -w.huang, y. -h.wang, l. -k.wu. -. a scalable noise de-embedding technique for on-wafer microwave device characterization, "IEEE micro.wireless company.let., vol.15, No.10, pp.649-651, oct.2005) proposes a de-embedding method based on a standard transmission line equation. Through testing a straight-through test structure with a certain length, parameters such as characteristic impedance, propagation coefficient and the like of the transmission line are obtained through calculation by using a standard transmission line equation, and thus scattering parameters of the transmission line with any length are obtained through calculation. However, the circuit model on which the standard transmission line equation is based is too simple to reflect the transmission line characteristics well in the higher frequency band.
In the traditional de-embedding technology, some technical approaches need to depend on complex structures in order to achieve higher de-embedding precision, the number of structures needing to be tested is large, and scalability is not available; some technical approaches have scalability, but lower precision. A simple, precise, scalable de-embedding technique is lacking to date.
Disclosure of Invention
The invention aims to: aiming at the defects of the existing de-embedding technology, the invention aims to provide a circuit topological structure based on interconnection line units and a de-embedding method for interconnection line unit cascade, provides an external embedding technology with simple structure, high precision and scalability, and can realize the performance that the traditional technology can be respectively realized only by depending on a complex structure or different modes.
The technical scheme is as follows: in order to achieve the purpose, the invention adopts the following technical scheme:
a circuit topology structure based on interconnection line units and a de-embedding method of interconnection line unit cascade are provided. The method comprises the steps of firstly, respectively testing scattering parameters (S-parameters) of a device testing structure, an open-circuit testing structure, a through testing structure and a short-circuit testing structure, obtaining the scattering parameters of a bonding pad by using the scattering parameters of the open-circuit testing structure, and removing the scattering parameters of the bonding pad from the scattering parameters of the through testing structure. The interconnect in the through test structure is then divided into several adjacent interconnect cells, and for each interconnect cell a topology of circuit cells is established (by the series impedance Z) s Parallel admittance Y sub Or other parameters transformed from S parameters), then a cascaded model of the interconnect cells is established,and according to series impedance Z s Parallel admittance Y sub Calculating to obtain scattering parameters of the input interconnection line unit and the output interconnection line unit according to the equal proportion relation between the scattering parameters and the length; removing the scattering parameters of the pad and the input interconnection line unit and the output interconnection line unit of the short-circuit test structure to obtain the scattering parameters of the grounding interconnection line and the grounding through hole in the short-circuit test structure; if the interconnection line in the short-circuit test structure is long and cannot be ignored, establishing an interconnection line circuit unit which is the same as the straight-through interconnection line for the short-circuit interconnection line, wherein the series impedance and the parallel admittance of the interconnection line circuit unit and the series impedance and the parallel admittance of the straight-through interconnection line unit respectively meet the equal proportional relation of the lengths; and finally, removing the scattering parameters of the test scattering parameters of the device test structure from the bonding pad, the input interconnection unit, the output interconnection unit, the device grounding interconnection line and the grounding through hole to obtain the scattering parameters of the device to be tested. Compared with the traditional technology, the technology has the advantages of simple structure, high precision and scalability, and can realize the performance which can be realized respectively only by depending on a complex structure or different modes.
Preferably, the interconnection line in the through test structure is divided into a plurality of adjacent through interconnection line units, and a circuit unit topological structure of an equivalent circuit is established for each through interconnection line unit; the circuit unit topology is composed of series impedance Z s Parallel admittance Y sub Or pi-type topological structure composed of other parameters converted from S parameters, and does not depend on specific elements such as resistance, inductance and capacitance.
Preferably, the ABCD matrix parameter expression of each through interconnection line unit is
Where j represents adjacent different through interconnect line cells,
for the series resistance of the different through interconnect line cells,
for the parallel admittance of different through interconnect line cells,
ABCD matrix of different through interconnect line cells.
Preferably, the ABCD matrix of each interconnect line in the cascade model of the through interconnect line unit is multiplied by the ABCD matrix divided into several adjacent interconnect line units.
Preferably, the ABCD matrix parameters of the through interconnection line unit
The series impedance and the parallel admittance of different direct connection interconnection line units satisfy the relationship in direct proportion to the length of the interconnection line unit:
wherein L is m 、L n Representing the length of the two-segment through interconnect line cell,
representing the series resistance of two sections of through-interconnect cells,
representing the parallel admittance of two sections of through-interconnection cells.
Preferably, the circuit topology based on the interconnection line unit and the de-embedding method of interconnection line unit cascade comprise the following steps:
(1) measuring scattering parameters [ S ] of open circuit test structures Open ]And transforms it into admittance parameter [ Y Open ]，
By the formula
Calculating to obtain ABCD matrix parameters of the bonding pad
(2) Measuring scattering parameters [ S ] of a through test structure Thru ]And converts it into ABCD matrix parameters [ A ] Thru ]By the formula [ A INT ]＝[A Pad ] -1 [A Thru ][A Pad ] -1 Obtaining the ABCD matrix parameter [ A ] of the interconnection line in the direct-through test structure INT ]；
(3) Dividing the interconnecting line in the through test structure into several different interconnecting line units, marking the input interconnecting line unit as INT1, and marking the corresponding ABCD matrix parameter as
The output interconnection line unit is marked as INT2, and the ABCD matrix parameter is marked as
Recording other cascaded through interconnection line units (namely interconnection line units between INT1 and INT 2) as INT3, and recording ABCD matrix parameters as
By means of a relational expression
Is calculated to obtain
(4) The ABCD matrix parameter after the cascade connection of the pad and the input interconnection line unit INT1 is recorded as [ A ] IN ]And the ABCD matrix parameter after the cascade connection of the bonding pad and the output interconnection line unit INT2 is marked as [ A ] OUT ]Respectively using relational expressions
Is calculated to obtain [ A IN ]，[A OUT ]；
(5) Measuring scattering parameters [ S ] of short circuit test structures Short ]And converting it into ABCD matrix parameters [ A ] Short ]By the formula [ A Short,via+TL ]＝[A IN ] -1 [A Short ][A OUT ] -1 Obtaining ABCD matrix parameter [ A ] of grounding interconnection line and grounding through hole in short circuit test structure Short,via+TL ]Obtaining [ Z ] by converting the ABCD matrix parameters into Z parameters Short,via+TL ]；
(6) Measuring scattering parameters [ S ] of device test structures DUT ]And converts it into ABCD matrix parameters [ A ] DUT ]By the formula [ A Dev,via+TL ]＝[A IN ] -1 [A DUT ][A OUT ] -1 Obtaining ABCD matrix parameter [ A ] of the device to be tested containing the grounding interconnection line and the grounding through hole Dev,via+TL ]Obtaining [ Z ] by converting the ABCD matrix parameters into Z parameters Dev,via+TL ]；
(7) By the formula [ Z Dev ]＝[Z Dev,via+TL ]-[Z Short,via+TL ]And calculating to obtain the Z parameter [ Z ] of the device to be measured Dev ]Converting the Z parameter into S parameter to obtain S parameter [ S ] of the device to be tested Dev ]；
Preferably, when the width of the interconnection line unit in the short-circuit test structure is the same as that in the through structure, the ABCD matrix parameter expression of the interconnection line unit in the short-circuit test structure is as follows
Where j represents adjacent different through interconnect line cells,
for the series impedances of the different short-circuited interconnect line cells,
for the parallel admittance of different short-circuited interconnect line cells,
ABCD matrixes of different short circuit interconnection line units; series impedance of the short-circuit interconnection line unit
Parallel admittance
And series resistance of through interconnection line unit
Parallel admittance
The lengths of the interconnection line units are in direct proportion to each other:
wherein, K m 、K n Representing the length of the short interconnect cell and the through interconnect cell respectively,
representing the series impedances of the short interconnect cell and the through interconnect cell respectively,
representing the parallel admittance of the short interconnect cell and the through interconnect cell, respectively.
Preferably, the circuit topology based on the interconnection line unit and the de-embedding method of interconnection line unit cascade include the following steps:
(1) measuring scattering parameters [ S ] of open circuit test structures Open ]And transforming it into admittanceParameter [ Y Open ]，
By the formula
Calculating to obtain ABCD matrix parameters of the bonding pad
(2) Measuring scattering parameters [ S ] of a through test structure Thru ]And converts it into ABCD matrix parameters [ A ] Thru ]By the formula
Obtaining ABCD matrix parameters of interconnection lines in through test structure
(3) Dividing the interconnecting line in the through test structure into several different interconnecting line units, marking the input interconnecting line unit as INT1, and marking the corresponding ABCD matrix parameter as
The output interconnection line unit is marked as INT2, and the ABCD matrix parameter is marked as
Recording other cascaded through interconnection line units (namely interconnection line units between INT1 and INT 2) as INT3, and recording ABCD matrix parameters as
By means of a relational expression
Is calculated to obtain
(4) ABCD matrix parameters through interconnect cells
The series impedances INT1, INT2 and INT3 were calculated
And parallel admittance
(5) Based on the series impedance of the short-circuited interconnection line unit
Parallel admittance
And series resistance of through interconnection line cell
Parallel admittance
The mutual requirements respectively satisfy the relationship in direct proportion to the length of the interconnection line unit, and the series impedance of the interconnection line unit between the grounding through hole and the device in the short circuit test structure is calculated
And parallel admittance
Thereby calculating the impedance [ Z ] of the interconnection line unit between the grounding through hole and the device in the short circuit test structure Short,via+TL ]；
(6) The ABCD matrix parameter of the cascade connection of the bonding pad and the input interconnection line unit INT1 is marked as [ A ] IN ]And the ABCD matrix parameter of the cascade connection of the pad and the output interconnection line unit INT2 is marked as [ A ] OUT ]Respectively using relational expressions
Calculating to obtain [ A ] IN ]，[A OUT ]；
(7) Measuring scattering parameters [ S ] of device test structures DUT ]And converts it into ABCD matrix parameters [ A ] DUT ]By the formula [ A Dev,via+TL ]＝[A IN ] -1 [A DUT ][A OUT ] -1 Obtaining ABCD matrix parameter [ A ] of the device to be tested containing the grounding interconnection line and the grounding through hole Dev,via+TL ]，
(8) By the formula [ Z Dev ]＝[Z Dev,via+TL ]-[Z Short,via+TL ]And calculating to obtain the Z parameter [ Z ] of the device to be tested Dev ]Converting the Z parameter into S parameter to obtain S parameter [ S ] of the device to be tested Dev ]。
Has the advantages that: compared with the prior art, the invention has the following advantages: the invention discloses a circuit topological structure based on interconnection line units and an embedding removing method of interconnection line unit cascade. The technology of the invention has the advantages of simple structure, high precision and scalability, and can realize the performance which can be realized respectively only by depending on a complex structure or different modes in the traditional technology.
Drawings
FIG. 1 is a schematic diagram of a DUT and an embedded structure according to an embodiment of the invention.
Fig. 2 is a schematic diagram of an open circuit test structure according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of a pass-through test structure according to an embodiment of the present invention.
FIG. 4 is a schematic diagram of a short circuit test structure according to an embodiment of the invention.
FIG. 5 is a schematic diagram of a two-port network cascade of a device test structure according to an embodiment of the present invention.
Figure 6 is a schematic diagram of an interconnect line dividing interconnect line unit in a through test structure according to an embodiment of the present invention.
FIG. 7 shows the gate-source voltage of the device under test (transistor) being equal to-4V and the drain-source voltage being equal to 0V bias condition, field effect transistor intrinsic grid source capacitance C extracted at different frequency points gs Wherein the open squares represent the conventional open-short method, the open triangles represent the conventional open-straight-through method, and the open circles represent the present technique.
FIG. 8 shows the intrinsic gate-drain capacitance C of the FET extracted at different frequency points under the bias condition that the gate-source voltage of the device under test (transistor) is equal to-4V and the drain-source voltage is equal to 0V gd Wherein the open squares represent the conventional open-short method, the open triangles represent the conventional open-straight-through method, and the open circles represent the present technique.
Detailed Description
The present invention is further illustrated by the following examples, which are intended to be purely exemplary and are not intended to limit the scope of the invention, which is defined in the appended claims, as may be amended by those skilled in the art upon reading the present invention, and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
In the circuit topological structure based on the interconnection line unit and the de-embedding method of interconnection line unit cascade, test scattering parameters of a device test structure, an open circuit test structure, a direct connection test structure and a short circuit test structure are respectively obtained; and obtaining the scattering parameters of the bonding pad by using the scattering parameters of the open-circuit test structure, and removing the scattering parameters of the bonding pad from the scattering parameters of the through-circuit test structure. Then, the interconnection line in the through test structure is divided into a plurality of adjacent interconnection line units, a topological structure (a circuit topological structure formed by series impedance Zs, parallel admittance Ysub or other parameters converted from S parameters) of the circuit unit is established for each interconnection line unit, and then a cascade model of the interconnection line units is established, so that scattering parameters of each interconnection line unit including the input interconnection line unit and the output interconnection line unit are obtained through calculation. And removing the scattering parameters of the pad and the input interconnection line unit and the output interconnection line unit from the scattering parameters of the short-circuit test structure to obtain the scattering parameters of the grounding interconnection line and the grounding through hole in the short-circuit test structure. And finally, removing the scattering parameters of the test scattering parameters of the device test structure from the bonding pad, the input interconnection unit, the output interconnection unit, the device grounding interconnection line and the grounding through hole to obtain the scattering parameters of the device to be tested. Compared with the traditional technology, the technology has the advantages of simple structure, high precision and scalability, and can realize the performance which can be realized respectively only by depending on a complex structure or different modes. The method is suitable for microwave testing and modeling of various devices such as transistors, inductors, transformers, resistors, capacitors and the like.
The following describes a specific parasitic parameter extraction process according to an embodiment of the present invention with reference to a specific example.
When testing an integrated circuit device on a chip, since a probe cannot be directly connected with the device, embedded structures such as a bonding pad and an interconnection line on an input/output test port must be added, and the device test structure in the embodiment of the invention is shown in fig. 1. In order to obtain parameters of the equivalent circuit model of the device, the influence of the embedded structure needs to be accurately removed through an external embedding removing step, and test data of the device is obtained.
The invention provides a circuit topological structure based on interconnection line units and an embedding removing method for interconnection line unit cascade connection. The open circuit test structure is shown in fig. 2, the through test structure is shown in fig. 3, and the short circuit test structure is shown in fig. 4. The open circuit test structure is not connected with a device to be tested, and is not provided with an input interconnection line, an output interconnection line, a grounding interconnection line of the device to be tested and a grounding through hole; the through test structure is not connected with the device to be tested, the input bonding pad and the output bonding pad are connected by using an interconnecting wire, and the device to be tested is not provided with a grounding interconnecting wire and a grounding through hole; the short circuit test structure is not connected with the device to be tested, the input bonding pad and the output bonding pad are connected through the interconnecting wire, and the grounding interconnecting wire and the grounding through hole of the device to be tested are reserved.
For a 0.1 μm GaN process, a field effect transistor with a size of 1 × 50 μm, the pad, the interconnection line, and the device unit cascade form of the device test structure are shown in fig. 5. A circuit topological structure based on interconnection line units and a de-embedding method of interconnection line unit cascade are disclosed, which comprises the following steps:
(1) measuring scattering parameters [ S ] of open circuit test structures Open ]And transforms it into admittance parameter [ Y Open ]，
By the formula
Calculating to obtain ABCD matrix parameters of the bonding pad
(2) Measuring scattering parameters [ S ] of a through test structure Thru ]And converts it into ABCD matrix parameters [ A ] Thru ]By the formula [ A INT ]＝[A Pad ] -1 [A Thru ][A Pad ] -1 Obtaining the ABCD matrix parameter [ A ] of the interconnection line in the direct-through test structure INT ]；
(3) Dividing the interconnect line in the through test structure into three different interconnect line units, as shown in fig. 6, marking the input interconnect line unit as INT1, and marking the corresponding ABCD matrix parameter as INT1
The output interconnection line unit is marked as INT2, and the ABCD matrix parameter is marked as
The other cascaded through interconnect line cells (i.e., the interconnect line cells between INT1 and INT 2) are denoted as INT3, and the ABCD matrix parameters are denoted as ABCD matrix parameters
The ABCD matrix parameter expression of the interconnection line units INT1, INT2 and INT3 is as follows
Wherein j represents an adjacent isAs with the through-interconnection line cells,
for the series resistance of different through interconnect line cells,
for the parallel admittance of different through interconnect line cells,
ABCD matrixes of different through interconnection line units; the series impedance and the parallel admittance of the three interconnection line units mutually satisfy the relationship in direct proportion to the length of the interconnection line unit:
wherein L is 0 Is the total length of the interconnect line in the through test structure, L 1 And L 2 The lengths of the input interconnect line and the output interconnect line, respectively. Based on the device test structure and the through test structure layout of the embodiment, the series impedance of each interconnection line unit is obtained through calculation
And parallel admittance
The relationship between them is:
by means of a relational expression
Is calculated to obtain
(4) The ABCD matrix parameter of the cascade connection of the pad and the input interconnection line unit INT1 is marked as [ A ] IN ]And the ABCD matrix parameter of the cascade connection of the bonding pad and the output interconnection line unit INT2 is marked as [ A ] OUT ]Respectively using relational expressions
Calculating to obtain [ A ] IN ]，[A OUT ]；
(5) Measuring scattering parameters [ S ] of short circuit test structures Short ]And converts it into ABCD matrix parameters [ A ] Short ]By the formula [ A Short,via+TL ]＝[A IN ] -1 [A Short ][A OUT ] -1 Obtaining ABCD matrix parameter [ A ] of grounding interconnection line and grounding through hole in short circuit test structure Short,via+TL ]Obtaining [ Z ] by converting the ABCD matrix parameters into Z parameters Short,via+TL ]；
(6) Measuring scattering parameters [ S ] of device test structures DUT ]And converts it into ABCD matrix parameters [ A ] DUT ]By the formula [ A Dev,via+TL ]＝[A IN ] -1 [A DUT ][A OUT ] -1 And obtaining ABCD matrix parameters [ A ] of the device to be tested comprising the grounding interconnection line and the grounding through hole Dev,via+TL ]Obtaining [ Z ] by converting the ABCD matrix parameters into Z parameters Dev,via+TL ]；
(7) By the formula [ Z Dev ]＝[Z Dev,via+TL ]-[Z Short,via+TL ]And calculating to obtain the Z parameter [ Z ] of the device to be measured Dev ]Converting the Z parameter into S parameter to obtain S parameter [ S ] of the device to be tested Dev ]；
According to the circuit topological structure based on the interconnection line unit and the de-embedding step of interconnection line unit cascade, extracting intrinsic gate-source capacitance C on different frequency points from the field effect transistor without the external embedding effect in a frequency range of 0-66GHz gs And gate-drain capacitance C gd The curves are shown in fig. 7 and fig. 8, respectively; by contrast, the field effect transistor intrinsic gate-source capacitance C extracted by the traditional open-short circuit method and the open-through method gs And a drain-source capacitance C gd The capacitance value at different frequency points changes with the frequency change, and the intrinsic grid-source capacitance C of the field effect transistor extracted by the method of the invention gs And a drain-source capacitance C gd The capacitance values at different frequency points tend to be a fixed value, which shows that the external embedding effect in the device testing structure can be removed with high precision by using the method.
Claims (8)
1. A de-embedding method based on interconnection line unit cascade is characterized by comprising the following steps:
step 1: respectively acquiring test S parameters of a device test structure, an open circuit test structure, a direct connection test structure and a short circuit test structure;
step 2: obtaining the S parameter of the bonding pad by using the testing S parameter of the open-circuit testing structure, and removing the S parameter of the bonding pad from the testing S parameter of the through testing structure;
and 3, step 3: dividing the interconnection lines in the through test structure into a plurality of adjacent through interconnection line units, establishing a topological structure of a circuit unit for each through interconnection line unit, establishing a cascade model of the through interconnection line units, and calculating to obtain S parameters of an input interconnection line unit and an output interconnection line unit;
and 4, step 4: removing S parameters of a pad, an input interconnection line unit and an output interconnection line unit from the test S parameters of the short-circuit test structure to obtain S parameters of a grounding interconnection line and a grounding through hole in the short-circuit test structure;
and 5: and removing S parameters of the test S parameters of the device test structure from the bonding pad, the input interconnection unit, the output interconnection unit, the grounding interconnection line and the grounding through hole to obtain the S parameters of the device to be tested.
2. Method according to claim 1, characterized in that the circuit cell topology in step 3 is composed of a series impedance Z s Parallel admittance Y sub The formed pi-type topological structure is formed without depending on specific resistance, inductance and capacitance.
3. The method of claim 2, wherein the ABCD matrix parameter expression of each through interconnection line unit is
Wherein j represents adjacent different through interconnect line cells,
for the series resistance of the different through interconnect line cells,
for the parallel admittance of different through interconnect line cells,
an ABCD matrix of different through interconnect line cells.
4. The method of claim 1, the ABCD matrix of each through interconnection line in the cascaded model of through interconnection line units being multiplied by the ABCD matrix divided into several segments of adjacent through interconnection line units.
5. The method of claim 3, ABCD matrix parameters of the through interconnect line cells
Where j represents adjacent different through interconnect line cells,
for the series resistance of the different through interconnect line cells,
for the parallel admittance of different through interconnect line cells,
ABCD matrixes of different through interconnection line units;
the series impedance and the parallel admittance of different direct connection interconnection line units satisfy the relationship in direct proportion to the length of the direct connection interconnection line units:
wherein L is m 、L n Representing the length of the two-segment through interconnect line cell,
representing the series resistance of two sections of through-interconnect cells,
representing the parallel admittance of two sections of through-interconnection cells.
6. The method of claim 1,2,3, 4 or 5, comprising the steps of:
(1) measuring scattering parameters [ S ] of open circuit test structures Open ]And transforms it into admittance parameter [ Y Open ]，
By the formula
Calculating to obtain ABCD matrix parameters of the bonding pad
(2) Measuring scattering parameters [ S ] of a through test structure Thru ]And converts it into ABCD matrix parameters [ A ] Thru ]By the formula
Obtaining ABCD matrix parameters of interconnection lines in through test structure
(3) Dividing the interconnecting line in the through test structure into several different interconnecting line units, recording the input interconnecting line unit as INT1, and recording the corresponding ABCD matrix parameter as
The output interconnection line unit is marked as INT2, and the ABCD matrix parameter is marked as
Marking the other cascaded through interconnection line units, namely the interconnection line units between INT1 and INT2 as INT3, and marking the ABCD matrix parameters as INT3
By means of a relational expression
Is calculated to obtain
(4) The ABCD matrix parameter after the cascade connection of the pad and the input interconnection line unit INT1 is recorded as [ A ] IN ]And the ABCD matrix parameter after the cascade connection of the pad and the output interconnection line unit INT2 is recorded as [ A ] OUT ]Respectively using relational expressions
Is calculated to obtain [ A IN ]，[A OUT ]；
(5) Measuring scattering parameters [ S ] of short circuit test structures Short ]And converting it into ABCD matrix parameters[A Short ]By the formula [ A Short,via+TL ]＝[A IN ] -1 [A Short ][A OUT ] -1 Obtaining ABCD matrix parameter [ A ] of grounding interconnection line and grounding through hole in short circuit test structure Short,via+TL ]By using the ABCD matrix parameter [ A ] Short,via+TL ]Converting into Z parameter to obtain [ Z Short ,via+TL ]；
(6) Measuring scattering parameters [ S ] of device test structures DUT ]And converts it into ABCD matrix parameters [ A ] DUT ]By the formula [ A Dev,via+TL ]＝[A IN ] -1 [A DUT ][A OUT ] -1 And obtaining ABCD matrix parameters [ A ] of the device to be tested comprising the grounding interconnection line and the grounding through hole Dev,via+TL ]By using the ABCD matrix parameter [ A ] Dev,via+TL ]Converting into Z parameter to obtain [ Z ] Dev,via+TL ]；
(7) By the formula [ Z Dev ]＝[Z Dev,via+TL ]-[Z Short,via+TL ]And calculating to obtain the Z parameter [ Z ] of the device to be measured Dev ]The parameter Z is Dev ]Converting into S parameter to obtain S parameter [ S ] of the device to be tested Dev ]。
7. The method of claim 1, wherein when the width of the short interconnect line unit in the short circuit test structure is the same as that in the through test structure, the ABCD matrix parameter expression of the short interconnect line unit in the short circuit test structure is
Wherein j represents a short-circuit interconnection line unit between different sections,
for the series impedances of the different short-circuited interconnect line cells,
for the parallel admittance of different short-circuited interconnect line cells,
ABCD matrixes of different short circuit interconnection line units; series impedance of the short-circuit interconnection line unit
Parallel admittance
And series resistance of through interconnection line unit
Parallel admittance
The lengths of the interconnection line units are in direct proportion to each other:
wherein, K m 、K n Representing the length of the short interconnect cell and the through interconnect cell respectively,
representing the series impedances of the short interconnect cell and the through interconnect cell respectively,
representing the parallel admittance of the short interconnect cell and the through interconnect cell, respectively.
8. The method of claim 1,2 or 7, comprising the steps of:
(1) measuring scattering parameters [ S ] of open circuit test structures Open ]And transforms it into admittance parameter [ Y Open ]，
By the formula
Calculating to obtain ABCD matrix parameters of the bonding pad
(2) Measuring scattering parameters [ S ] of a through-test structure Thru ]And converts it into ABCD matrix parameters [ A ] Thru ]By the formula
Obtaining ABCD matrix parameters of interconnection lines in through test structure
(3) Dividing the interconnecting line in the through test structure into several different interconnecting line units, marking the input interconnecting line unit as INT1, and marking the corresponding ABCD matrix parameter as
The output interconnection line unit is marked as INT2, and the ABCD matrix parameter is marked as
Marking the other cascaded through interconnection line units, namely the interconnection line units between INT1 and INT2 as INT3, and marking the ABCD matrix parameters as INT3
By means of a relational expression
Is calculated to obtain
(4) ABCD matrix parameters through interconnection line cells
The series impedances INT1, INT2 and INT3 were calculated
j is 1,2,3, and parallel admittance
j＝1,2,3；
(5) Based on the series impedance of the short-circuited interconnection line unit
Parallel admittance
And series resistance of through interconnection line unit
Parallel admittance
The mutual relation which is in direct proportion to the length of the interconnection line unit is respectively satisfied, and the series impedance of the short circuit interconnection line unit between the grounding through hole and the device in the short circuit test structure is calculated
And parallel admittance
Thereby calculating the impedance [ Z ] of the interconnection line unit between the grounding through hole and the device in the short circuit test structure Short,via+TL ]；
(6) The ABCD matrix parameter of the cascade connection of the bonding pad and the input interconnection line unit INT1 is marked as [ A ] IN ]And the ABCD matrix parameter of the cascade connection of the bonding pad and the output interconnection line unit INT2 is marked as [ A ] OUT ]Respectively using relational expressions
Is calculated to obtain [ A IN ]，[A OUT ]；
(7) Measuring scattering parameters [ S ] of device test structures DUT ]And converts it into ABCD matrix parameters [ A ] DUT ]By the formula [ A Dev,via+TL ]＝[A IN ] -1 [A DUT ][A OUT ] -1 And obtaining ABCD matrix parameters [ A ] of the device to be tested comprising the grounding interconnection line and the grounding through hole Dev,via+TL ](ii) a By dividing the ABCD matrix parameter [ A ] Dev,via+TL ]Converting into Z parameter to obtain [ Z Dev,via+TL ]；
(8) By the formula [ Z Dev ]＝[Z Dev,via+TL ]-[Z Short,via+TL ]And calculating to obtain the Z parameter [ Z ] of the device to be tested Dev ]The parameter Z is Dev ]Converting into S parameter to obtain S parameter [ S ] of the device to be tested Dev ]。
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