CN108664717B - De-embedding method of millimeter wave device on-chip test structure - Google Patents
De-embedding method of millimeter wave device on-chip test structure Download PDFInfo
- Publication number
- CN108664717B CN108664717B CN201810391173.9A CN201810391173A CN108664717B CN 108664717 B CN108664717 B CN 108664717B CN 201810391173 A CN201810391173 A CN 201810391173A CN 108664717 B CN108664717 B CN 108664717B
- Authority
- CN
- China
- Prior art keywords
- open
- parameter
- short
- circuit
- embedding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a de-embedding method of a millimeter wave device on-chip test structure, which comprises the following steps: s01: forming a device to be tested and an open-circuit de-embedding structure and a short-circuit de-embedding structure corresponding to the device to be tested on a silicon substrate; s02: carrying out S parameter test on the device to be tested, the open circuit de-embedding structure and the short circuit de-embedding structure; s03: simulating a plate capacitor by using an electromagnetic field simulation model, wherein the plate capacitor is used for simulating a parasitic capacitor generated in the open circuit de-embedding structure; and obtaining an additional capacitance value of the capacitor; s04: and converting the S parameter of the open circuit de-embedding structure obtained by the test into a Y parameter, removing the additional capacitor in the open circuit de-embedding structure, and further performing de-embedding calculation to obtain the S parameter of the device to be tested. The de-embedding method of the millimeter wave device on-chip test structure disclosed by the invention can remove the parasitic effect of the on-chip test structure caused between the PAD structure and the additional connecting line, and has better prospect in the application of radio frequency microwave and millimeter wave.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a de-embedding method of an on-chip test structure of a millimeter wave device.
Background
With the rapid development of silicon-based integrated circuit technology, the characteristic size of a transistor is reduced to below 100 nanometers, the characteristic frequency reaches above 100 gigahertz, and the integrated circuit based on the CMOS technology can be applied to the field of microwave and millimeter wave circuits. In order to improve the design speed of an integrated circuit and accelerate the time of product marketing, when a radio frequency microwave integrated circuit is designed by adopting a CMOS process, an accurate device model is needed to ensure the consistency of circuit simulation and test results, so that an accurate radio frequency microwave device model needs to be provided for circuit design. Such a test structure is generally composed of a PAD, an additional connection line and a device to be tested, the PAD connects a probe with the device to be tested, the additional connection line connects the device to be tested with the PAD, the PAD brings a parasitic capacitance to the test, and the additional connection line brings a parasitic resistance and a parasitic inductance, so that the influence of the PAD and the additional connection line must be removed from S parameters of the test before characterizing the semiconductor device, which is called a de-embedding process.
The common de-embedding method in the prior art is an open-circuit short-circuit de-embedding method, which comprises the following specific steps:
step 1: as shown in fig. 2, a device to be tested is formed on a silicon substrate, and an open-circuit de-embedding structure and a short-circuit de-embedding structure corresponding to the device to be tested are formed on the same silicon substrate as the device to be tested, as shown in fig. 3 and 4; the device to be tested, the open circuit de-embedding structure and the short circuit de-embedding structure all comprise PADs and additional connecting lines;
step 2: performing S parameter test on the device to be tested, the open circuit de-embedding structure and the short circuit de-embedding structure to obtain S parameter S of the device to be testedmeaS parameter S of open circuit de-embedding structureopenAnd S parameter S of short circuit de-embedding structureshort；
And step 3: converting the S parameters of the device to be tested, the open circuit de-embedding structure and the short circuit de-embedding structure into Y parameters to respectively obtain the Y parameters Y of the device to be testedmeaY parameter Y of open circuit de-embedding structureopenAnd Y parameter Y of short circuit de-embedding structureshort(ii) a Calculating Y based on the above Y parametersmea-open＝Ymea-Yopen(ii) a The obtained Ymea-openConverting into corresponding Z parameter to obtain Zmea-open(ii) a Therefore, the parasitic component connected in parallel between the two ports of the device to be tested is removed.
And 4, step 4: calculating Yshort-open＝Yshort-Yopen(ii) a Subjecting the obtained Y toshort-openConverting into corresponding Z parameter to obtain Zshort-openObtaining Z parameter after removing parasitic resistance in parallel between two ports by the short circuit de-embedding structure, and removing Z parametermea-openAnd Zshort-openSubtracting to obtain the accurate Z parameter of the device to be measured: zdevice＝Zmea-open-Zshort-openThus, series parasitics between the two ports of the DUT are removed. And converting the accurate Z parameter of the device to be tested into the S parameter, so as to obtain the accurate S parameter of the device to be tested.
However, in the conventional open-short de-embedding method, the open-circuit de-embedding structure only simply removes the device to be tested, and keeps the PAD and the additional connection lines, and as the application frequency band is higher and higher, the capacitance generated between the additional connection lines due to the open circuit is more and more difficult to be ignored, as shown in fig. 5. So S in the existing open-circuit short-circuit de-embedding algorithmopenIn fact not only the s-parameter of the open-circuit de-embedding structure, but also the additional parasitic capacitance Cj. With the improvement of the application frequency band, if the calculation is continued according to the traditional de-embedding method, the final calculation result is far different from the S parameter of the device to be measured due to the error generated by the family planning capacitor.
Disclosure of Invention
In order to solve the above problems, the technical problem to be solved by the present invention is to provide a method for de-embedding a millimeter wave device on-chip test structure, which can remove the parasitic effect of the on-chip test structure caused between a probe PAD structure and an attached connection line, and has a good prospect in radio frequency microwave millimeter wave application.
In order to achieve the purpose, the invention adopts the following technical scheme: a de-embedding method of a millimeter wave device on-chip test structure comprises the following steps:
s01: forming a device to be tested on a silicon substrate, and simultaneously forming an open-circuit de-embedding structure and a short-circuit de-embedding structure corresponding to the device to be tested on the same substrate; the device to be tested, the open circuit de-embedding structure and the short circuit de-embedding structure all comprise subsidiary connecting lines and on-chip test PADs;
s02: performing S parameter test on the device to be tested, the open circuit de-embedding structure and the short circuit de-embedding structure to obtain S parameter S of the device to be testedmeaS parameter S of open circuit de-embedding structureopenAnd S parameter S of short circuit de-embedding structureshort；
S03: simulating a plate capacitor by using an electromagnetic field simulation model, wherein the plate capacitor is used for simulating the capacitor generated between the auxiliary connecting lines after the device to be tested is removed in the open circuit de-embedding structure; training the environment of the electromagnetic field simulation model by using a passive device which is made of the same material and has the same preparation process as the device to be tested to obtain simulation parameters related to the environment, simulating the flat capacitor by using the calibrated electromagnetic field simulation model containing the simulation parameters to obtain the Y parameter Y of the flat capacitorCjAnd its additional capacitance value Cj;
s04: converting the S parameters obtained in the step S02 into Y parameters to respectively obtain the Y parameters Y of the device to be testedmeaY parameter Y of open circuit de-embedding structureopenAnd Y parameter Y of short circuit de-embedding structureshortAnd calculating the S parameter of the device to be measured, wherein the specific calculation process is as follows:
s041: calculating the Y parameter of the open circuit de-embedding structure after the parasitic capacitance is removed: y'open＝Yopen-YCj；
S042: calculating Y 'based on the Y parameter'mea-open＝Ymea-Y’open；
S043: calculating Y 'based on the Y parameter'short-open＝Yshort-Y’open；
S044: y 'obtained from the above'mea-openAnd Y'short-openConversion to corresponding Z parameter to obtain Z'mea-openAnd Z'short-open，；
S045: by mixing Z'mea-openAnd Z'short-openSubtracting to obtain the accurate Z parameter of the device to be measured: z'device＝Z’mea-open-Z’short-openAnd converting the accurate Z parameter of the device to be tested into the S parameter, so as to obtain the accurate S parameter of the device to be tested.
Further, the specific process of training the environment where the electromagnetic field simulation model is located in step S03 is as follows:
s031: preparing a passive device which has the same material and preparation process as the device to be tested on a silicon substrate, and respectively forming an open circuit structure and a short circuit structure corresponding to the passive device on the same silicon substrate as the device;
s032: s parameter test is carried out on the passive device, the open circuit structure and the short circuit structure to obtain S parameter S of the passive device "meaS parameter S of open circuit structure "openAnd S parameter S of the short-circuit structure "shortObtaining accurate S parameters of the passive device under low frequency according to an open-circuit short-circuit de-embedding method;
s033: and training the environment where the electromagnetic field simulation model is positioned by adopting the size of the passive device and the corresponding accurate S parameter to obtain accurate simulation parameters related to the environment.
Further, the specific step of obtaining the accurate S parameter of the passive device under the low frequency according to the open-circuit short-circuit de-embedding method in step S032 is as follows:
s0321: converting S parameters of the passive device, the open circuit structure and the short circuit structure obtained by the test into Y parameters to respectively obtain Y parameters Y' of the passive device "meaY parameter Y of open circuit structure "openAnd Y parameter Y of the short-circuit structure "short；
S0322: based on the above Y parameters, Y is calculated "mea-open＝Y”mea-Y”open(ii) a Calculating Y "short-open＝Y”short-Y”open；
S0323: y obtained above "mea-openAnd Y "short-openConversion into the corresponding Z parameter to obtain Z "mea-openAnd Z "short-openDisclosure of the inventionGeneral formula Z "mea-openAnd Z "short-openSubtracting to obtain the accurate Z parameter of the passive device: z "device＝Z”mea-open-Z”short-openAnd converting the accurate Z parameter of the passive device into the S parameter, so as to obtain the accurate S parameter of the passive device.
Further, various device sizes of the passive devices are adopted, the steps S031-S032 are respectively repeated, and simulation parameters are verified through the passive devices with different sizes and the corresponding accurate S parameters.
Further, the passive device is a transmission line device or a spiral inductance device.
Further, the simulation parameters related to the environment include the electrical conductivity of the PAD under test, the passive device and the accessory connecting line, the dielectric constant and the loss tangent of the passive device, the dielectric constant and the loss tangent of the medium between the passive device and the substrate, the substrate electrical conductivity, the simulation space range, the simulation boundary conditions, the excitation mode and the like.
Furthermore, a capacitor generated between the additional connecting lines in the open circuit de-embedding structure corresponding to the device to be tested is connected in parallel between the probes at the two ends.
Further, in step S03, the two side plates of the plate capacitor are metal sections of the additional connecting wire.
Further, a finite element simulation method is adopted for the electromagnetic field simulation model.
Further, the short circuit de-embedding structure can be replaced by a via de-embedding structure.
The invention has the beneficial effects that: the invention uses an electromagnetic field simulation model to simulate a plate capacitor, the plate capacitor adopts the material of the subsidiary connecting lines in the device to be tested as two side plates and is used for simulating the capacitance generated between the subsidiary connecting lines after the device to be tested is removed in the open circuit de-embedding structure corresponding to the device to be tested; and (3) acquiring the Y parameter of the capacitor by adopting electromagnetic field simulation, and removing the capacitor connected in parallel from the Y parameter of the open-circuit de-embedding structure, thereby acquiring a de-embedding result with higher precision.
Drawings
FIG. 1 is a flow chart of a de-embedding method of a millimeter wave device on-chip test structure according to the present invention.
FIG. 2 is a device under test including probes and accompanying wiring.
FIG. 3 shows an open de-embedding structure corresponding to the DUT.
FIG. 4 shows a short de-embedding structure corresponding to the DUT.
Fig. 5 shows an additional capacitor in an open de-embedding structure corresponding to a dut.
FIG. 6 is a diagram of a plate capacitor simulated by an electromagnetic field simulation model according to the present invention.
Fig. 7 is a schematic diagram of a lumped circuit corresponding to an open-circuit de-embedding structure in a low frequency state.
FIG. 8 is a schematic diagram of a lumped circuit corresponding to an open de-embedding structure in a high frequency state.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the method for de-embedding a millimeter wave device on-chip test structure provided by the invention comprises the following steps:
s01: forming a device to be tested on a silicon substrate, and simultaneously forming an open-circuit de-embedding structure and a short-circuit de-embedding structure corresponding to the device to be tested on the same substrate; the device to be tested, the open circuit de-embedding structure and the short circuit de-embedding structure all comprise an on-chip test PAD and an attached connecting line. Wherein the device to be tested is a millimeter wave device.
S02: performing S parameter test on the device to be tested, the open circuit de-embedding structure and the short circuit de-embedding structure to obtain S parameter S of the device to be testedmeaS parameter S of open circuit de-embedding structureopenAnd S parameter S of short circuit de-embedding structureshort。
S03: simulating a plate capacitor by using an electromagnetic field simulation model, wherein the plate capacitor is used for simulating the capacitor generated between the attached connecting lines after the device to be tested is removed in the open circuit de-embedding structure; utilizing a passive device with the same material and preparation process as the device to be tested to carry out the operation of the environment where the electromagnetic field simulation model is positionedTraining to obtain simulation parameters related to the plate capacitor, simulating the plate capacitor by using the calibrated simulation model containing the simulation parameters, and obtaining the Y parameter Y of the plate capacitorCjWith its additional capacitance value Cj.
As the application frequency band increases, the S parameter of the open-circuit de-embedding structure in step S02 is not the S parameter of the actual open-circuit de-embedding structure, because parasitic capacitance is formed in the broken portion after the additional connection is broken, as shown in fig. 5. If we want to obtain the S parameter in the open de-embedding structure accurately, we need to remove the influence of the parasitic capacitance. With the application of the electromagnetic field simulation technology in the ultra-high frequency band, as long as the simulation parameter extraction is accurate enough, the simulation precision of the simple capacitor is high enough from DC to the millimeter wave frequency band, a flat capacitor with a metal flat plate as the section of the additional connecting wire is designed, and the electromagnetic field simulation deck of the process platform is used for performing electromagnetic field simulation, so that the Y parameter Y of the capacitor from DC to the millimeter wave frequency band can be obtainedCj。
The two side plates in the plate capacitor designed in the invention are metal sections with subsidiary connecting wires, and the capacitance value of the plate capacitor is equal to the capacitance generated between the subsidiary connecting wires after the device to be tested is removed in the open circuit de-embedding structure corresponding to the device to be tested.
Before simulating a plate capacitor corresponding to a device to be tested by using an electromagnetic field simulation model, training the environment where the electromagnetic field simulation model is located is needed to obtain simulation parameters related to the environment of the simulation model, wherein the training process can adopt a simple passive device with the same process as the device to be tested to train, and the specific steps are as follows:
s031: preparing a passive device which has the same material and preparation process as the device to be tested on a silicon substrate, and respectively forming an open circuit structure and a short circuit structure corresponding to the passive device on the same silicon substrate as the device;
s032: s parameter test is carried out on the passive device, the open circuit structure and the short circuit structure to obtain S parameter S of the passive device "meaS parameter S of open circuit structure "openAnd S parameter S of the short-circuit structure "shortAccording to an open circuitAnd obtaining the accurate S parameter of the passive device under the low frequency by a short circuit de-embedding method.
In the process of calculating the accurate S parameter of the passive device, the passive device is kept in a low-frequency state, and at the moment, parasitic capacitance existing in an open circuit structure in the passive device can be ignored. The process of the accurate S parameter of the specific calculator adopts an open-circuit short-circuit de-embedding method in the prior art to calculate:
s0321: converting S parameters of the passive device, the open circuit structure and the short circuit structure obtained by the test into Y parameters to respectively obtain Y parameters Y' of the passive device "meaY parameter Y of open circuit structure "openAnd Y parameter Y of the short-circuit structure "short；
S0322: based on the above Y parameters, Y is calculated "mea-open＝Y”mea-Y”open(ii) a Calculating Y "short-open＝Y”short-Y”open；
S0323: y obtained above "mea-openAnd Y "short-openConversion into the corresponding Z parameter to obtain Z "mea-openAnd Z "short-openBy reacting Z "mea-openAnd Z "short-openSubtracting to obtain the accurate Z parameter of the passive device: z "device＝Z”mea-open-Z”short-openAnd converting the accurate Z parameter of the passive device into the S parameter, so as to obtain the accurate S parameter of the passive device.
S0323: and training the environment where the electromagnetic field simulation model is located by adopting the size of the passive device and the corresponding accurate S parameter to obtain the simulation parameter related to the environment where the electromagnetic field simulation model is located.
The size of the plate capacitor corresponding to the device to be tested is shown in figure 6, and the sizes of the capacitor plates at two sides of the plate capacitor correspond to the size of the additional connecting line of the device to be tested.
The passive device in the invention can be a transmission line device, the transmission line device can set the length and the width of the transmission line device, and the steps S0321-S0323 are repeated according to different length and width values, so that more accurate simulation parameters can be obtained through the size of the passive device and the corresponding accurate S parameters. The specific simulation parameters comprise PAD in a chip test, the conductivity of the passive device and an accessory connecting line, the dielectric constant and the loss tangent of the passive device and the substrate, the substrate conductivity, the simulation space range, the simulation boundary condition, the excitation mode and the like.
After accurate simulation parameters are obtained, the size of the plate capacitor corresponding to the device to be tested is introduced into an electromagnetic field simulation model containing the simulation parameters, so that the Cj of the additional capacitor of the plate capacitor can be obtained and converted into Y parameters YCjThat is, the additional capacitance generated in the open circuit de-embedding structure corresponding to the device under test in the present invention. The electromagnetic field simulation model can adopt a finite element simulation method and the like.
S04: converting the S parameters obtained by the test into Y parameters to respectively obtain the Y parameters Y of the device to be testedmeaY parameter Y of open circuit de-embedding structureopenAnd Y parameter Y of short circuit de-embedding structureshortThe following calculation is performed:
s041: calculating the Y parameter of the open circuit de-embedding structure after the parasitic capacitance is removed: y'open＝Yopen-YCj(ii) a This removes the parasitic capacitance in the open de-embedding structure.
S042: calculating Y 'based on the Y parameter'mea-open＝Ymea-Y’open(ii) a And the parasitic resistance connected in parallel between the two ports of the device to be tested is removed.
S043: calculating Y 'based on the Y parameter'short-open＝Yshort-Y’open；
S044: y 'obtained from the above'mea-openAnd Y'short-openConversion to corresponding Z parameter to obtain Z'mea-openAnd Z'short-open，；
S045: by mixing Z'mea-openAnd Z'short-openSubtracting to obtain the accurate Z parameter of the device to be measured: z'device＝Z’mea-open-Z’short-openAnd converting the accurate Z parameter of the device to be tested into the S parameter, so as to obtain the accurate S parameter of the device to be tested.
It is worth to be noted that the de-embedding method in the invention is particularly suitable for the de-embedding method of the device to be tested in the ultrahigh frequency state. Because, in the normal state or low frequency state, the additional capacitance due to the short circuit in the open-circuit de-embedding structure is negligible, as shown in fig. 7. However, in the ultra-high frequency regime, this additional capacitance is significant, and in order to obtain accurate de-embedding results, the de-embedding process must be performed using the lumped circuit schematic shown in fig. 8.
The invention uses an electromagnetic field simulation model to simulate a plate capacitor, the plate capacitor adopts the material of the subsidiary connecting lines in the device to be tested as two side plates and is used for simulating the capacitance generated between the subsidiary connecting lines after the device to be tested is removed in the open circuit de-embedding structure corresponding to the device to be tested; and (3) acquiring the Y parameter of the capacitor by adopting electromagnetic field simulation, and removing the capacitor connected in parallel from the Y parameter of the open-circuit de-embedding structure, thereby acquiring a de-embedding result with higher precision.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (10)
1. A de-embedding method of a millimeter wave device on-chip test structure is characterized by comprising the following steps:
s01: forming a device to be tested on a silicon substrate, and simultaneously forming an open-circuit de-embedding structure and a short-circuit de-embedding structure corresponding to the device to be tested on the same substrate; the device to be tested, the open circuit de-embedding structure and the short circuit de-embedding structure all comprise subsidiary connecting lines and on-chip test PADs;
s02: performing S parameter test on the device to be tested, the open circuit de-embedding structure and the short circuit de-embedding structure to obtain S parameter S of the device to be testedmeaS parameter S of open circuit de-embedding structureopenAnd S parameter S of short circuit de-embedding structureshort；
S03: simulating a plate capacitor using an electromagnetic field simulation modelThe circuit is used for simulating the capacitance generated between the additional connecting lines in the open circuit de-embedding structure; training the environment of the electromagnetic field simulation model by using a passive device which is made of the same material and has the same preparation process as the device to be tested to obtain simulation parameters related to the environment, simulating the flat capacitor by using the calibrated electromagnetic field simulation model containing the simulation parameters to obtain the Y parameter Y of the flat capacitorCjAnd its additional capacitance value Cj;
s04: converting the S parameters obtained in the step S02 into Y parameters to respectively obtain the Y parameters Y of the device to be testedmeaY parameter Y of open circuit de-embedding structureopenAnd Y parameter Y of short circuit de-embedding structureshortAnd calculating the S parameter of the device to be measured, wherein the specific calculation process is as follows:
s041: calculating the Y parameter of the open circuit de-embedding structure after the parasitic capacitance is removed: y'open＝Yopen-YCj；
S042: calculating Y 'based on the Y parameter'mea-open＝Ymea-Y’open；
S043: calculating Y 'based on the Y parameter'short-open＝Yshort-Y’open；
S044: y 'obtained from the above'mea-openAnd Y'short-openConversion to corresponding Z parameter to obtain Z'mea-openAnd Z'short-open；
S045: by mixing Z'mea-openAnd Z'short-openSubtracting to obtain the accurate Z parameter of the device to be measured: z'device＝Z’mea-open-Z’short-openAnd converting the accurate Z parameter of the device to be tested back to the S parameter to obtain the accurate S parameter of the device to be tested.
2. The method for de-embedding the millimeter wave device on-chip test structure according to claim 1, wherein the step S03 of training the environment where the electromagnetic field simulation model is located comprises:
s031: preparing a passive device which has the same material and preparation process as the device to be tested on a silicon substrate, and respectively forming an open circuit structure and a short circuit structure corresponding to the passive device on the same silicon substrate as the device;
s032: s parameter test is carried out on the passive device, the open circuit structure and the short circuit structure to obtain S parameter S of the passive device "meaS parameter S of open circuit structure "openAnd S parameter S of the short-circuit structure "shortObtaining accurate S parameters of the passive device under low frequency according to an open-circuit short-circuit de-embedding method;
s033: and training the environment where the electromagnetic field simulation model is positioned by adopting the size of the passive device and the corresponding accurate S parameter to obtain accurate simulation parameters related to the environment.
3. The de-embedding method of the millimeter wave device on-chip test structure as claimed in claim 2, wherein the specific step of obtaining the accurate S parameter of the passive device under low frequency according to the open-short de-embedding method in step S032 is as follows:
s0321: converting S parameters of the passive device, the open circuit structure and the short circuit structure obtained by the test into Y parameters to respectively obtain Y parameters Y' of the passive device "meaY parameter Y of open circuit structure "openAnd Y parameter Y of the short-circuit structure "short；
S0322: based on the above Y parameters, Y is calculated "mea-open＝Y”mea-Y”open(ii) a Calculating Y "short-open＝Y”short-Y”open；
S0323: y obtained above "mea-openAnd Y "short-openConversion into the corresponding Z parameter to obtain Z "mea-openAnd Z "short-openBy reacting Z "mea-openAnd Z "short-openSubtracting to obtain the accurate Z parameter of the passive device: z "device＝Z”mea-open-Z”short-openAnd converting the accurate Z parameter of the passive device into the S parameter to obtain the accurate S parameter of the passive device.
4. The de-embedding method of the millimeter wave device on-chip test structure according to claim 2, wherein the simulation parameters are verified by using a plurality of passive devices of different sizes and corresponding accurate S parameters by repeating steps S031-S032 with a plurality of device sizes of the passive devices.
5. The de-embedding method of the millimeter wave device on-chip test structure as claimed in claim 2, wherein the passive device is a transmission line device or a spiral inductor device.
6. The method as claimed in claim 2, wherein the simulation parameters related to the environment include conductivity of the PAD, passive device and accessory connection line, dielectric constant and loss tangent of the passive device, dielectric medium between the passive device and the substrate, substrate conductivity, simulation space range, simulation boundary conditions and excitation mode.
7. The method as claimed in claim 1, wherein the capacitance generated between the additional connection lines in the open de-embedding structure corresponding to the device under test is connected in parallel between the probes at the two ends.
8. The method as claimed in claim 1, wherein the two side plates of the plate capacitor in step S03 are metal sections of the additional connecting wires.
9. The de-embedding method of the millimeter wave device on-chip test structure as claimed in claim 1, wherein a finite element simulation method is applied to the electromagnetic field simulation model.
10. The method of claim 1-9, wherein the short de-embedding structure is a via de-embedding structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810391173.9A CN108664717B (en) | 2018-04-27 | 2018-04-27 | De-embedding method of millimeter wave device on-chip test structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810391173.9A CN108664717B (en) | 2018-04-27 | 2018-04-27 | De-embedding method of millimeter wave device on-chip test structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108664717A CN108664717A (en) | 2018-10-16 |
| CN108664717B true CN108664717B (en) | 2021-11-02 |
Family
ID=63780239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810391173.9A Active CN108664717B (en) | 2018-04-27 | 2018-04-27 | De-embedding method of millimeter wave device on-chip test structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108664717B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444717B (en) | 2018-11-27 | 2020-08-18 | 中国电子科技集团公司第十三研究所 | Novel on-chip S parameter error calibration method and device |
| CN110034780B (en) * | 2019-03-26 | 2021-09-24 | 湖南赛博诺格电子科技有限公司 | Method and system for constructing N-port microwave passive network and readable storage medium |
| CN111142057B (en) * | 2019-12-17 | 2020-11-24 | 中国电子科技集团公司第十三研究所 | Terahertz frequency band on-chip S parameter calibration method and terminal equipment |
| US11385175B2 (en) | 2019-12-17 | 2022-07-12 | The 13Th Research Institute Of China Electronics Technology Group Corporation | Calibration method and terminal equipment of terahertz frequency band on-wafer S parameter |
| CN112098794B (en) * | 2020-08-14 | 2023-02-28 | 中国电子科技集团公司第十三研究所 | Method for determining parameters in piece calibration piece model and terminal equipment |
| CN111929558B (en) * | 2020-09-28 | 2021-01-15 | 浙江铖昌科技股份有限公司 | Self-calibration-based de-embedding method, system, storage medium and terminal |
| CN112131817B (en) * | 2020-09-28 | 2023-10-31 | 北京国联万众半导体科技有限公司 | Millimeter wave monolithic integrated design method |
| CN113655360A (en) * | 2021-08-10 | 2021-11-16 | 中国科学院上海微系统与信息技术研究所 | De-embedding method of on-chip test structure of RF MOS device |
| CN116449183B (en) * | 2023-04-24 | 2024-04-05 | 上海新微半导体有限公司 | De-embedding structure and method for on-chip test of radio frequency chip, storage medium and terminal |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194798A (en) * | 2010-03-11 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Short-circuit deembedding test structure for micro-capacitance MOS (Metal Oxide Semiconductor) varactor and variode |
| CN105022878A (en) * | 2015-07-21 | 2015-11-04 | 中国科学院上海高等研究院 | Radio frequency SOI-MOS varactor substrate model and parameter extracting method thereof |
| CN105891628A (en) * | 2016-03-30 | 2016-08-24 | 清华大学 | Universal four-port on-wafer high-frequency de-embedding method |
| CN106021670A (en) * | 2016-05-12 | 2016-10-12 | 成都海威华芯科技有限公司 | Modeling method of millimeter waves FET |
| TW201730792A (en) * | 2016-02-22 | 2017-09-01 | 國立交通大學 | A high precision semiconductor device parameters extraction method |
| CN107818187A (en) * | 2016-09-14 | 2018-03-20 | 中航（重庆）微电子有限公司 | A kind of multiple-grid refers to AlGaN/GaN HETM small-signal models and its puies forward ginseng method |
-
2018
- 2018-04-27 CN CN201810391173.9A patent/CN108664717B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194798A (en) * | 2010-03-11 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Short-circuit deembedding test structure for micro-capacitance MOS (Metal Oxide Semiconductor) varactor and variode |
| CN105022878A (en) * | 2015-07-21 | 2015-11-04 | 中国科学院上海高等研究院 | Radio frequency SOI-MOS varactor substrate model and parameter extracting method thereof |
| TW201730792A (en) * | 2016-02-22 | 2017-09-01 | 國立交通大學 | A high precision semiconductor device parameters extraction method |
| CN105891628A (en) * | 2016-03-30 | 2016-08-24 | 清华大学 | Universal four-port on-wafer high-frequency de-embedding method |
| CN106021670A (en) * | 2016-05-12 | 2016-10-12 | 成都海威华芯科技有限公司 | Modeling method of millimeter waves FET |
| CN107818187A (en) * | 2016-09-14 | 2018-03-20 | 中航（重庆）微电子有限公司 | A kind of multiple-grid refers to AlGaN/GaN HETM small-signal models and its puies forward ginseng method |
Non-Patent Citations (3)
| Title |
|---|
| "毫米波GaN基HEMT小信号建模和参数提取";尹成功;《中国优秀硕士学位论文全文数据库 信息科技辑》;20160315;I135-721 * |
| "毫米波共面波导建模技术研究";傅飞;《中国优秀硕士学位论文全文数据库 信息科技辑》;20160415;I136-4 * |
| Qing-Hong Bu 等."Evaluation of a Multi-line De-embedding Technique for Millimeter-Wave CMOS Circuit Desig ".《Proceedings of Asia-Pacific Microwave Conference 2010》.2012, * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108664717A (en) | 2018-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108664717B (en) | De-embedding method of millimeter wave device on-chip test structure | |
| Mangan et al. | De-embedding transmission line measurements for accurate modeling of IC designs | |
| Ito et al. | A simple through-only de-embedding method for on-wafer S-parameter measurements up to 110 GHz | |
| US7954080B2 (en) | Method and apparatus for de-embedding on-wafer devices | |
| CN107167724B (en) | A kind of small measuring signal goes embedding method | |
| CN100552460C (en) | Can remove inductance measurement method on the radio frequency tablet of ghost effect on the test structure | |
| CN103617326A (en) | Impedance simulation method for chip capacitor in power-supply distribution network | |
| CN111679171B (en) | Circuit topological structure based on interconnection line unit and de-embedding method for interconnection line unit cascade | |
| Yen et al. | TSV RF de-embedding method and modeling for 3DIC | |
| US10520543B2 (en) | Test structure and method for judging de-embedding accuracy of RF devices by using an introduced device | |
| CN113655360A (en) | De-embedding method of on-chip test structure of RF MOS device | |
| Luo et al. | A distributed de-embedding solution for CMOS mm-wave on-wafer measurements based-on double open-short technique | |
| Lu et al. | Scalable modeling and wideband measurement techniques for a signal TSV surrounded by multiple ground TSVs for RF/high-speed applications | |
| McGibney et al. | An overview of electrical characterization techniques and theory for IC packages and interconnects | |
| Yen et al. | A physical de-embedding method for silicon-based device applications | |
| CN112098795A (en) | Two-port on-chip calibration piece model and parameter determination method | |
| CN112098792A (en) | Two-port on-wafer calibration piece model and parameter determination method | |
| CN104635135A (en) | De-embedding method of compound semiconductor device | |
| Berbel et al. | Characterization and modeling of the conducted emission of integrated circuits up to 3 GHz | |
| Chang et al. | Investigation on realizing 1 Ω current probe complied with IEC 61967-4 direct coupling method | |
| Abdo et al. | Comparison between L-2L and thru-reflect-line de-embedding methods for W-band CMOS amplifier design | |
| US9147020B2 (en) | Transmission line characterization using EM calibration | |
| Hong et al. | Extracting High Speed Refresh Current for DDR5 Module based on Network Parameter Theory | |
| CN112711927B (en) | De-embedding method based on resistor unit cascading | |
| Haiyan et al. | 220GHz on-wafer measurement based on TRL calibration method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |