CN107887327A - 在垂直晶体管替代栅极流程中控制自对准栅极长度 - Google Patents
在垂直晶体管替代栅极流程中控制自对准栅极长度 Download PDFInfo
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Abstract
本发明涉及在垂直晶体管替代栅极流程中控制自对准栅极长度,其中,一种半导体结构包括半导体衬底,位于半导体衬底上方的第一垂直晶体管的底部源/漏层,位于该源/漏层上方的垂直沟道,以及包覆该垂直沟道的金属栅极,该垂直沟道在与该金属栅极之间的接口处相对金属栅极具有固定高度。半导体结构还包括位于该垂直沟道上方的顶部源/漏层,以及至各顶部及底部源/漏层及该栅极的自对准接触。半导体结构可通过以下步骤实现:提供上方具有底部源/漏层的半导体衬底,在底部源/漏层上方形成垂直沟道,形成包覆垂直沟道的伪栅极,以及分别围绕垂直沟道的顶部及底部形成底部间隙壁层及顶部间隙壁层,垂直沟道的剩余中心部分定义固定垂直沟道高度。
Description
技术领域
本发明通常涉及垂直晶体管的制造。尤其,本发明涉及通过替代栅极制程控制垂直晶体管中的自对准栅极长度。
背景技术
当前,垂直FET(vertical FET;VFET)的制造在控制自对准栅极宽度并将该VFET集成入替代金属栅极(replacement metal gate;RMG)流程方面具有挑战性。
发明内容
因此,需要克服上述挑战。
为克服现有技术的缺点并提供额外的优点,在一个态样中提供一种在垂直晶体管替代栅极制程中控制自对准栅极长度的方法。该方法包括:提供上方具有底部源/漏层的半导体衬底,在该底部源/漏层上方形成垂直沟道,形成包覆该垂直沟道的伪栅极,以及分别围绕该垂直沟道的顶部及底部形成底部间隙壁层及顶部间隙壁层,该垂直沟道的剩余中心部分定义固定垂直沟道高度。该方法还包括在该垂直沟道上方形成顶部源/漏层,用金属栅极替代该伪栅极,以及形成自对准源、漏及栅极接触。
依据另一个态样,提供一种半导体结构。该半导体结构包括:半导体衬底,位于该半导体衬底上方的第一垂直晶体管的底部源/漏层,位于该源/漏层上方的垂直沟道,以及包覆该垂直沟道的金属栅极,该垂直沟道在与该金属栅极之间的接口(interface)处相对该金属栅极具有固定高度。该半导体结构还包括位于该垂直沟道上方的顶部源/漏层,以及至各该顶部及底部源/漏层及该栅极的自对准接触。
从下面结合附图所作的本发明的各种态样的详细说明将很容易了解本发明的这些及其它目的、特征及优点。
附图说明
图1显示依据本发明的一个或多个态样的初始半导体结构的一个例子的剖视图,该初始半导体结构包括半导体衬底,位于该半导体衬底上方的掺杂源/漏半导体材料层,位于该掺杂源/漏半导体材料层的任意一侧上并部分延伸进入该半导体衬底中的隔离材料层,以及位于该掺杂源/漏半导体材料上方的至少一个鳍片,该鳍片包括由半导体沟道材料构成的底部以及由牺牲外延材料构成的顶部。
图2显示依据本发明的一个或多个态样,(例如,利用气体团簇离子束制程)在该初始半导体结构的水平表面上形成垂直晶体管的底部间隙壁层及顶部间隙壁层以后,图1的结构的一个例子。
图3显示依据本发明的一个或多个态样,在该第一硬掩膜层及该至少一个鳍片的侧面上方形成共形介电层并邻近该共形介电层的垂直部分形成伪栅极,接着平坦化(例如CMP)以向下抛光该伪栅极材料至该共形介电层以后,图2的结构的一个例子。
图4显示依据本发明的一个或多个态样,在移除该伪栅极的顶部以后,图3的结构的一个例子。
图5显示依据本发明的一个或多个态样,在该伪栅极上方形成硬掩膜层并平坦化以后,图4的结构的一个例子。
图6显示依据本发明的一个或多个态样,在光刻图案化以移除该伪栅极的不想要的部分及该硬掩膜层的相应部分以后,图5的结构的一个例子。
图7显示依据本发明的一个或多个态样,在移除该鳍片的该顶部以暴露该鳍片的该底部以后,图6的结构的一个例子。
图8显示依据本发明的一个或多个态样,在移除该共形介电层的暴露部分以部分暴露该鳍片的剩余部分以后,图7的结构的一个例子。
图9显示依据本发明的一个或多个态样,邻近剩余伪栅极层的内外侧形成间隙壁层以后,图8的结构的一个例子。
图10显示依据本发明的一个或多个态样,在该暴露的至少一个鳍片的该部分暴露部分上方形成第二掺杂源/漏半导体材料层以后,图9的结构的一个例子。
图11显示依据本发明的一个或多个态样,用介电材料填充该结构的开口部分以后,图10的结构的一个例子。
图12显示依据本发明的一个或多个态样,在凹入除用于该填充的该介电材料以外的所有材料以后,图11的结构的一个例子。
图13显示依据本发明的一个或多个态样,在移除该伪栅极(例如,a-Si)及该栅极介电质(图3,114)的剩余部分以后,图12的结构的一个例子。
图14显示依据本发明的一个或多个态样,在形成替代金属栅极以后,图13的结构的一个例子。
图15显示依据本发明的一个或多个态样,在凹入该金属栅极以后,图14的结构的一个例子。
图16显示依据本发明的一个或多个态样,在用介电材料填充因凹入该金属栅极而形成的开口区域以后,图15的结构的一个例子。
图17显示依据本发明的一个或多个态样,在形成至该金属栅极、该源极及该漏极的接触以后,图16的结构的一个例子。
具体实施方式
下面通过参照附图中所示的非限制性例子来更加充分地解释本发明的态样及其特定的特征、优点以及细节。省略对已知材料、制造工具、制程技术等的说明,以免在细节上不必要地模糊本发明。不过,应当理解,当说明本发明的态样时,详细的说明及具体的例子仅作为示例,而非限制。本领域的技术人员将会从本揭露中了解在基础的发明概念的精神及/或范围内的各种替代、修改、添加和/或布局。
这里在说明书及权利要求书中所使用的近似语言可用以修饰任意量化表达,可允许该量化表达变动而不会导致与其相关的基本功能的改变。因此,由一个或多个术语例如“约”修饰的值不限于所指定的精确值。在一些情况下,该近似语言可对应用以测量该值的仪器的精度。
这里所使用的术语仅是出于说明特定例子的目的,并非意图限制本发明。除非上下文中明确指出,否则这里所使用的单数形式“一个”以及“该”也意图包括复数形式。还应当理解,术语“包括”(以及任意形式的包括)、“具有”(以及任意形式的具有)以及“包含”(以及任意形式的包含)都是开放式连接动词。因此,“包括”、“具有”或“包含”一个或多个步骤或元件的方法或装置具有那些一个或多个步骤或元件,但并不限于仅仅具有那些一个或多个步骤或元件。类似地,“包括”、“具有”或“包含”一个或多个特征的一种方法的步骤或一种装置的元件具有那些一个或多个特征,但并不限于仅仅具有那些一个或多个特征。而且,以特定方式配置的装置或结构至少以那种方式配置,但也可以未列出的方式配置。
当这里所使用的术语“连接”用以指两个物理元件时,是指该两个物理元件之间的直接连接。不过,术语“耦接”可指直接连接或者通过一个或多个中间元件的连接。
这里所使用的术语“可”以及“可能是”表示在一系列条件下发生的可能性;具有特定的属性、特性或功能;以及/或者修饰另一个动词,通过表达与该修饰动词相关联的一种或多种能力、功能或可能性的方式进行修饰。因此,考虑到在某些情况下,被修饰的术语可能有时不适当、不能够或不合适,“可”以及“可能是”的使用表示被修饰的术语明显是适当的、有能力的或适合所示性能、功能或用途。例如,在一些情况下,事件或性能可以预期,而在其它情况下,该事件或性能无法发生-这个区别由术语“可”以及“可能是”体现。
除非另外指出,否则这里所使用的术语“约”与一个值例如测量结果、尺寸等一起使用时,是指加或减该值的百分之五的可能变动。
下面参照附图,为有利于理解,该些附图并非按比例绘制,其中,不同附图中所使用的相同附图标记表示相同或类似的组件。
图1显示依据本发明的一个或多个态样的初始半导体结构100的一个例子的剖视图,该初始半导体结构包括半导体衬底102,位于该半导体衬底上方的掺杂源/漏半导体材料层104,在该掺杂源/漏半导体材料层的任意一侧上并部分延伸进入该半导体衬底中的隔离材料层110,以及位于该掺杂源/漏半导体材料上方的一个或多个鳍片105,该一个或多个鳍片105包括由半导体沟道材料构成的底部106以及由牺牲外延材料构成的顶部108。
该初始结构可例如通过使用已知的制程及技术以传统方式制造。另外,除非另外指出,否则,传统的制程及技术可用以实现本发明的制程的单独步骤。不过,尽管为简单起见仅显示部分,但应当理解,实际上,在同一块体衬底上通常包括许多此类结构。
在一个例子中,衬底102可包括任意含硅衬底,包括但不限于硅(Si)、单晶硅、多晶硅、非晶硅、空洞层上硅(silicon-on-nothing;SON)、绝缘体上硅(silicon-on-insulator;SOI),或替代绝缘体上硅(silicon-on-replacement insulator;SRI),或硅锗衬底,以及类似物。衬底102可附加地或替代地包括各种隔离、掺杂及/或装置特征。该衬底可包括其它合适的元素半导体例如晶体锗(Ge),复合半导体例如碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs),和/或锑化铟(InSb),或其组合;合金半导体,包括GaAsP、AlInAs、GaInAs、GaInP,或GaInAsP,或其组合。
图2显示依据本发明的一个或多个态样,(例如,利用气体团簇离子束(gascluster ion beam;GCIB)制程)在该初始半导体结构的水平表面上形成底部间隙壁层112及顶部间隙壁层113(用于垂直晶体管的间隙壁)以后,图1的结构的一个例子。由于该间隙壁层通过定向沉积制程形成,因此其仅形成于该鳍片的底部表面及顶部表面。定向沉积的例子包括:(1)SiN的GCIB沉积;或(2)SiO2或SiN的HDP沉积。(HDP:高密度等离子体化学气相沉积(high-density plasma CVD),其通常包括多个沉积-蚀刻循环并最终在底部形成介电材料,而不会在侧壁形成任意介电材料)。
图3显示依据本发明的一个或多个态样,在底部间隙壁层112及该至少一个鳍片的侧面上方形成共形介电层114并邻近该共形介电层的垂直部分形成伪栅极116,接着平坦化(例如CMP(化学机械抛光))以向下抛光伪栅极材料116至该共形介电层以后,图2的结构的一个例子。材料的例子包括:114:SiO2、116:a-Si。
图4显示依据本发明的一个或多个态样,在移除该伪栅极的顶部118以后,图3的结构的一个例子。
图5显示依据本发明的一个或多个态样,在伪栅极116上方形成硬掩膜层120并平坦化(移除顶部间隙壁层113)以后,图4的结构的一个例子。该硬掩膜层可例如通过沉积介电薄膜并接着执行CMP制程来形成。该介电膜的一个例子包括氮化硅(Si3N4)。
图6显示依据本发明的一个或多个态样,在光刻图案化以移除该伪栅极的不想要的部分及该硬掩膜层的相应部分(通常,该结构的部分122)以后,图5的结构的一个例子。
图7显示依据本发明的一个或多个态样,在移除鳍片105的顶部108以暴露该鳍片的该底部以后,图6的结构的一个例子。较佳地,鳍片105的顶部108的该移除对该鳍片的底部106的材料具有选择性。在一个例子中,牺牲顶部108包括外延硅锗且底部106包括硅。因此,相对硅及其它围绕材料例如SiN、a-Si(非晶硅)及SiO2可选择性移除e-SiGe(外延-SiGe)。
图8显示依据本发明的一个或多个态样,在移除该共形介电层(图3,114)的暴露部分120以部分暴露该至少一个鳍片的剩余部分122以后,图7的结构的一个例子。
图9显示依据本发明的一个或多个态样,邻近该剩余伪栅极层130的外侧126及内侧128形成间隙壁层124以后,图8的结构的一个例子。
图10显示依据本发明的一个或多个态样,在该暴露的至少一个鳍片的该部分暴露部分122上方形成第二掺杂源/漏半导体材料层132以后,图9的结构的一个例子。
图11显示依据本发明的一个或多个态样,用介电材料134(例如SiO2)填充该结构的开口部分以后,图10的结构的一个例子。
图12显示依据本发明的一个或多个态样,在凹入136除用于所述填充的介电材料134以外的所有材料以后,图11的结构的一个例子。在一个例子中,该凹入可通过相对氧化物具有选择性的氮化物移除来实现。
图13显示依据本发明的一个或多个态样,在移除该伪栅极(例如,a-Si)及该栅极介电质(图3,114)的剩余部分137以后,图12的结构的一个例子。
图14显示依据本发明的一个或多个态样,在形成替代金属栅极140以后,图13的结构的一个例子。替代栅极通常包括栅极介电质(例如,SiO2、SiON、HfO2、HfLaO2等)及导电材料(例如,功函数金属,如钨、铝、铜、钌等)。功函数金属的例子包括TiN、TiC、TiAl、TaN、TaC等。
图15显示依据本发明的一个或多个态样,在凹入142该金属栅极以后,图14的结构的一个例子。应当注意,通过用该初始底部鳍片部分高度预定义该栅极长度,该实际栅极长度将不受如图15中所示的不均匀替代栅极凹槽的影响。
图16显示依据本发明的一个或多个态样,在用介电材料144填充因凹入142该金属栅极而形成的开口区域(图15,141)以后,图15的结构的一个例子。
图17显示依据本发明的一个或多个态样,在形成至金属栅极146、源极(148或150)及漏极(150、148)以后,图16的结构的一个例子。
在第一态样中,上面揭露一种方法。该方法包括:提供上方具有底部源/漏层的半导体衬底,在该底部源/漏层上方形成垂直沟道,形成包覆该垂直沟道的伪栅极,以及分别围绕该垂直沟道的顶部及底部形成底部间隙壁层及顶部间隙壁层,该垂直沟道的剩余中心部分定义固定垂直沟道高度。该方法还包括在该垂直沟道上方形成顶部源/漏层,用金属栅极替代该伪栅极,以及形成自对准源、漏及栅极接触。
在一个例子中,形成该伪栅极可包括例如在该初始半导体结构的水平表面上形成第一硬掩膜层,在该第一硬掩膜层上方并沿着该一个或多个鳍片的垂直侧面形成共形介电层,以及邻近该共形介电层的垂直部分形成伪栅极。在一个例子中,形成该第一硬掩膜层可包括例如使用气体团簇离子束制程。在一个例子中,形成该第一硬掩膜层可包括例如形成该第一硬掩膜层至约5纳米至约15纳米的高度。
在一个例子中,在该第一态样的该方法中形成该垂直沟道可包括例如在该底部源/漏层上方形成鳍片,该鳍片包括由半导体沟道材料构成的底部以及由牺牲外延半导体材料构成的顶部。在一个例子中,形成该伪栅极可包括例如用第二硬掩膜层替代该伪栅极的顶部;移除该伪栅极的部分,该第二硬掩膜层的相应部分以及该一个或多个鳍片的该顶部,以暴露该共形介电层的部分以及该一个或多个鳍片的该底部;移除该共形介电层的该暴露部分,以部分暴露该一个或多个鳍片的该底部的侧面;以及邻近剩余伪栅极层的内外侧形成垂直硬掩膜层。在一个例子中,移除该伪栅极的部分可包括例如移除该伪栅极的不均匀部分。
在一个例子中,移除该一个或多个鳍片的该顶部可包括例如相对该一个或多个鳍片的该底部具有选择性的自该鳍片的移除。
在一个例子中,在该垂直沟道上方形成顶部源/漏层可包括例如在该部分暴露的一个或多个鳍片上方形成第二掺杂源/漏半导体材料层并用介电材料填充该结构的开口部分,以及凹入除用于该填充的该介电材料以外的所有材料。
在一个例子中,该方法还可包括例如用介电材料填充因凹入金属栅极堆叠而形成的该金属栅极堆叠的开口区域。
在第二态样中,上面揭露一种半导体结构。该半导体结构包括:半导体衬底,位于该半导体衬底上方的第一垂直晶体管的底部源/漏层,位于该源/漏层上方的垂直沟道,以及包覆该垂直沟道的金属栅极,该垂直沟道在与该金属栅极之间的接口处相对该金属栅极具有固定高度。该半导体结构还包括位于该垂直沟道上方的顶部源/漏层,以及至各该顶部及底部源/漏层及该栅极的自对准接触。
在一个例子中,该金属栅极可例如在该垂直沟道内的该接口以外不具有高度均匀性。
在一个例子中,该第二态样的该半导体衬底还可包括例如围绕该金属栅极的硬掩膜材料。
在一个例子中,该第二态样的该半导体衬底还可包括例如第二垂直晶体管,其具有与该第一垂直晶体管的固定高度垂直沟道不同的固定高度垂直沟道。在一个例子中,该第二垂直晶体管的金属栅极可具有例如均匀的高度。
尽管本文已说明并显示本发明的数个态样,但本领域的技术人员可实施替代态样来达到相同的目的。因此,所附权利要求意图涵盖落入本发明的真实精神及范围内的所有此类替代态样。
Claims (15)
1.一种方法,包括:
提供半导体衬底,其上方具有底部源/漏层;
在该底部源/漏层上方形成垂直沟道;
形成包覆该垂直沟道的伪栅极;
分别围绕该垂直沟道的顶部及底部形成底部间隙壁层及顶部间隙壁层,该垂直沟道的剩余中心部分定义固定垂直沟道高度;
在该垂直沟道上方形成顶部源/漏层;
用金属栅极替代该伪栅极;以及
形成自对准源、漏及栅极接触。
2.如权利要求1所述的方法,其中,形成该伪栅极包括:
在初始半导体结构的水平表面上形成第一硬掩膜层;
在该第一硬掩膜层上方并沿着至少一个鳍片的垂直侧面形成共形介电层;以及
邻近该共形介电层的垂直部分形成伪栅极。
3.如权利要求2所述的方法,其中,形成该第一硬掩膜层包括使用气体团簇离子束制程。
4.如权利要求3所述的方法,其中,形成该第一硬掩膜层包括形成该第一硬掩膜层至约5纳米至约15纳米的高度。
5.如权利要求1所述的方法,其中,形成该垂直沟道包括在该底部源/漏层上方形成鳍片,该鳍片包括半导体沟道材料的底部以及牺牲外延半导体材料的顶部。
6.如权利要求5所述的方法,其中,形成该伪栅极包括:
用第二硬掩膜层替代该伪栅极的顶部;
移除该伪栅极的部分,该第二硬掩膜层的相应部分以及至少一个鳍片的该顶部,以暴露共形介电层的部分以及该至少一个鳍片的该底部;
移除该共形介电层的该暴露部分,以部分暴露该至少一个鳍片的该底部的侧面;以及
邻近剩余伪栅极层的内外侧形成垂直硬掩膜层。
7.如权利要求6所述的方法,其中,移除该伪栅极的部分包括移除该伪栅极的不均匀部分。
8.如权利要求6所述的方法,其中,移除该至少一个鳍片的该顶部包括相对该至少一个鳍片的该底部具有选择性的自该鳍片的移除。
9.如权利要求6所述的方法,其中,在该垂直沟道上方形成顶部源/漏层包括:
在该部分暴露的至少一个鳍片上方形成第二掺杂源/漏半导体材料层并用介电材料填充结构的开口部分;以及
凹入除用于该填充的该介电材料以外的所有材料。
10.如权利要求9所述的方法,还包括用介电材料填充因凹入金属栅极堆叠而形成的该金属栅极堆叠的开口区域。
11.一种半导体结构,包括:
半导体衬底;
第一垂直晶体管的底部源/漏层,位于该半导体衬底上方;
垂直沟道,位于该源/漏层上方;
金属栅极,包覆该垂直沟道,该垂直沟道在与该金属栅极之间的接口处相对该金属栅极具有固定高度;
顶部源/漏层,位于该垂直沟道上方;以及
至各该顶部及底部源/漏层及该栅极的自对准接触。
12.如权利要求11所述的半导体衬底,其中,该金属栅极在该垂直沟道内的该接口以外不具有高度均匀性。
13.如权利要求11所述的半导体衬底,还包括围绕该金属栅极的硬掩膜材料。
14.如权利要求11所述的半导体衬底,还包括第二垂直晶体管,其具有与该第一垂直晶体管的固定高度垂直沟道不同的固定高度垂直沟道。
15.如权利要求14所述的半导体衬底,其中,该第二垂直晶体管的金属栅极具有均匀高度。
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US11152507B2 (en) | 2018-11-07 | 2021-10-19 | International Business Machines Corporation | Vertical field-effect transistor with a bottom contact that exhibits low electrical resistance |
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US20180090598A1 (en) | 2018-03-29 |
CN107887327B (zh) | 2021-11-05 |
US10199480B2 (en) | 2019-02-05 |
TWI647815B (zh) | 2019-01-11 |
TW201814884A (zh) | 2018-04-16 |
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