CN107885678A - Hard disk controlling interface arrangement - Google Patents
Hard disk controlling interface arrangement Download PDFInfo
- Publication number
- CN107885678A CN107885678A CN201711187816.XA CN201711187816A CN107885678A CN 107885678 A CN107885678 A CN 107885678A CN 201711187816 A CN201711187816 A CN 201711187816A CN 107885678 A CN107885678 A CN 107885678A
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- Prior art keywords
- signal
- universal input
- hard disk
- interface arrangement
- serial universal
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4054—Coupling between buses using bus bridges where the bridge performs a synchronising function where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
The invention discloses a kind of hard disk controlling interface arrangement, has serial universal input output (serial general purpose input/output, SGPIO) converter, controller and decoder.SGPIO data-signals are converted to signal to be decoded by SGPIO converters to foundation SGPIO clock signals with SGPIO load signals.Controller with internal clock signal to judge the source of SGPIO load signals according to SGPIO load signals, to produce selection signal.SGPIO converters and controller is electrically connected in decoder, has multiple decodings regular, selects one of decoding rule that signal to be decoded is decoded as into control signal to foundation selection signal.
Description
Technical field
The present invention can recognize serial universal input output automatically on a kind of hard disk controlling interface arrangement especially in regard to one kind
The hard disk controlling interface arrangement of signal source category.
Background technology
All there is serial universal input output (serial general purpose in many computer systems or server
Input/output, SGPIO) decoder, to control the lumination of light emitting diode of hard disk in systems, to facilitate operator to monitor
The state of hard disk.However, computer system/server is controlled firmly using a variety of different hard disk controlling cards or South Bridge chip sometimes
Disk, and the form that different controllers is set in SGPIO signals for the control signal of the light emitting diode of each hard disk is usual
It is different.Therefore, the common practice is come which kind of hard disk control allows SGPIO decoders to know be currently with wire jumper (jumper) now
Device processed, and then switch different decoding rules.
But this way has some shortcomings：Just it is necessarily provided with corresponding pin array using wire jumper, and such pin
Pin array either occupies the area of mainboard or can influence the configuration of signal wire.And with the component density of current system
More and more higher, mainboard not necessarily have space to set pin array.When user or assembler change hard disk controller, except
The line that changes gear must also change jumper settings outside, so as to add the risk of artificial careless mistake.In addition, many holders have not only
One server node manages hard disk, when system does not allow to be each server node respectively to pin array, this expression
All server nodes must all use same hard disk controller, the use of this hard disk controller that ossify.
The content of the invention
In view of the above problems, the present invention is intended to provide a kind of hard disk controlling interface arrangement, automatically to recognize what is received
The source category of SGPIO hard disk controlling signals.
According to the hard disk controlling interface arrangement of one embodiment of the invention, there is serial universal input output (serial
General purpose input/output, SGPIO) converter, controller and decoder.SGPIO converters are to foundation
SGPIO data-signals are converted to signal to be decoded by SGPIO clock signals with SGPIO load signals.Controller is to foundation
SGPIO load signals judge the source of SGPIO load signals with internal clock signal, to produce selection signal.Decoder is distinguished
SGPIO converters and controller are electrically connected with, there are multiple decoding rules, to foundation selection signal selection decoding rule wherein
One of so that signal to be decoded is decoded as into control signal.
In summary, the hard disk controlling interface arrangement according to one embodiment of the invention, by SGPIO load signals and inside
Clock signal judges the source category of SGPIO load signals, and selects correct SGPIO decoded data signals rule according to this,
To realize the purpose for recognizing, being correctly decoded automatically.
More than on the explanation of present invention and the explanation of following embodiment demonstrating and explain the present invention
Spirit and principle, and provide the present invention patent application claims protection domain further explain.
Brief description of the drawings
Fig. 1 is the functional block diagram of the hard disk controlling interface arrangement according to one embodiment of the invention.
Fig. 2A is the circuit diagram of the decoder according to one embodiment of the invention.
Fig. 2 B are the circuit diagram of the decoder according to another embodiment of the present invention.
Fig. 3 A are the circuit framework figure of the controller according to one embodiment of the invention.
Signal timing diagrams of Fig. 3 B and Fig. 3 C for the controller corresponding to Fig. 3 A under two kinds of different conditions.
Fig. 4 is the circuit framework figure of the controller according to another embodiment of the present invention.
Fig. 5 is the circuit framework figure of the controller according to further embodiment of this invention.
Fig. 6 is the circuit framework figure of the controller according to yet another embodiment of the invention.
Wherein, reference：
1000 hard disk controlling interface arrangements
1100 serial universal input output translators
1200th, 1200A, 1200B decoder
1210th, 1220 decoding circuit
1230 selection circuits
1240 logic circuits
1300th, 1300A~1300D controllers
1310th, 1321~1326,1330 buffer
1320th, 1340 shift registor
1350th, 1370,1380 logic circuit
1360 counters
1400 clock pulse generators
Count count values
CTRL control signals
CTRL1, CTRL2 output signal
DATA_P signals to be decoded
ICLK internal clock signals
MEM storage mediums
Q_INT internal signals
SEL selection signals
The serial universal input output clock signals of SGPIOCLK
The serial universal input output loading signals of SGPIOLOAD
The serial universal input outputting data signals of SGPIODATA
T1~T9 time points
VDD system power supply voltages
VH high voltages
VL low-voltages
Vs, Vst status signal
Embodiment
The detailed features and advantage of the narration present invention, its content are enough to make any ability in detail in embodiments below
The technical staff in domain understands the technology contents of the present invention and implemented according to this, and is wanted according to content disclosed in this specification, right
Protection domain and accompanying drawing are asked, any those skilled in the art can be readily understood upon the purpose and advantage of correlation of the invention.Below
Embodiment the viewpoint of the present invention is further described, it is but non-anyways to limit scope of the invention.
Fig. 1 is refer to, it is the functional block diagram of the hard disk controlling interface arrangement according to one embodiment of the invention.Such as Fig. 1
Shown, the hard disk controlling interface arrangement 1000 according to one embodiment of the invention has serial universal input output (serial
General purpose input/output, SGPIO) converter 1100, decoder 1200 and controller 1300.
Serial universal input output translator 1100, to according to serial universal input output clock signal SGPIOCLK with
Serial universal input outputting data signals SGPIODATA is converted to by serial universal input output loading signal SGPIOLOAD
Signal DATA_P to be decoded.Specifically, serial universal input output translator 1100 is by the serial general of serial signal form
Inputoutput data signal SGPIODATA is converted into the signal DATA_P to be decoded of parallel signals form.Serial universal input is defeated
Integrated circuit realiration can be used by going out converter 1100.
Serial universal input output translator 1100 and controller 1300, decoder is electrically connected in decoder 1200
1200 have it is multiple decoding rule, to according to controller 1300 export selection signal SEL come select it is aforesaid plurality of decoding rule
Then one of them by signal DATA_P to be decoded to be decoded as control signal CTRL.Explain decoder for two example two below
1200 function mode, but decoder 1200 is not limited only to following two embodiment.
In the first embodiment, Fig. 2A is refer to, it is the circuit diagram of the decoder according to one embodiment of the invention.
Decoder 1200A in the present embodiment has the first decoding circuit 1210, the second decoding circuit 1220 and selection circuit 1230.The
One decoding circuit 1210 is used to signal DATA_P to be decoded is converted into the first output signal CTRL1 with the first decoding rule.The
Two decoding circuits 1220 are used to signal DATA_P to be decoded is converted into the second output signal CTRL2 with the second decoding rule.Choosing
Select circuit 1230 and be electrically connected with the first decoding circuit 1210 and the second decoding circuit 1220, selection circuit 1230 is to according to selection
Signal SEL selection one of the first output signal CTRL1 and the second output signal CTRL2 is as control signal CTRL.Specifically
For, the first decoding circuit 1210 and the second decoding circuit 1220 are with the side of hardware circuit its decoding rule
Formula is realized.The first decoding circuit 1210, the second decoding circuit 1220 in the present embodiment are with selection circuit 1230 for example with integrated
Circuit realiration.
In second of embodiment, Fig. 2 B are refer to, it is the circuit of the decoder according to another embodiment of the present invention
Figure.Decoder 1200B in the present embodiment has storage medium MEM and logic circuit 1240.Storage medium MEM stores multiple
Decoding rule.Logic circuit 1240 is electrically connected with storage medium MEM.Logic circuit 1240 to according to selection signal SEL from storage
Deposit medium MEM and read one of decoding rule.Logic circuit 1240 and according to the decoding rule that is read by signal to be decoded
DATA_P is converted to control signal CTRL.Storage medium MEM in the present embodiment is with logic circuit 1240 for example with integrated circuit
Realize.Further, logic circuit 1240 is, for example, FPGA (field programmable gate
Array, FPGA), CPLD (complex programmable logic device, CPLD), microcontroller
Device (micro controller unit, MCU), single-chip processor or other suitable digital circuits.Storage medium MEM examples
Such as it is volatility storage medium or non-volatile storage medium, wherein, if storage medium MEM is volatility storage medium, often
Secondary power-off needs to re-write decoding rule after reopening.
Controller 1300 is to according to serial universal input output loading signal SGPIOLOAD and internal clock signal iCLK
Serial universal input output loading signal SGPIOLOAD source is judged, to produce selection signal SEL.It is interior in an embodiment
Frequency of the portion clock signal iCLK frequency higher than serial universal input output clock signal SGPIOCLK, and in an embodiment
In, internal clock signal iCLK is produced by the clock pulse generator 1400 in hard disk controlling interface arrangement 1000, clock pulse generator
1400 be, for example, the clock pulse generator with quartz (controlled) oscillator.In another embodiment, internal clock signal iCLK is by hard disk control
The system clock signal that server where interface arrangement 1000 processed is provided, and different from serial universal input output clock pulse
Signal SGPIOCLK.The function mode of controller 1300 is explained for some embodiments below, but controller 1300 is not only
It is limited to the following example.
In an embodiment, Fig. 3 A are refer to, it is the Organization Chart of the controller circuitry according to one embodiment of the invention.Such as
Shown in Fig. 3 A, controller 1300A in the present embodiment there is the first buffer 1310, be made up of buffer 1321~1326 6
The buffer 1330 of bit shift buffer 1320 and second.First buffer 1310 is to by internal clock signal iCLK trailing edges
It is internal signal Q_INT to trigger and export the serial universal input output loading signal SGPIOLOAD received.Shift registor
In 1320, the input of buffer 1321 is electrically connected to high voltage (being, for example, system power supply voltage VDD), shift registor
1320 are triggered by internal clock signal iCLK rising edges and carry out shift register running.So-called rising edge triggering, is referred to when tactile
Signalling is by low-voltage VL when being changed to high voltage VH, the action specified.Conversely, so-called trailing edge triggering, refers to working as
When trigger signal is changed to low-voltage VL by high voltage VH, the action specified.For example, as internal clock signal iCLK
When being changed by low-voltage VL to high voltage VH, buffer 1322 can send the voltage that buffer 1321 is exported to buffer
1323.When internal clock signal iCLK is changed to low-voltage VL by high voltage VH, the first buffer 1310 can incite somebody to action serial general
Input and output load signal SGPIOLOAD outputs are internal signal Q_INT.
And the output of the 6th grade (buffer 1326) of 6 bit shift buffers 1320 is defined as status signal Vs.Wherein,
When internal signal Q_INT is low-voltage VL (for example, ground voltage, 0 volt), 6 bit shift buffers 1320 can be reset,
That is the voltage that the output end of buffer 1321~1326 is exported is 0 volt.Second buffer 1330 is serially led to
It is selection signal SEL to be triggered with input and output load signal SGPIOLOAD trailing edges and exported status signal Vs.
Make flowing mode for a further understanding of Fig. 3 A circuit, refer to Fig. 3 B and Fig. 3 C, it is corresponding to Fig. 3 A's
Signal timing diagram of the controller under two kinds of different conditions.
Fig. 3 B are refer to first, and in this state, serial universal input output loading signal SGPIOLOAD is high voltage VH
Time span be more than internal clock signal iCLK six cycles.First in first time point T1, internal clock signal iCLK
Trailing edge and now serial universal input output loading signal SGPIOLOAD is just changed into high voltage from low-voltage VL
VH, hence in so that internal signal Q_INT is transformed into high voltage VH by low-voltage VL.In this way, 6 bit shift buffers 1320 are no longer
It is reset.And then since the second time point T2, buffer 1321~1326 all starts the every of internally clock signal iCLK
The voltage of input is sent to output end by rising edge, therefore is calculated since the second time point T2, internal clock signal
ICLK the 6th rising edge, is exactly just the 3rd time point T3, and now status signal Vs can be converted to high electricity from low-voltage VL
Press VH.Next, during the 4th time point T4, serial universal input output loading signal SGPIOLOAD is transformed into from high voltage VH
Low-voltage VL (trailing edge), so that the second buffer 1330 is triggered and by now status signal Vs voltage (high voltage
VH) output is selection signal SEL.During following 5th time point T5, internal clock signal iCLK trailing edge make it that first is temporary
Serial universal input output loading signal SGPIOLOAD voltage (low-voltage VL) output is internal signal Q_ by storage 1310
INT, so as to reset 6 bit shift buffers 1320, its result causes status signal Vs voltage to be also pulled low.
Fig. 3 C are refer to again, in this state, serial universal input output loading signal SGPIOLOAD is high voltage VH
Time span be less than internal clock signal iCLK six cycles.First in the 6th time point T6, internal clock signal iCLK
Trailing edge and now serial universal input output loading signal SGPIOLOAD is just changed into high voltage from low-voltage VL
VH, hence in so that internal signal Q_INT is transformed into high voltage VH by low-voltage VL.In this way, 6 bit shift buffers 1320 are no longer
It is reset.And then since the 7th time point T7, buffer 1321~1326 all starts the every of internally clock signal iCLK
The voltage of input is sent to output end by rising edge.Next, during the 8th time point T8, serial universal input output is negative
Information carrying SGPIOLOAD is transformed into low-voltage VL (trailing edge) from high voltage VH, so that the second buffer 1330 is triggered
And be selection signal SEL by now status signal Vs voltage output, however, now because the time point T7 of distance the 7th just undergoes
Five internal clock signal iCLK rising edge, therefore status signal Vs is still low-voltage VL, so as to the second buffer 1330
The selection signal SEL exported is also maintained at low-voltage VL.During following 9th time point T9, under internal clock signal iCLK
Drop is along so that the first buffer 1310 exports serial universal input output loading signal SGPIOLOAD voltage (low-voltage VL)
For internal signal Q_INT, so as to reset 6 bit shift buffers 1320., can from above-mentioned Fig. 3 B and Fig. 3 C signal timing diagram
Serial universal input output loading signal SGPIOLOAD can be differentiated as high electricity using the framework for the controller 1300A for learning Fig. 3 A
Press whether VH time span is less than internal clock signal iCLK six cycles.Specifically, as long as being suitably designed this control
The length of shift registor in device processed, it is possible to adjust the rule of judgement.Such as by the Design of length of shift registor be 8
Member (is concatenated) by eight buffers, then it is high voltage VH's that can differentiate serial universal input output loading signal SGPIOLOAD
Whether time span is less than internal clock signal iCLK eight cycles.
In another embodiment, Fig. 4 is refer to, it is the circuit framework of the controller according to another embodiment of the present invention
Figure.As shown in figure 4, controller 1300B in the present embodiment have the first buffer 1310, N-bit shift registor 1340 with
Logic circuit 1350.Wherein N is the positive integer more than 1.The controller 1300B and Fig. 3 A of the present embodiment controller 1300A's
Difference is that what the N-bit shift registor 1340 in the controller 1300B of the present embodiment was exported not only has N levels
Output voltage (bit), but the output voltage of part (more bits) is selected from N levels as one group of status signal Vst.And
Logic circuit 1350 is triggered by serial universal input output loading signal SGPIOLOAD trailing edges and according to this group of status signal
Vst output selection signals SEL.For example, if N is equal to 6, and this group of status signal Vst totally six bits, then logic circuit 1350
Most multipotency recognizes the serial universal input output loading signal SGPIOLOAD of 6 kinds of differences (Cycle Length).
In another embodiment, Fig. 5 is refer to, it is the circuit framework of the controller according to further embodiment of this invention
Figure.As shown in figure 5, the controller 1300C in the present embodiment has the counter 1360 and logic circuit being electrically connected to each other
1370.Counter 1360 by serial universal input output loading signal SGPIOLOAD rising edges trigger and start according to it is internal when
Arteries and veins signal iCLK is counted with accumulated counts value count.In an embodiment, internal clock signal iCLK often passes through a cycle,
Then count value count can add one.When count value count is equal to a threshold value of the inner setting of logic circuit 1370, logic
Voltage of the circuit 1370 according to the serial universal input output loading signal SGPIOLOAD, selection signal SEL corresponding to generation is simultaneously
Reset count value count, now, logic circuit 1370 and make counter 1360 stop counting.
In another embodiment, Fig. 6 is refer to, it is the circuit framework of the controller according to yet another embodiment of the invention
Figure.As shown in fig. 6, the controller 1300D in the present embodiment has the counter 1360 and logic circuit being electrically connected to each other
1380.The difference of this embodiment and Fig. 5 embodiment is logic circuit 1380 by serial universal input output loading signal
SGPIOLOAD trailing edges trigger and read count value count and counter 1360 is stopped accumulated counts value count, logic electricity
Road 1380 and count value count according to reading produces selection signal SEL.Wherein logic circuit 1380 is in stopping counter 1360
Counter 1360 is only set to reset count value count after accumulated counts value count.Specifically, the controller in this embodiment
Even 1300D goes for differentiating two kinds of more kinds of different serial universal input output loading signal SGPIOLOAD.
In summary, the hard disk controlling interface arrangement according to one embodiment of the invention, by SGPIO load signals and inside
Clock signal judges the source category of SGPIO load signals, and selects correct SGPIO decoded data signals rule according to this,
To realize the purpose for recognizing, being correctly decoded automatically.
Although the present invention is disclosed as above with embodiment, so it is not limited to the present invention, any art technology
Personnel, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations, therefore protection scope of the present invention
It is defined when depending on the scope of which is defined in the appended claims.
Claims (9)
1. a kind of hard disk controlling interface arrangement, it is characterised in that the hard disk controlling interface arrangement includes：
One serial universal input output translator, to serial general defeated according to a serial universal input output clock signal and one
Enter output loading signal and one serial universal input outputting data signals are converted to a signal to be decoded；
One controller, to judge that this is serial general with an internal clock signal according to the serial universal input output loading signal
The source of input and output load signal, to produce a selection signal；And
One decoder, the serial universal input output translator and the controller is electrically connected, there are multiple decoding rules,
To select one of those decoding rules that the signal to be decoded is decoded as into a control signal according to the selection signal.
2. hard disk controlling interface arrangement as claimed in claim 1, it is characterised in that the frequency of the internal clock signal is higher than should
The frequency of serial universal input output clock signal.
3. hard disk controlling interface arrangement as claimed in claim 1 or 2, it is characterised in that further include a clock pulse generator to produce
The raw internal clock signal.
4. hard disk controlling interface arrangement as claimed in claim 1, it is characterised in that the decoder includes：
One first decoding circuit, for the signal to be decoded to be converted into one first output signal with one first decoding rule；
One second decoding circuit, for the signal to be decoded to be converted into one second output signal with one second decoding rule；With
And
One selection circuit, first decoding circuit and second decoding circuit are electrically connected with, to be selected according to the selection signal
One of first output signal and second output signal are used as the control signal.
5. hard disk controlling interface arrangement as claimed in claim 1, it is characterised in that the decoder includes：
One storage medium, store multiple decoding rules；And
One logic circuit, the storage medium is electrically connected with, to read those decodings from the storage medium according to the selection signal
One of rule, so that the signal to be decoded is converted into the control signal according to the decoding rule being read.
6. hard disk controlling interface arrangement as claimed in claim 1, it is characterised in that the controller includes：
One first buffer, the serial universal input received is exported negative to be triggered by the internal clock signal trailing edge
Load signal output is an internal signal；
One N-bit shift registor, there is one second input to be electrically connected to a high voltage, to by the internal clock signal
Rising edge triggers and carries out shift register running to export a status signal in the N levels of the N-bit shift registor, and works as and be somebody's turn to do
Internal signal is reset when being a low-voltage, and wherein N is the integer more than 1；And
One second buffer, the status signal is exported to be triggered by the serial universal input output loading signal trailing edge
For the selection signal.
7. hard disk controlling interface arrangement as claimed in claim 1, it is characterised in that the controller includes：
One first buffer, the serial universal input received is exported negative to be triggered by the internal clock signal trailing edge
Load signal output is an internal signal；
One N-bit shift registor, there is one second input to be electrically connected to a high voltage, to by the internal clock signal
Rising edge triggers and carries out shift register running to export N number of status signal, and is weighed when the internal signal is a low-voltage
Put, wherein N is the integer more than 1；And
One logic circuit, to defeated according to those status signals by the serial universal input output loading signal trailing edge triggering
Go out the selection signal.
8. hard disk controlling interface arrangement as claimed in claim 1, it is characterised in that the controller includes：
One counter, start to believe according to the internal clock to be triggered by the serial universal input output loading signal rising edge
Number count with add up a count value；And
One logic circuit, the counter is electrically connected with, it is defeated according to the serial universal input when the count value is equal to a threshold value
The voltage for going out load signal produces the selection signal and resets the count value, makes the counter stop counting.
9. hard disk controlling interface arrangement as claimed in claim 1, it is characterised in that the controller includes：
One counter, start to believe according to the internal clock to be triggered by the serial universal input output loading signal rising edge
Number count with add up a count value；And
One logic circuit, the counter is electrically connected with, to be read by the serial universal input output loading signal trailing edge triggering
Take the count value and the counter is stopped the count value that adds up, the selection signal is produced according to the count value read；
Wherein the logic circuit makes the counter reset the count value after the counter is stopped the cumulative count value.
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|---|---|---|---|
| CN201711187816.XA CN107885678B (en) | 2017-11-24 | 2017-11-24 | Hard disk control interface device |
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|---|---|---|---|
| CN201711187816.XA CN107885678B (en) | 2017-11-24 | 2017-11-24 | Hard disk control interface device |
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| CN107885678B CN107885678B (en) | 2020-12-22 |
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| Publication number | Publication date |
|---|---|
| CN107885678B (en) | 2020-12-22 |
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