KR940001490Y1 - Reset signal occurance circuit for source support - Google Patents

Abstract

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Description

Power supply reset signal generation circuit

1 is a conventional power supply reset signal generation circuit diagram.

(A) to (c) of FIG. 2 are operational waveform diagrams according to FIG.

3 is a power supply reset signal generation circuit diagram of the present invention.

(A) to (i) of FIG. 4 are output waveform diagrams according to FIG.

* Explanation of symbols for main parts of the drawings

1: Reset signal generator 2: Counter

3: multiplexer 4: flip-flop

TF1-TF4: Tip flip flop ND1-ND5: NAND gate

I1-I11: Inverter TG: Transmission Gate

R: Resistor C1: Capacitor

NR1-NR3: Noah gate

The present invention relates to a power supply reset signal generation circuit, and more particularly to a power supply reset signal generation circuit that allows the internal count value to select the width of the reset signal according to a value determined by the user.

Conventionally, as shown in FIG. 1, a power supply terminal Vdd is connected to ground through a resistor R1 and a capacitor C1, and a node n1 between the resistor R1 and a capacitor C1 is an inverter. It is configured to sequentially connect to (I1-I3) to generate a reset signal RST.

A conventional circuit configured as described above will be described below with reference to an operation waveform diagram as shown in (a) to (c) of FIG. 2.

First, as shown in (a) of FIG. 2, when the power supply Vdd goes from the low "0" to the high "1", the capacitor C1 is charged to the node n1 between the resistor R1 and the capacitor C1. The voltage goes from low “0” to high “1” as in (b) of FIG.

At this time, the output of inverter I3 is “0” state as it is charged above threshold voltage Vth from “1” state when node n1 voltage is below threshold voltage Vth. As shown. Here, the reset delay time is determined according to the time constant RC size.

As described above, as the power supply Vdd repeats on / off, the above operation is repeated to generate a power supply reset signal.

However, such a conventional power supply reset signal generating circuit is difficult to adjust to a time constant (RC) value when the internal circuit is composed of resistance values and capacitor values in order to have various reset widths, and the integrated system is complicated. Or if the integrated circuit is large, there was a problem that occupies a lot of chip area.

Accordingly, in view of such a conventional defect, the present invention uses the power supply reset signal by the time constant RC as an initialization signal of the counters TF1-TF4 to output the desired count value according to a value determined by the user. By selecting the power supply reset signal generating circuit having various reset widths, the present invention is described with reference to FIGS. 3 and 4 as follows.

3 is a power supply reset signal generation circuit diagram of the present invention, and includes a reset signal generator 1 for delaying the reset signal with a time constant by the resistor R1 and the capacitor C1 and generating a reset signal. The counting signal is reset by the output of the set signal generator 1 and receives the clock signal ND from the NAND gate ND1 with the clock signal through the club signal CLK and the transmission gate TG as the clock terminal CK. A counter (2), a multiplexer (3) for multiplexing the output signal and the option signals (S1, S2) of the counter (2), and an output signal of the multiplexer (3) through a set terminal (S). The set width is selected and the flip-flop 4 is configured to receive the signal of the reset signal generator 1 through the reset terminal R and finally output the output through the inverter I11.

Referring to the operation and effects of the present invention configured as described above in detail.

First, when the power supply Vdd goes from the low "0" to the high "1", there is a delay by a time constant by the resistor r1 and the capacitor C1, and then the node n1 voltage is passed through the inverters I1 and I2. The reset signal is generated as shown in (a) of Fig. 3 from 0 ”to“ 1 ”.

While the voltage of the node n1 is "1", the flip-flop TF1-TF4 is reset and its outputs Q1-Q4 are in the mode "0" state, so the output of the NAND gate ND2 is "1". It becomes a state. When the voltage of the node n1 becomes “0”, the counter 2 composed of the flip-flops TF1-TF4 starts counting according to the clock CLK as shown in (b) of FIG. 3. The outputs Q1-Q4 of the respective flip-flops TF1-TF4 output a signal as shown in Figs.

At this time, a reset signal of different clock signal cycles is generated according to the values of the option signals S1 and S0. For example, when the option signals S1 and S0 have a value of (0,0), the option signals S1 and S0 are generated. NAND combination of the signal inverted through the inverters I3 and I4 and the output signal of the flip-flop TF1-TF4 constituting the counter 2 to the NAND gates ND3-ND5 and ND2. Then, the inverted signal through the inverters I5-I8 is input to the set terminal 5 of the flip-flop 4 via the noar gate NR1 and the inverter I9, and the reset signal RST is reset. The reset signal, which is input to the terminal R and is one time R1 of the clock signal period R1 as shown in FIG. 3 (i) through the inverter I11, is finally output.

Here, the clock signal period is adjusted according to the values of the option signals S1 and S0. If the status option signals S1 and S0 are (0,0), the reset width is 1 times the clock signal period (R1) and (0). If 1, 4 times R3, and if (1, 1), the signal whose reset width is 8 times the clock signal period can be used as the reset signal.

In response to the supply of the power supply Vdd, the reset (RST) signal generated after a predetermined time delay by the time constant resets the flip-flop TF1-TF4 constituting the counter 2, When set and then set, it is counted according to an input clock. The output of the count value is selected according to a user-specified value, and the output values of the tip flip-flops TF1-TF4 and the option signals S1 and S0 are selected. Final output through multiplexer 3 and clip-flop 4 to multiplex, where 1 times (R1), 2 times (R2), 4 times (R3) of the clock signal period depending on the values of the option signals S1, S0. ), An eight times reset signal R4 is output.

As described in detail above, the present invention implements a circuit having various reset widths by selecting the output of the internal count value according to a user-specified value instead of configuring a circuit with resistors and capacitors to have various reset widths. It is not necessary to adjust by the time constant RC, and the chip area is reduced.

Claims (1)

In the power supply reset signal generation circuit for generating a reset signal in the reset signal generator 1 after a delay in accordance with the time constant by the resistor R1 and the capacitor C1, the reset signal generator 1 A counter 2 counting according to the club CLK reset and applied by an output signal of the < RTI ID = 0.0 >) < / RTI > and a multiplexer 3 multiplexing the output signal of the counter 2 and the option signals S1 and S2 The input signal of the multiplexer 3 is input to the set terminal S, the reset width is selected, and the signal of the reset signal generator 1 is input to the reset terminal R. A power supply reset signal generation circuit comprising a flip-flop (4) for final output through (I11).