CN107871518A - Logical-arithmetic unit based on variable-resistance memory unit and the method that dyadic Boolean logical operation is realized using it - Google Patents
Logical-arithmetic unit based on variable-resistance memory unit and the method that dyadic Boolean logical operation is realized using it Download PDFInfo
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- CN107871518A CN107871518A CN201610858694.1A CN201610858694A CN107871518A CN 107871518 A CN107871518 A CN 107871518A CN 201610858694 A CN201610858694 A CN 201610858694A CN 107871518 A CN107871518 A CN 107871518A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Abstract
The invention provides a kind of logical-arithmetic unit based on variable-resistance memory unit, is formed by a variable-resistance memory unit and a switch by series connection.The logical-arithmetic unit is simple in construction, it is ingenious in design, low manufacture cost, pass through design logic operation rule, all 16 kinds of dyadic Boolean logical operations can be completed in the case where being not more than write operation three times, and logic operation result can be stored in variable-resistance memory unit automatic and non-volatilely, thus data processing and store function can be integrated, the practicalization of resistance-variable storing device base logic circuit can be greatly promoted, the development to resistance-variable storing device base logic circuit is significant.
Description
Technical field
The present invention relates to logical-arithmetic unit technical field, more particularly to a kind of logical operation based on variable-resistance memory unit
Device, and the method for realizing using the logical-arithmetic unit dyadic Boolean logical operation.
Background technology
Logic circuit is the core component that current computer carries out data processing.Logic circuit based on traditional cmos process
The physics limit of its miniaturization is up to, and it is complicated, function is single, and energy consumption is higher.Therefore, based on new material, new knot
The new logic circuit of structure and new device is by the growing concern of people.
Resistance-variable storing device is a kind of promising nonvolatile memory of future generation, have it is simple in construction, be easily integrated, wipe
The advantages such as writing rate is fast, operation power consumption is low so that resistance-variable storing device base logic circuit is better than traditional CMOS in combination property
Logic circuit.Importantly, having benefited from the intrinsic non-volatile of resistance-variable storing device, associated logical circuitry can collect data processing
Be stored in one, be expected to break through for a long time limit computer actual motion speed " von Neumann bottleneck ", to calculating
The performance of machine brings qualitative leap.
Currently, the core of this area correlative study work is the implementation method for exploring resistance-variable storing device base logical operation,
Simple Devices and the multi-functional logic realization method of circuit structure are based particularly on, to simplify circuit knot in practical application
Structure, integration density is improved, reduce and prepare cost.Although the variable-resistance memory unit based on single twin voltage polar operation realizes part
The universal method of dyadic logical operation has been suggested and proved, but there has been no based on single any variable-resistance memory unit so far
Realize that the universal method of all 16 kinds of dyadic Boolean logical operations is reported, hinder the practicality of resistance-variable storing device base logic circuit
Change process.
The content of the invention
In view of the above-mentioned problems, the present invention is intended to provide a kind of logical-arithmetic unit based on variable-resistance memory unit, logic fortune
It is simple in construction to calculate device, a variety of dyadic Boolean logical operations can be realized.
To realize above-mentioned technical purpose, the present inventor opens a variable-resistance memory unit M and one after exploratory development
S is closed to be cascaded, can be ingenious by controlling the size of variable-resistance memory unit M input driving voltages and switching S folding
Realize all 16 kinds of dyadic Boolean logical operations in ground.
The technical scheme is that：A kind of logical-arithmetic unit based on variable-resistance memory unit, by a resistance-change memory list
First (M) and switch (S) composition；
Described variable-resistance memory unit is resistor-type random memory unit, including first electrode (T1), second electrode (T2)
And intermediate layer, intermediate layer is between first electrode and second electrode, in the case where writing voltage drive, the variable-resistance memory unit table
Reveal the transformation between high low resistance state and memory characteristic, it is V to define write-in voltage corresponding to high-impedance stateH, write corresponding to low resistance state
It is V to enter voltageL；
During working condition, write-in voltage is applied to T1 ends, and loop is formed after T2 ends series connection S；
Using the write-in voltage at T1 ends and S folding condition as two logic input terminals, high low resistance state using M is as patrolling
Output end is collected, input logic value and output logic value definition are as follows：
The input logic value at T1 ends and the corresponding relation of write-in voltage：The corresponding write-in voltage V of input logic value 0H, input patrols
Collect the corresponding write-in voltage V of value 1L；
S input logic value and the corresponding relation of its physical state：The corresponding S closures of input logic value 0, input logic value 1
Corresponding S disconnects；
Export the corresponding relation of logical value and M high low resistance state：The corresponding M of logical value 0 high-impedance state is exported, exports logical value
1 corresponding M low resistance state.
According to the relation that polarity of voltage is write between high low resistance state, variable-resistance memory unit can be divided into following two class：
The first kind：The write-in polarity of voltage of high low resistance state is identical, as shown in Fig. 2 the referred to as resistive of single voltage polarity operation
Memory cell, wherein Vreset≤VH＜ Vset, VL≥Vset, VsetIt is the threshold voltage that low resistance state is converted to by high-impedance state, VresetIt is
The threshold voltage of high-impedance state is converted to by low resistance state.
Second class：The write-in polarity of voltage of high low resistance state is on the contrary, as shown in figure 3, the referred to as resistive of twin voltage polar operation
Memory cell, wherein VH≤Vreset, VL≥Vset, VsetIt is the threshold voltage that low resistance state is converted to by high-impedance state, VresetIt is by low
Resistance state is converted to the threshold voltage of high-impedance state.
No matter variable-resistance memory unit belongs to the first kind or the second class, when S is closed, applies V at T1 endsLIt can be written into
To low resistance state, and apply V at T1 endsHHigh-impedance state can be written into；Conversely, when S disconnects, apply V at T1 endsLAnd VHNot
The current resistance states of memory cell can be changed.Therefore, in the present invention, described variable-resistance memory unit both can be univoltage pole
Property operation variable-resistance memory unit, can be again twin voltage polar operation variable-resistance memory unit.
Utilize the logical-arithmetic unit of the present invention, setting logical operation rule, you can complete by being not more than write operation three times
Into all 16 kinds of dyadic Boolean logical operations, and the logic operation result can be stored in M automatic and non-volatilely, thus
Data processing and store function can be integrated, the development to resistance-variable storing device base logic circuit is significant.
Write-once operation (W) includes S disconnection or closure and the voltage write-in at T1 ends.
Described write operation three times can be expressed as first time write operation (W1), second of write operation (W2) and
Third time write operation (W3).
In W1, W2 and W3, setting 0,1, p,Q orFor the input logic value at S and T1 ends, p=0 or 1, q=0
Or 1,Symbol represents inversion operation, i.e.,
As shown in table 1 below, 16 kinds of described dyadic Boolean logical operations are True, False, p, q, NOT p, NOT respectively
q、p AND q、p NAND q、p OR q、p NOR q、p IMP q、p NIMP q、p RIMP q、p RNIMP q、p XOR
Q, and p XNOR q.
Wherein, True, False, p, q, NOT p and NOT q computings only need W1 to can be achieved.Preferably, such as table 1 below institute
Show, logical operation rule is as follows：
(1)True：
In W1,0 and 1 is separately input to S and T1 ends；
(2)False：
In W1,0 and 0 is separately input to S and T1 ends；
(3)p：
In W1,0 and p is separately input to S and T1 ends；
(4)q：
In W1,0 and q is separately input to S and T1 ends；
(5)NOT p：
In W1,0 HeIt is separately input to S and T1 ends；
(6)NOT q：
In W1,0 HeIt is separately input to S and T1 ends；
Wherein, p AND q, p NAND q, p OR q, p NOR q, p IMP q, p NIMP q, p RIMP q and p
RNIMP q computings need to carry out W1 and W2 write operations successively and can be achieved.Preferably, as shown in table 1 below, logical operation rule
It is then as follows：
(7)p AND q：
In W1,0 and 0 is separately input to S and T1 ends；
In W2,S and T1 ends are separately input to q；
(8)p NAND q：
In W1,0 and 1 is separately input to S and T1 ends；
In W2,WithIt is separately input to S and T1 ends；
(9)p OR q：
In W1,0 and 1 is separately input to S and T1 ends；
In W2, p and q are separately input to S and T1 ends；
(10)p NOR q：
In W1,0 and 0 is separately input to S and T1 ends；
In W2, p andIt is separately input to S and T1 ends；
(11)p IMP q：
In W1,0 and 1 is separately input to S and T1 ends；
In W2,S and T1 ends are separately input to q；
(12)p NIMP q：
In W1,0 and 0 is separately input to S and T1 ends；
In W2,WithIt is separately input to S and T1 ends；
(13)p RIMP q：
In W1,0 and 1 is separately input to S and T1 ends；
In W2, p andIt is separately input to S and T1 ends；
(14)p RNIMP q：
In W1,0 and 0 is separately input to S and T1 ends；
In W2, p and q are separately input to S and T1 ends；
And p XOR q and p XNOR q computings then need to carry out W1, W2 and W3 write operation successively to realize.As excellent
Choosing, as shown in table 1 below, logical operation rule is as follows：
(15)p XOR q：
In W1,0 and 0 is separately input to S and T1 ends；
In W2, p and q are separately input to S and T1 ends；
In W3, q and p are separately input to S and T1 ends；
(16)p XNOR q：
In W1,0 and 0 is separately input to S and T1 ends；
In W2, p andIt is separately input to S and T1 ends；
In W3,S and T1 ends are separately input to p.
Table 1：The operation rule of all 16 kinds of dyadic Boolean logics in the present invention
In summary, the present invention is based on a variable-resistance memory unit and a switch, and by connecting, one logic of formation is transported
Device is calculated, is had the advantages that：
(1) it is simple in construction, ingenious in design, low manufacture cost；
(2) by design logic operation rule, all 16 kinds of binary cloth can be completed in the case where being not more than write operation three times
That logical operation, and logic operation result can be stored in variable-resistance memory unit automatic and non-volatilely, thus number can be collected
According to processing and store function in one, the practicalization of resistance-variable storing device base logic circuit can be greatly promoted, to resistive
The development of memory base logic circuit is significant.
Brief description of the drawings
Fig. 1 is the structural representation of the logical-arithmetic unit of the invention based on variable-resistance memory unit；
Fig. 2 is the V-I cycle characteristics curve maps of the variable-resistance memory unit of single voltage polarity operation；
Fig. 3 is the V-I cycle characteristics curve maps of the variable-resistance memory unit of twin voltage polar operation.
Embodiment
The present invention is described in further detail below in conjunction with drawings and examples, it should be pointed out that reality as described below
Apply example to be intended to be easy to the understanding of the present invention, and do not play any restriction effect to it.
Embodiment 1：
In the present embodiment, variable-resistance memory unit includes first electrode (T1), second electrode (T2) and intermediate layer, intermediate layer position
Between T1 and T2.T1 materials are Ta, and T2 materials are Pt, intermediate layer material Ta2O5, form Ta/Ta2O5/ Pt trilamellar membrane devices
Part, its preparation process are as follows：
First, using radio-frequency magnetron sputter method in Pt (120nm)/Ti/SiO2Ta thick/Si deposition on substrate 10nm2O5It is thin
Film., it is necessary to shelter from sub-fraction substrate in deposition process, so that the part is not by Ta2O5Film covers, and gives over to follow-up survey
Second electrode is served as during examination.
Secondly, in Ta2O5One layer of photoresist of spin coating on film, in conjunction with uv-exposure and developing process, on photoresist layer
Obtain multiple a diameter of 50 μm of hole.
Finally, the thick Ta films of 60nm are deposited using direct current magnetron sputtering process, acetone soak sample is recycled, to peel off
Ta films on photoresist, the Ta films at hole are only left, first electrode is served as when giving over to follow-up test.
Using semiconductor devices analyzer (Agilent B1500A) to the Ta/Ta of above-mentioned preparation2O5/ Pt trilamellar membrane devices
Carry out change resistance performance test.Test temperature is room temperature, and external voltage is applied to the Ta/Ta by the first tungsten tipped probe2O5/ Pt trilamellar membranes
The T1 ends (i.e. Ta electrodes) of device, T2 ends (i.e. Pt electrodes) are grounded by the second tungsten tipped probe.Test result shows, the Ta/Ta2O5/
Pt trilamellar membrane devices have resistive characteristic as shown in Figure 3, VsetAnd VresetRespectively 0.75V and -1V, high-impedance state resistance are
1600 Ω, corresponding to output logical zero, low resistance state resistance is 120 Ω, corresponding to output logic 1.
Utilize the Ta/Ta2O5/ Pt trilamellar membrane device construction logic arithmetic units, it is specially：External voltage passes through the first tungsten tipped probe
It is applied to the Ta/Ta2O5The T1 ends (i.e. Ta electrodes) of/Pt trilamellar membrane devices, T2 ends (i.e. Pt electrodes) are connect by the second tungsten tipped probe
Ground, and by the second tungsten tipped probe T2 ends are contacted and left to realize switch S closed and disconnected.Using semiconductor devices analyzer
(Agilent B1500A) carries out logic testing, and test temperature is room temperature.
Set the V in Fig. 3LAnd VHRespectively 1V and -2V.By the Ta/Ta2O5The write-in electricity at the T1 ends of/Pt trilamellar membrane devices
Pressure and S folding condition are as two logic input terminals, by the Ta/Ta2O5The high low resistance state of/Pt trilamellar membrane devices is used as and patrolled
Output end is collected, input logic value and output logic value definition are as follows：
The input logic value at T1 ends and the corresponding relation of write-in voltage：The corresponding write-in voltage V of input logic value 0H, input patrols
Collect the corresponding write-in voltage V of value 1L；
S input logic value and the corresponding relation of its physical state：The corresponding S closures of input logic value 0, input logic value 1
Corresponding S disconnects；
Export the corresponding relation of logical value and M high low resistance state：Output logical zero corresponds to M high-impedance state, and output logic 1 is right
Answer M low resistance state.
Using in table 1 logical operation rule, setting 0,1, p,Q orFor the input logic value at S and T1 ends, p=0
Or 1, q=0 or 1,Symbol represents inversion operation, i.e.,All 16 kinds of dyadic Booleans can be achieved to patrol
Collect computing.It is described in detail below by taking p NAND q and p NOR q computings as an example：
(1) p NAND q
In W1 write operations, 0 and 1 is separately input to S and T1 ends so that and S is closed, and 1V external voltages are applied to Ta electrodes,
By Ta/Ta2O5/ Pt devices are written to low resistance state.
In W2 write operations,WithS and T1 ends are separately input to, according to p and q actual numerical value, four kinds can be divided into
Situation：
(1) p=0, q=0, can obtainSo that S disconnects, 1V external voltages are applied on Ta electrodes.Because S breaks
Open, device configuration will not be influenceed by external voltage, be rested on low resistance state (120 Ω, corresponding to export logic 1), be realized logical operation p
NAND q=0NAND 0=1.
(2) p=0, q=1, can obtainSo that S disconnects, -2V external voltages are applied on Ta electrodes.Because S breaks
Open, device configuration will not be influenceed by external voltage, be rested on low resistance state (120 Ω, corresponding to export logic 1), be realized logical operation p
NAND q=0NAND 1=1.
(3) p=1, q=0, can obtainSo that S is closed, 1V external voltages are applied on Ta electrodes, can not still changed
Become device resistance state, that is, rest on low resistance state (120 Ω, corresponding to export logic 1), realize logical operation p NAND q=1 NAND
0=1.
(4) p=1, q=1, can obtainSo that S is closed, -2V external voltages are applied on Ta electrodes, by device
High-impedance state (1600 Ω, corresponding to export logical zero) is converted to by low resistance state, realizes logical operation p NAND q=1 NAND 1=
0。
(2) p NOR q：
In W1 write operations, 0 and 0 is separately input to S and T1 ends so that switch S closures, -2V external voltages are applied to Ta
Electrode, by Ta/Ta2O5/ Pt devices are written to high-impedance state.
In W2 write operations, p andS and T1 ends are separately input to, according to p and q actual numerical value, four kinds of feelings can be divided into
Condition：
(1) p=0, q=0, can obtainSo that S is closed, 1V external voltages are applied on Ta electrodes, device by high-impedance state
Low resistance state (120 Ω, corresponding to export logic 1) is converted to, realizes logical operation p NORq=0NOR0=1.
(2) p=0, q=1, can obtainSo that S is closed, -2V external voltages are applied on Ta electrodes, it is impossible to change device
Resistance state, that is, high-impedance state (1600 Ω, corresponding to export logical zero) is rested on, realizes logical operation p NORq=0NOR1=0.
(3) p=1, q=0, can obtainSo that S disconnects, 1V external voltages are applied on Ta electrodes.Because S disconnects, device
Resistance state will not be influenceed by external voltage, be rested on high-impedance state (1600 Ω, corresponding to export logical zero), be realized logical operation p NORq
=1 NOR0=0.
(4) p=1, q=1, can obtainSo that S disconnects, -2V external voltages are applied on Ta electrodes.Because S disconnects, device
Part resistance state will not be influenceed by external voltage, be rested on high-impedance state (1600 Ω, corresponding to export logical zero), be realized logical operation p
NORq=1 NOR1=0.
The various embodiments described above are merely to illustrate the present invention, wherein the structure of each part, connected mode and manufacture craft etc. are all
It can be varied from, every equivalents carried out on the basis of technical solution of the present invention and improvement, should not exclude
Outside protection scope of the present invention.
Technical scheme is described in detail embodiment described above, it should be understood that it is described above only
For the specific embodiment of the present invention, it is not intended to limit the invention, all any modifications made in the spirit of the present invention,
Supplement or similar fashion replacement etc., should be included in the scope of the protection.
Claims (10)
1. a kind of logical-arithmetic unit based on variable-resistance memory unit, it is characterized in that：Opened by a variable-resistance memory unit (M) and one
Close (S) composition；
Described variable-resistance memory unit includes first electrode (T1), second electrode (T2) and intermediate layer, and intermediate layer is positioned at the first electricity
Between pole and second electrode；In the case where writing voltage drive, the variable-resistance memory unit shows the transformation between high low resistance state and note
Recall characteristic, it is V to define write-in voltage corresponding to high-impedance stateH, write-in voltage is V corresponding to low resistance stateL；
During working condition, write-in voltage is applied to T1 ends, and loop is formed after T2 ends series connection S；
It is using the write-in voltage at T1 ends and S folding condition as two logic input terminals, M high low resistance state is defeated as logic
Go out end, input logic value and output logic value definition are as follows：
The input logic value at T1 ends and the corresponding relation of write-in voltage：The corresponding write-in voltage V of input logic value 0H, input logic value 1
Corresponding write-in voltage VL；
S input logic value and the corresponding relation of its physical state：The corresponding S closures of input logic value 0,1 corresponding S of input logic value
Disconnect；
Export the corresponding relation of logical value and M high low resistance state：The corresponding M of logical value 0 high-impedance state is exported, output logical value 1 is right
Answer M low resistance state.
2. the logical-arithmetic unit based on variable-resistance memory unit as claimed in claim 1, it is characterized in that：Described resistance-change memory list
Member both can be the variable-resistance memory unit of single voltage polarity operation, can be the variable-resistance memory unit of twin voltage polar operation again.
3. the side of dyadic Boolean logical operation is realized using the logical-arithmetic unit based on variable-resistance memory unit described in claim 1
Method, it is characterized in that：Write-once operation (W) includes S disconnection or closure and the voltage write-in at T1 ends；
Write-once operation in, setting 0,1, p,Q orFor the input logic value at S and T1 ends, p=0 or 1, q=0 or
Person 1,Symbol represents inversion operation, i.e.,
Logical operation True operation rule is：
In first time write operation (W1), 0 and 1 is separately input to S and T1 ends；
Preferably, logical operation False operation rule is：
In first time write operation (W1), 0 and 0 is separately input to S and T1 ends.
4. the side of dyadic Boolean logical operation is realized using the logical-arithmetic unit based on variable-resistance memory unit described in claim 1
Method, it is characterized in that：Write-once operation (W) includes S disconnection or closure and the voltage write-in at T1 ends；
Write-once operation in, setting 0,1, p,Q orFor the input logic value at S and T1 ends, p=0 or 1, q=0 or
Person 1,Symbol represents inversion operation, i.e.,
Logical operation p operation rule is：
In first time write operation (W1), 0 and p is separately input to S and T1 ends；
Preferably, logical operation q operation rule is：
In first time write operation (W1), 0 and q is separately input to S and T1 ends.
5. the side of dyadic Boolean logical operation is realized using the logical-arithmetic unit based on variable-resistance memory unit described in claim 1
Method, it is characterized in that：Write-once operation (W) includes S disconnection or closure and the voltage write-in at T1 ends；
Write-once operation in, setting 0,1, p,Q orFor the input logic value at S and T1 ends, p=0 or 1, q=0 or
Person 1,Symbol represents inversion operation, i.e.,
Logical operation NOT p rule is as follows：
In W1,0 HeIt is separately input to S and T1 ends；
Preferably, logical operation NOT q rule is as follows：
In W1,0 HeIt is separately input to S and T1 ends.
6. the side of dyadic Boolean logical operation is realized using the logical-arithmetic unit based on variable-resistance memory unit described in claim 1
Method, it is characterized in that：Write-once operation (W) includes S disconnection or closure and the voltage write-in at T1 ends；
Write-once operation in, setting 0,1, p,Q orFor the input logic value at S and T1 ends, p=0 or 1, q=0 or
Person 1,Symbol represents inversion operation, i.e.,
Logical operation p AND q rule is as follows：
In first time write operation (W1), 0 and 0 is separately input to S and T1 ends；
In second of write operation (W2),S and T1 ends are separately input to q；
Preferably, logical operation p NAND q rule is as follows：
In first time write operation (W1), 0 and 1 is separately input to S and T1 ends；
In second of write operation (W2),WithIt is separately input to S and T1 ends.
7. the side of dyadic Boolean logical operation is realized using the logical-arithmetic unit based on variable-resistance memory unit described in claim 1
Method, it is characterized in that：Write-once operation (W) includes S disconnection or closure and the voltage write-in at T1 ends；
Write-once operation in, setting 0,1, p,Q orFor the input logic value at S and T1 ends, p=0 or 1, q=0 or
Person 1,Symbol represents inversion operation, i.e.,
Logical operation p OR q rule is as follows：
In first time write operation (W1), 0 and 1 is separately input to S and T1 ends；
In second of write operation (W2), p and q are separately input to S and T1 ends；
Preferably, logical operation p NOR q rule is as follows：
In first time write operation (W1), 0 and 0 is separately input to S and T1 ends；
In second of write operation (W2), p andIt is separately input to S and T1 ends.
8. the side of dyadic Boolean logical operation is realized using the logical-arithmetic unit based on variable-resistance memory unit described in claim 1
Method, it is characterized in that：Write-once operation (W) includes S disconnection or closure and the voltage write-in at T1 ends；
Write-once operation in, setting 0,1, p,Q orFor the input logic value at S and T1 ends, p=0 or 1, q=0 or
Person 1,Symbol represents inversion operation, i.e.,
Logical operation p IMP q rule is as follows：
In first time write operation (W1), 0 and 1 is separately input to S and T1 ends；
In second of write operation (W2),S and T1 ends are separately input to q；
Preferably, logical operation p NIMP q rule is as follows：
In first time write operation (W1), 0 and 0 is separately input to S and T1 ends；
In second of write operation (W2),WithIt is separately input to S and T1 ends.
9. the side of dyadic Boolean logical operation is realized using the logical-arithmetic unit based on variable-resistance memory unit described in claim 1
Method, it is characterized in that：Write-once operation (W) includes S disconnection or closure and the voltage write-in at T1 ends；
Write-once operation in, setting 0,1, p,Q orFor the input logic value at S and T1 ends, p=0 or 1, q=0 or
Person 1,Symbol represents inversion operation, i.e.,
Logical operation p RIMP q rule is as follows：
In first time write operation (W1), 0 and 1 is separately input to S and T1 ends；
In second of write operation (W2), p andIt is separately input to S and T1 ends；
Preferably, logical operation p RNIMP q rule is as follows：
In first time write operation (W1), 0 and 0 is separately input to S and T1 ends；
In second of write operation (W2), p and q are separately input to S and T1 ends.
10. realize dyadic Boolean logical operation using the logical-arithmetic unit based on variable-resistance memory unit described in claim 1
Method, it is characterized in that：Write-once operation (W) includes S disconnection or closure and the voltage write-in at T1 ends；
Write-once operation in, setting 0,1, p,Q orFor the input logic value at S and T1 ends, p=0 or 1, q=0 or
Person 1,Symbol represents inversion operation, i.e.,
P XOR q logical operation rule is as follows：
In first time write operation (W1), 0 and 0 is separately input to S and T1 ends；
In second of write operation (W2), p and q are separately input to S and T1 ends；
In third time write operation (W3), q and p are separately input to S and T1 ends；
Preferably, p XNOR q logical operation rule is as follows：
In first time write operation (W1), 0 and 0 is separately input to S and T1 ends；
In second of write operation (W2), p andIt is separately input to S and T1 ends；
In third time write operation (W3),S and T1 ends are separately input to p.
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| CN201610858694.1A CN107871518B (en) | 2016-09-28 | 2016-09-28 | Logical operator based on resistive random access memory unit and method for realizing binary Boolean logical operation by using logical operator |
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| CN109994139A (en) * | 2019-03-15 | 2019-07-09 | 北京大学 | A kind of complete non-volatile logic implementation method and its application based on unipolarity memristor |
| CN111061454A (en) * | 2019-12-18 | 2020-04-24 | 北京大学 | Logic implementation method based on bipolar memristor |
| CN112002365A (en) * | 2020-08-21 | 2020-11-27 | 中国科学技术大学 | Parallel logic operation method based on multi-bit nonvolatile memory and full adder |
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| CN112002365A (en) * | 2020-08-21 | 2020-11-27 | 中国科学技术大学 | Parallel logic operation method based on multi-bit nonvolatile memory and full adder |
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