CN106374912B - A kind of logical operation circuit and operating method - Google Patents
A kind of logical operation circuit and operating method Download PDFInfo
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- CN106374912B CN106374912B CN201610817068.8A CN201610817068A CN106374912B CN 106374912 B CN106374912 B CN 106374912B CN 201610817068 A CN201610817068 A CN 201610817068A CN 106374912 B CN106374912 B CN 106374912B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
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Abstract
The invention discloses a kind of logical operation circuit and operating methods；Modulating properties based on the input of 1T1R device multiterminal signal realize 16 kinds of boolean calculations, such as AND, OR, NAND, logic operation result is all stored in 1T1R device with non-volatile resistance states, to realize that logical operation function simultaneously realizes data storage function simultaneously in individual devices, that is, the fusion of storage and calculating, thus device basis is established to surmount the limitation of information apparatus Moore's Law and breaking through von Neumann bottleneck in computer architecture.1T1R device disclosed by the invention can be applied to the fields such as New Solid memory, logical-arithmetic unit, programmable gate array and system on chip as basic unit, to push novel computer framework to provide a new road.
Description
Technical field
The invention belongs to field of microelectronic devices, are based on 1T1R (1 transistor, 1 RRAM) more particularly, to one kind
The logical operation circuit and its logical operation method of device architecture.
Background technique
With the arrival in " big data " epoch, people propose the following non-volatile, high density, low power consumption memories part
Higher requirement, simple performance boost also can no longer meet growing real time data processing task, thus new number
Research hot topic is increasingly becoming according to processing framework.Charge or voltage different from the past using transistor carries out logical operation, and one
The new logical calculation method of kind --- logical operation is carried out as variable using the physical state of device, i.e. state logic is transported
It calculates.Logical operation is carried out as logical signal using the resistance states of RRAM has been achieved for biggish progress, this state
Logical calculation method is expected to realize that calculating is merged with what is stored in individual devices, effectively improves computer digital animation speed.
These advantages can break through the limitation of Moore's Law in existing development of electronic devices.However it largely studies in existing research and does not all have
Have in view of RRAM is in the integrated middle problems faced of industrialization, existing industrialization integrated technology mainly utilizes 1T1R device junction
Structure.In fact, the operating point of RRAM can change, logical operation when RRAM and transistor integrated combination are at 1T1R structure
Method is most of to be all no longer applicable in, and Chinese patent CN201410093949.0 proposes a kind of logical operation electricity of 1T1R array
Road, but it is more using transistor size, and preparation is complicated, to the non-volatile using limited of device.
Summary of the invention
In view of the drawbacks of the prior art, non-volatile logic operation can be realized simultaneously the purpose of the present invention is to provide a kind of
With the logical operation circuit and its logical operation method of information storage.
The present invention provides a kind of logical operation circuit, including transistor and resistance-variable storing device, one end of resistance-variable storing device
As the first signal input part of the logical operation circuit, the drain electrode of the other end and transistor of resistance-variable storing device is connected, brilliant
Second signal input terminal of the source electrode of body pipe as the logical operation circuit, the grid of transistor is as logical operation circuit
Third signal input part；By being inputted simultaneously not in the first signal input part, second signal input terminal and third signal input part
Same pulse signal, so that the resistance states of the resistance-variable storing device change, to realize logical operation.
Further, when applying pulse signal simultaneously in first signal input part and third signal input part, and
When second signal input end grounding, the resistance states of the resistance-variable storing device are to become low resistance state from high-impedance state；When in the second letter
Number input terminal and third signal input part apply pulse signal simultaneously, and when first signal input part is grounded, the resistive
The resistance states of memory are to become high-impedance state from low resistance state.
The present invention also provides a kind of operating methods based on above-mentioned logical operation circuit, include the following steps:
(1) initialization process is carried out to the resistance states of the resistance-variable storing device, and defines the height of the resistance-variable storing device
The corresponding logical signal I of resistance state is " 0 ", and the corresponding logical signal I of the low resistance state of resistance-variable storing device is " 1 "；Wherein, I is described
The corresponding logical signal of initialization resistance states of resistance-variable storing device；
(2) defeated in first signal input part, the second signal input terminal and the third signal input part simultaneously
Enter voltage pulse signal；The corresponding logical signal T when the first signal input part receives zero level pulse1For " 0 ", when first
Signal input part receives logical signal T corresponding when forward voltage pulse1For " 1 ", wherein T1It is applied for the first signal input part
Add the corresponding logical signal of pulse signal；The corresponding logical signal T when second signal input terminal receives zero level pulse2For
" 0 ", the corresponding logical signal T when second signal input terminal receives forward voltage pulse2For " 1 ", wherein T2For the second letter
Number input terminal applies the corresponding logical signal of pulse signal；It is corresponding when third signal input part receives zero level pulse to patrol
Collecting signal G is " 0 ", and when third signal input part receives forward voltage pulse, corresponding logical signal G is " 1 ", wherein G
Apply the corresponding logical signal of pulse signal for third signal input part；
(3) according to formulaIt carries out logical operation and reads logic operation result.
Further, when carrying out setting 0 logical operation, by the second signal input terminal and the third signal
Input terminal applies forward voltage pulse simultaneously, and first signal input part is grounded, so that the resistance shape of resistance-variable storing device
State is changed into high-impedance state；Again by the way that the third signal input part to be grounded, and apply logic in first signal input part
Signal p applies logical signal q in the second signal input terminal to realize zero setting logical operation；When carrying out setting 1 logical operation
When, by applying forward voltage pulse simultaneously in first signal input part and the third signal input part, and will be described
Second signal input end grounding, so that the resistance states of resistance-variable storing device are low resistance state；Again by inputting the third signal
End ground connection, and apply logical signal p in first signal input part, apply logical signal q in the second signal input terminal
1 logical operation is set to realize；When carrying out setting p logical operation, by the second signal input terminal and the third signal
Input terminal applies forward voltage pulse simultaneously, and first signal input part is grounded, so that the resistance shape of resistance-variable storing device
State is changed into high-impedance state；Again by the way that first signal input part is applied logical signal p, the second signal input termination
Ground, the third signal input part apply forward voltage pulse, complete initialization resistance states and are the logical operation of p, then pass through
The third signal input part is grounded, and applies logical signal p in first signal input part, it is defeated in the second signal
Enter end application logical signal q and sets p logical operation to realize；When carrying out setting q logical operation, by being inputted in the second signal
End and the third signal input part apply forward voltage pulse simultaneously, and first signal input part is grounded, so that resistance
The resistance states of transition storage are changed into high-impedance state；Again by will first signal input part application logical signal q, described the
Binary signal input end grounding, the third signal input part apply forward voltage pulse, and completing initialization resistance states is patrolling for q
Operation is collected, then by the way that the third signal input part to be grounded, and apply logical signal p in first signal input part,
The second signal input terminal applies logical signal q and sets q logical operation to realize；When being setWhen logical operation, by
The second signal input terminal and the third signal input part apply forward voltage pulse simultaneously, and first signal is defeated
Enter end ground connection, so that the resistance states of resistance-variable storing device are changed into high-impedance state；Again by applying first signal input part
Logical signalThe second signal input end grounding, the third signal input part apply forward voltage pulse, complete initial
Changing resistance states isLogical operation, then by by the third signal input part be grounded, and first signal input
End applies logical signal p, applies logical signal q in the second signal input terminal and sets to realizeLogical operation；When being setWhen logical operation, by applying forward voltage arteries and veins simultaneously in the second signal input terminal and the third signal input part
Punching, and first signal input part is grounded, so that the resistance states of resistance-variable storing device are changed into high-impedance state；Again by by institute
It states the first signal input part and applies logical signalThe second signal input end grounding, the third signal input part apply just
To voltage pulse, completing initialization resistance states isLogical operation, then by by the third signal input part be grounded, and
Apply logical signal p in first signal input part, applies logical signal q in the second signal input terminal and set to realize
Logical operation.
Further, when carrying out logic or when p+q logical operation, by the second signal input terminal and described the
Three signal input parts apply forward voltage pulse simultaneously, and first signal input part is grounded, so that resistance-variable storing device
Resistance states are changed into high-impedance state；Again by the way that first signal input part is applied logical signal p, the second signal input
End ground connection, the third signal input part apply forward voltage pulse, complete the logical operation that initialization resistance states are p, then
By the way that the third signal input part is connect forward voltage pulse, and apply logical signal q in first signal input part,
The second signal input end grounding realizes logic or p+q logical operation；When carrying out, logical AND is non-When logical operation,
By applying forward voltage pulse simultaneously in first signal input part and the third signal input part, and by described second
Signal input part ground connection, so that the resistance states of resistance-variable storing device are low resistance state；Again by applying the third signal input part
Add logical signal p, and be grounded in first signal input part, applies logical signal q in the second signal input terminal and come in fact
Existing logical AND is non-Logical operation；When carrying out logical AND pq logical operation, by the second signal input terminal and
The third signal input part applies forward voltage pulse simultaneously, and first signal input part is grounded, so that resistive is deposited
The resistance states of reservoir are changed into high-impedance state；Again by the way that the third signal input part is applied logical signal p, and described the
One signal input part applies logical signal q, realizes logical AND pq logical operation in the second signal input end grounding；When
Carry out logic or non-When logical operation, by being applied simultaneously in the second signal input terminal and the third signal input part
Add forward voltage pulse, and first signal input part is grounded, so that the resistance states of resistance-variable storing device are changed into high resistant
State；Again by the way that first signal input part is applied logical signalThe second signal input end grounding, the third letter
Number input terminal applies forward voltage pulse, completes initialization resistance states and isLogical operation, then by the way that the third is believed
Number input terminal applies logical signal p, and applies logical signal q in first signal input part, inputs in the second signal
End applies forward voltage pulse and sets logic or non-to realizeLogical operation.
Further, when progress logicWhen logical operation, by first signal input part and described
Three signal input parts apply forward voltage pulse simultaneously, and by the second signal input end grounding, so that resistance-variable storing device
Resistance states are low resistance state；Again by the way that the third signal input part is connect forward voltage pulse, and it is defeated in first signal
Enter end and apply logical signal p, applies logical signal q in the second signal input terminal to realize logicLogical operation；When
Carry out logicWhen logical operation, by applying simultaneously in first signal input part and the third signal input part
Forward voltage pulse, and by the second signal input end grounding, so that the resistance states of resistance-variable storing device are low resistance state；Lead to again
It crosses and the third signal input part is applied into logical signal p, and apply logical signal q in first signal input part, in institute
It states second signal input terminal and applies forward voltage pulse to realize logicLogical operation；When progress logicLogic fortune
When calculation, by applying forward voltage pulse simultaneously in the second signal input terminal and the third signal input part, and by institute
The first signal input part ground connection is stated, so that the resistance states of resistance-variable storing device are changed into high-impedance state；Again by believing the third
Number input terminal applies forward voltage pulse, and applies logical signal q in first signal input part, defeated in the second signal
Enter end and applies logical signal p to realize logicLogical operation；When progress logicWhen logical operation, by described
Binary signal input terminal and the third signal input part apply forward voltage pulse simultaneously, and first signal input part is connect
Ground, so that the resistance states of resistance-variable storing device are changed into high-impedance state；Again by the way that the third signal input part is applied positive electricity
Pulse is pressed, and applies logical signal p in first signal input part, applies logical signal q in the second signal input terminal
To realize logicLogical operation.
Further, when progress logic exclusive orWhen logical operation, by the second signal input terminal
Apply forward voltage pulse simultaneously with the third signal input part, and first signal input part is grounded, so that resistive
The resistance states of memory are changed into high-impedance state；Again by will first signal input part application logical signal p, described second
Signal input part ground connection, the third signal input part apply forward voltage pulse, complete the logic that initialization resistance states are p
Operation, then by the way that the third signal input part is applied logical signal q, and apply logic letter in first signal input part
NumberApply logical signal p in the second signal input terminal to realize logic exclusive orLogical operation；Work as progress
Logic with orWhen logical operation, by the second signal input terminal and the third signal input part simultaneously
Apply forward voltage pulse, and first signal input part is grounded, so that the resistance states of resistance-variable storing device are changed into height
Resistance state；Again by the way that first signal input part is applied logical signalThe second signal input end grounding, the third
Signal input part applies forward voltage pulse, completes initialization resistance states and isLogical operation, then by by the third
Signal input part applies logical signal p, and applies logical signal q in first signal input part, defeated in the second signal
Enter end and applies logical signalCome realize set logic with orLogical operation.
Contemplated above technical scheme through the invention, compared with prior art, due to that can be realized in individual devices
Calculate and merged with storage, and can realize 16 kinds of all two-value boolean calculations in three steps, can obtain structure simply,
Perfect in shape and function, low in energy consumption, operating method be easy and the beneficial effects such as good compatibility.
Detailed description of the invention
Fig. 1 is 1T1R device architecture schematic diagram provided in an embodiment of the present invention.
(a) is the extrinsic motivated provided in an embodiment of the present invention based on the 1T1R device provided in Fig. 1 embodiment in Fig. 2
Connection type；(b) be the 1T1R device provided in Fig. 1 embodiment equivalent circuit diagram.
Fig. 3 be it is provided in an embodiment of the present invention based on 1T1R device equivalent circuit diagram in Fig. 2 (b) embodiment outside plus logic
Device resistance state change under signal function.
Fig. 4 is logical operation process of the embodiment of the present invention based on Fig. 2 embodiment 1T1R device equivalent logic computing circuit
Figure
Fig. 5 is the NAND logic behaviour that the embodiment of the present invention is provided based on Fig. 2 embodiment 1T1R device schematic equivalent circuit
Make flow chart.
Fig. 6 is provided in an embodiment of the present invention based on the corresponding result exhibition of NAND logic operating method specific steps in Fig. 4
Show.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
For the development and urgent need of novel computer framework, the purpose of the present invention is to provide one kind to be based on
1T1R device architecture, can realize non-volatile logic operation simultaneously and information storage logical device and its logical operation side
Method realizes the perfect set of two-value Boolean logic, has that structure simple, perfect in shape and function, low in energy consumption, operating method is easy and compatible
The features such as property is good.
Contemplated above technical scheme through the invention due to that can simplify logic circuit, overcomes compared with prior art
The bottleneck that existing logical operation circuit is encountered at integrated aspect, efficiently uses the regulation of grid voltage, reduce logical operation when
Between complexity, in individual devices realize Boolean logic perfect set, can also realize in individual devices store with calculating merge,
And then the Feng Luoyiman bottleneck of active computer is broken through, so going to realize that logical operation is one and has very much developing using 1T1R device
The research direction and great development prospect of property.
To achieve the above object, according to one aspect of the present invention, a kind of logic based on 1T1R device architecture is provided
Circuit, wherein RRAM is made of resistive functional layer material and electrode material with resistance states conversion characteristic, the resistance of material
State can be by dynamic excitation signal come reversible regulation.
There are two types of non-volatile physical state, high-impedance state High Resistance for 1T1R device tool provided by the invention
(H) and low resistance state Low Resistance (L), resistance states can be not only used for the storage of information, can also be in the present invention
Logical operation is realized as logical signal.For this feature of 1T1R device, the invention proposes one kind based on single
The logical operation method of 1T1R device architecture is powered on pulse and carries out logical operation as embodiment input signal, in addition with device
The result of the final resistance states physical quantity characterization logic operation of part.This operation result can be stored in device in nonvolatile manner
In resistance states, (it can generally be incited somebody to action in the read signal of 0.2V or less) by low current (generally in na level) or small voltage
It reads, and can be wiped by applying the electric pulse of certain amplitude and pulsewidth it.
In addition, end voltage is written using the initial resistivity state of 1T1R device, grid voltage and device two rationally
Regulation, the present invention realize the NAND logic operation in Boolean logic.The present invention assigns 1T1R device respectively on this basis
Initial resistivity state, the grid voltage logical signal different from device two write-in end voltage, and then realize all 16 kinds
Boolean calculation.The present invention can promote the development of non-volatile logic device, for the Feng Luoyi for breaking through active computer
The limitation of graceful bottleneck and electronic device Moore's Law lays the foundation.
The present invention is based on 1T1R device propose a kind of logical operation circuit for realizing all 16 kinds of boolean calculations and
Operating method, operation result are stored in the devices with resistance states, are deposited to realize and carry out information simultaneously in logical device
The effect of storage.1T1R device disclosed by the invention is expected to be used for constructing the novel parallel meter of next-generation information storage and processing fusion
Body system structure is calculated, is broken through in convention computer architecture as caused by information storage and processing separation " von Neumann bottleneck "
Problem and the time complexity for reducing logical operation, realize Boolean logic perfect set in individual devices.It is disclosed by the invention
Logical device can be applied to New Solid memory, logical-arithmetic unit, programmable gate array and on piece system as basic unit
The fields such as system.
For the growth requirement of the prior art, it is non-easy based on 1T1R device architecture that the purpose of the present invention is to provide a kind of
The property lost logical operation circuit and its logical operation method are, it can be achieved that 16 kinds of boolean calculations, it is intended to improve standing state logic
The function of the problem of being encountered in terms of industrialization is integrated and the storage and processing fusion for realizing information.
Compared with prior art, the present invention can change and can occur non-based on resistance states possessed by 1T1R device
The characteristic of volatibility variation, can realize 16 kinds of boolean calculations, operation result is with device resistance state in individual devices
It is stored among device, is achieved in the effect of the storage and processing fusion of the information in logical device.This device is expected to use
In the novel computer architectural framework for constructing next-generation information storage and processing fusion, breaks through information in convention computer architecture and deposit
" the von Neumann bottleneck " of storage and processing separation, pushes the development of novel parallel computer.
Referring now to the attached drawing for showing exemplary embodiment of the invention, the present invention is described more fully with.However, it is possible to
Implement the present invention with many different forms, and the present invention should not be construed the embodiment for being limited to list here；More really
It says with cutting, theses embodiments are provided so that the disclosure is more thorough and comprehensive, and fully communicate to those skilled in the art
Idea of the invention.
In the present invention, at least have two resistance states: high-impedance state as the 1T1R device of logical operation circuit core
High Resistance (H) and low resistance state Low Resistance (L), the effect that resistance states can be motivated in external signal
It is lower that reversible resistance states transformation, such as electric impulse signal occurs.In the case where there is grid voltage, terminated in 1T1R device source
Ground, the positive electric pulse of another termination, can make device resistance state change to low resistance state Low from high-impedance state High Resistance (H)
Resistance(L)；Positive electric pulse is terminated in 1T1R device source, other end ground connection can make device resistance state from low-resistance
State Low Resistance (L) changes to high-impedance state High Resistance (H).The non-volatile resistance states of device have high resistant
State High Resistance (H) and low resistance state Low Resistance (L), both resistance states can be used for depositing for information
Storage and processing.
Fig. 1 is 1T1R device multilayer lamination structure figure provided in an embodiment of the present invention.As shown in fig. 1, transistor arrangement
Preparation is that source material 103 and drain terminal material 104 are deposited on base material 105 first, is then sunk between source and drain terminal
Product insulating layer 102, depositing gate electrode 101 on the insulating layer, material is thus formed the Transistor structure in 1T1R structure,
RRAM is also multilayer lamination structure, and by top electrode 106, lower electrode 108 and resistive functional layer material 107 are constituted, by institute in Fig. 1
Show and successively stacked in transistor drain terminal, shown in Fig. 1 embodiment be Transistor and RRAM combination and
At 1T1R structure can be other stacked structures, can be but the invention is not limited to this simple multilayer lamination structure
Other Nonvolatile resistance variation devices, as long as having non-volatile resistor change characteristic.
Fig. 2 (a) is the company of the extrinsic motivated provided in an embodiment of the present invention based on the 1T1R device provided in Fig. 1 embodiment
Connect mode.During the Set of RRAM, the gate terminal 20 of 1T1R device connects forward voltage, the top electrode exit of RRAM
21 connect positive electric pulse, and transistor source exit 22 connects zero level pulse, and 1T1R substrate exit 30 connects zero level pulse.?
During the Reset of RRAM, the gate terminal 20 of 1T1R device connects forward voltage, and the top electrode exit 21 of RRAM connects zero electricity
Flat pulse, transistor source exit 22 connect positive electric pulse, and 1T1R substrate exit 30 connects zero level pulse.And when grid draws
It, all will not be to the resistance states of RRAM no matter how exit 21 and exit 22 connect voltage when outlet 20 connects zero level pulse
It has an impact.Fig. 2 (b) is the equivalent logic computing circuit that the 1T1R device that provides in Fig. 1 embodiment is constituted, in dotted line frame 203
Element correspond to transistor arrangement, the element in dotted line frame 204 corresponds to resistance-variable storing device RRAM structure, third signal input part
202 correspond to the gate terminal of 1T1R device, and the first signal input part 200 corresponds to resistance-variable storing device RRAM in 1T1R device
Top electrode exit, second signal input terminal 201 correspond to 1T1R device in source exit.Similarly, in the Set of RRAM
In the process, third signal input part 202 connects forward voltage pulse, and the first signal input part 200 connects forward voltage pulse, the second letter
Number input terminal 201 connects zero level pulse；During the Reset of RRAM, third signal input part 202 connects forward voltage, and first
Signal input part 200 connects zero level pulse, and second signal input terminal 201 connects positive electric pulse, when third signal input part 202 connects
When zero level pulse, no matter 200 He of the first signal input part, how second signal input terminal 201, which connects electric pulse, will not all make
RRAM resistance states change.The electric pulse provided in embodiment is the voltage in 1T1R normal range of operation, can be made
1T1R proper device operation will not generate destructive effect to device again, and subsequent logic operates to mention in Fig. 2 (b) embodiment
The equivalent circuit diagram of confession is shown.
Invention defines 4 logical signals: the corresponding logical signal I of the initialization resistance states of device, defines high resistant
State High resistance is logical signal I=0, and low resistance state Low resistance is logical signal I=1；Third signal is defeated
Enter the voltage signal G at end 202, it is to patrol to grid forward voltage pulse that definition, which is logical signal G=0 to grid zero level voltage,
Collect signal G=1；The electric signal T of first signal input part 2001, definition is to patrol to the 200 zero level pulse of the first signal input part
Collect signal T1=0, it is logical signal T to the 200 forward voltage pulse of the first signal input part1=1；Second signal input terminal 201
Electric signal T2, definition is logical signal T to the 201 zero level pulse of second signal input terminal2=0, give second signal input terminal 201
Forward voltage pulse is logical signal T2=1.The result of last logical operation is stored among 1T1R device, is defined as resistance shape
Also there are two types of possibility, definition high-impedance state High resistance is logical zero, low-resistance by state R, the 1T1R device resistance state R of reading
State Low resistance is logic 1.Specific logical signal definition is as shown in Table 1.
Table one
| Logical signal definition | 0 | 1 |
| Device initializes resistance states I | High Resistance(H) | Low Resistance(L) |
| Grid electric signal G | Zero level pulse | Forward voltage pulse |
| 200 electric signal T of port1 | Zero level pulse | Forward voltage pulse |
| 201 electric signal T of port2 | Zero level pulse | Forward voltage pulse |
| Read resistance states R | High Resistance(H) | Low Resistance(L) |
On the basis of 4 logical signals that the present invention defines, the expression of our the available final resistance states R of device
Formula, as shown in formula (1).
Fig. 3 be it is provided in an embodiment of the present invention based on 1T1R device equivalent logic circuitry in Fig. 2 (b) embodiment outer plus patrol
Collect the device resistance state change under signal function.Logical signal 0 and logical signal 1 logic as defined in table one respectively in figure
Signal, the electric signal that third signal input part 202 connects are gate voltage signal G, the electric signal that the first signal input part 200 connects
As electric signal T1, the electric signal that second signal input terminal 201 connects is electric signal T2.Device resistance state H represents high-impedance state
High Resistance, device resistance state L represent low resistance state Low Resistance.From Fig. 3 we can see that
Three signal input parts 202 connect forward voltage pulse, and second signal input terminal 201 connects zero level, and the first signal input part 200 connects just
To voltage pulse, it can make 1T1R device that Set process occur in this way, change to low resistance state L from high-impedance state H；If in third signal
Input terminal 202 connects forward voltage pulse, and second signal input terminal 201 connects forward voltage pulse, the first signal input part 200 connects
Zero level pulse can make 1T1R device that Reset process occur, change to high-impedance state H from low resistance state L.In figure Set process with
The electric pulse size used during Reset may difference, this is determined by the operating point of device itself, in the normal work of device
It is to guarantee its one of key condition as logical device that suitable positive electric pulse is chosen under the conditions of work as logical signal, this
The logical signal and electric signal used in inventive embodiments can make 1T1R device steady operation.
Fig. 4 is logical operation process of the embodiment of the present invention based on Fig. 2 embodiment 1T1R device equivalent logic computing circuit
Figure (Correspond to Correspond to)。
Steps are as follows for specific logical operation:
(1) RRAM resistance states in 1T1R device are initialized.When initializing signal I is inputted not as logical signal, only
It needs by first signal input part 200 and the third signal input part 202 while applying forward voltage pulse, and
The second signal input terminal 201 is grounded, so that the resistance states of resistance-variable storing device are low resistance state or by described the
Binary signal input terminal 201 and the third signal input part 202 apply forward voltage pulse simultaneously, and first signal is defeated
Enter 200 ground connection of end, so that the resistance states of resistance-variable storing device are high-impedance state；When initializing signal I is inputted as logical signal,
It needs to first pass through in the second signal input terminal 201 and the third signal input part 202 while applying forward voltage pulse,
And be grounded first signal input part 200, so that the resistance states of resistance-variable storing device are high-impedance state；Then again by by institute
State the first signal input part 200 apply logical signal p, q,OrThe second signal input terminal 201 is grounded, the third letter
Number input terminal 202 applies forward voltage pulse, complete initialization resistance states be p, q,OrLogical operation；
(2) input logic signal.Corresponding logical signal, the first signal input part are inputted in corresponding signal input part
200, second signal input terminal 201, third signal input part 202 can be used as logic signal input end input 0,1, p, q,
OrLogical signal；
(3) logic operation result is read.Forward voltage is added in third signal input part 202, in second signal input terminal
201 ground connection, connect small reading voltage in the first signal input part 200, this voltage will not make RRAM resistance states change, root
The resistance states of 1T1R device can be accurately read according to electric current is read, this step can be omitted in real work.
The present invention is by assigning 1T1R device 4 logical signals (I, G, T1、T2) Different Logic signal realizes all 16
Kind boolean calculation, logical operation and signal assignment are as shown in Table 2.
Table two
Fig. 5 is that the embodiment of the present invention is provided based on Fig. 2 embodiment 1T1R device equivalent logic computing circuit schematic diagram
NAND logic operational flowchart.Using the equivalent circuit diagram provided in Fig. 2 embodiment, specific logical operational steps in the present embodiment
It is as follows:
(1) device resistance is initialized, is low resistance state L by 1T1R device resistance state initialization, even I=1.It can be
Three signal input parts 202 plus forward voltage pulse, second signal input terminal 201 connect zero level and connect zero level pulse, the first signal
Input terminal 200 connects forward voltage pulse, and 1T1R device can be thus initialized as to low resistance state L.
(2) input logic signal p and logical signal q.It is logic that we, which define 202 voltage signal G of third signal input part,
Signal p defines the electric signal T of second signal input terminal 2012For variable q, and the first signal input part 200 is connect into zero level arteries and veins
Punching, even G=p, T1=0, T2=q, according to formula (1), we are availableIt is patrolled it is possible thereby to complete NAND
Operation is collected, logic operation result is stored among 1T1R device in the form of resistance states.
(3) reading device resistance states.Forward voltage is added in third signal input part 202, in second signal input terminal
201 ground connection, connect small reading voltage in the first signal input part 200, this voltage will not make RRAM resistance states change, root
The resistance states of 1T1R device can be accurately read according to electric current is read.The present embodiment only shows one of reading manner, also
There are other reading manners also within that scope of the present invention.Table three is that NAND logic operates truth table and logical signal application side
Formula.
Table three
Fig. 6 is provided in an embodiment of the present invention based on the corresponding result exhibition of NAND logic operating method specific steps in Fig. 4
Show.1T1R device resistance state initialization is low resistance state L, i.e. I=1 by the first step；Second step input logic signal p and logic letter
Number q, the first signal input part 200 are grounded always, input simultaneously in third signal input part 202 and second signal input terminal 201
Logical signal p and logical signal q, only when third signal input part 202 and second signal input terminal 201 input positive electricity simultaneously
When pressure pulse signal, device resistance state can just change to high-impedance state H from low resistance state L, and the result of logical operation is protected with resistance states
There are among device, logic operation result can be read with small reading voltage, it is possible thereby to complete NAND logic operation.
4 logical signals (I, G, T are given respectively according to formula (1)1、T2) assign different logical signal and may be implemented to own
16 kinds of boolean calculations, logical operational steps can complete in three steps, reduce logical operation time complexity.First
Step: initialization device resistance assigns device different initialization resistance states according to logical signal p and logical signal q；Second
Step: input logic signal p and logical signal q distinguishes input logic signal p and logical signal q according to the definition of logical signal；The
Three steps, reading device resistance states can use small voltage reading device resistance states, and concrete operations and NAND logic operate class
Seemingly.
The stabilization occurred based on 1T1R with applying pulse voltage is realized in the logical operation of logical device in the embodiment of the present invention
Reversible electric resistance changing, operation result directly non-volatile can be stored with device resistance state in the devices, to have
It is calculated and stored in the characteristics of merging in individual unit.But the present invention is not limited to this, as long as the device can show class
The characteristic for being similar to pulse resistance transformation can use logical calculation method provided by the invention.In addition, patrolling of passing through of the present invention
Collecting computing circuit and logical calculation method actually can complete all logical operations in two steps, and greatly simplifie logic electricity
The design on road reduces the complexity of integrated technique.Finally, logical operation circuit proposed by the present invention will with logical calculation method
Research foundation is provided for subsequent logic circuit design, is greatly promoted the design and application of non-volatile logic device.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include
Within protection scope of the present invention.
Claims (5)
1. a kind of operating method of logic-based computing circuit, the logic circuit includes: transistor and resistance-variable storing device, described
First signal input part (200) of the one end of resistance-variable storing device as the logical operation circuit, the resistance-variable storing device it is another
One end is connect with the drain electrode of the transistor, and the source electrode of the transistor is inputted as the second signal of the logical operation circuit
It holds (201), third signal input part (202) of the grid of the transistor as the logical operation circuit；By described
First signal input part (200), second signal input terminal (201) and third signal input part (202) input different arteries and veins simultaneously
Signal is rushed, so that the resistance states of the resistance-variable storing device change, to realize logical operation；It is characterized in that, described
Operating method includes the following steps:
(1) initialization process is carried out to the resistance states of the resistance-variable storing device, and defines the high-impedance state of the resistance-variable storing device
Corresponding logical signal I is " 0 ", and the corresponding logical signal I of the low resistance state of resistance-variable storing device is " 1 "；Wherein, I is the resistive
The corresponding logical signal of initialization resistance states of memory；
(2) defeated in first signal input part (200), the second signal input terminal (201) and the third signal simultaneously
Enter end (202) input voltage pulse signal；
The corresponding logical signal T when the first signal input part (200) receive zero level pulse1For " 0 ", when the first signal is defeated
Enter end (200) and receives logical signal T corresponding when forward voltage pulse1For " 1 "；
The corresponding logical signal T when second signal input terminal (201) receive zero level pulse2For " 0 ", when second signal is defeated
Enter end (201) and receives logical signal T corresponding when forward voltage pulse2For " 1 "；
When third signal input part (202) receive zero level pulse, corresponding logical signal G is " 0 ", when third signal is defeated
Entering end (202) to receive logical signal G corresponding when forward voltage pulse is " 1 "；
(3) according to formulaIt carries out logical operation and reads logic operation result；Wherein,
T1Apply the corresponding logical signal of pulse signal, T for the first signal input part (200)2For second signal input terminal (201) application
The corresponding logical signal of pulse signal, G are that third signal input part (202) apply the corresponding logical signal of pulse signal.
2. operating method as described in claim 1, which is characterized in that when carrying out setting 0 logical operation, by described second
Signal input part (201) and the third signal input part (202) apply forward voltage pulse simultaneously, and by first signal
Input terminal (200) ground connection, so that the resistance states of resistance-variable storing device are changed into high-impedance state；Again by inputting the third signal
(202) ground connection is held, and applies logical signal p in first signal input part (200), in the second signal input terminal
(201) apply logical signal q to realize zero setting logical operation；
When carrying out setting 1 logical operation, by first signal input part (200) and the third signal input part
(202) apply forward voltage pulse simultaneously, and the second signal input terminal (201) is grounded, so that the electricity of resistance-variable storing device
Resistance state is low resistance state；Again by the way that the third signal input part (202) to be grounded, and in first signal input part
(200) apply logical signal p, apply logical signal q in the second signal input terminal (201) and set 1 logical operation to realize；
When carrying out setting p logical operation, by the second signal input terminal (201) and the third signal input part
(202) apply forward voltage pulse simultaneously, and first signal input part (200) is grounded, so that the electricity of resistance-variable storing device
Resistance state is changed into high-impedance state；Again by the way that first signal input part (200) is applied logical signal p, the second signal
Input terminal (201) ground connection, the third signal input part (202) apply forward voltage pulse, and completing initialization resistance states is p
Logical operation, then by the way that the third signal input part (202) to be grounded, and applied in first signal input part (200)
Add logical signal p, applies logical signal q in the second signal input terminal (201) and set p logical operation to realize；
When carrying out setting q logical operation, by the second signal input terminal (201) and the third signal input part
(202) apply forward voltage pulse simultaneously, and first signal input part (200) is grounded, so that the electricity of resistance-variable storing device
Resistance state is changed into high-impedance state；Again by the way that first signal input part (200) is applied logical signal q, the second signal
Input terminal (201) ground connection, the third signal input part (202) apply forward voltage pulse, and completing initialization resistance states is q
Logical operation, then by the way that the third signal input part (202) to be grounded, and applied in first signal input part (200)
Add logical signal p, applies logical signal q in the second signal input terminal (201) and set q logical operation to realize；
When being setWhen logical operation, by the second signal input terminal (201) and the third signal input part
(202) apply forward voltage pulse simultaneously, and first signal input part (200) is grounded, so that the electricity of resistance-variable storing device
Resistance state is changed into high-impedance state；Again by the way that first signal input part (200) is applied logical signalThe second signal
Input terminal (201) ground connection, the third signal input part (202) apply forward voltage pulse, complete initialization resistance states and areLogical operation, then by the way that the third signal input part (202) to be grounded, and in first signal input part (200)
Apply logical signal p, applies logical signal q in the second signal input terminal (201) and set to realizeLogical operation；
When being setWhen logical operation, by the second signal input terminal (201) and the third signal input part
(202) apply forward voltage pulse simultaneously, and first signal input part (200) is grounded, so that the electricity of resistance-variable storing device
Resistance state is changed into high-impedance state；Again by the way that first signal input part (200) is applied logical signalThe second signal
Input terminal (201) ground connection, the third signal input part (202) apply forward voltage pulse, complete initialization resistance states and are
Logical operation, then by the way that the third signal input part (202) to be grounded, and applied in first signal input part (200)
Add logical signal p, applies logical signal q in the second signal input terminal (201) and set to realizeLogical operation.
3. operating method as described in claim 1, which is characterized in that
When carrying out logic or p+q logical operation, by the second signal input terminal (201) and third signal input
End (202) applies forward voltage pulse simultaneously, and first signal input part (200) is grounded, so that resistance-variable storing device
Resistance states are changed into high-impedance state；Again by the way that first signal input part (200) is applied logical signal p, second letter
Number input terminal (201) ground connection, the third signal input part (202) apply forward voltage pulse, complete initialization resistance states
For the logical operation of p, then by the way that the third signal input part (202) is connect forward voltage pulse, and in first signal
Input terminal (200) applies logical signal q, is grounded in the second signal input terminal (201) to realize logic or p+q logic fortune
It calculates；
When carrying out, logical AND is non-When logical operation, by first signal input part (200) and the third signal
Input terminal (202) applies forward voltage pulse simultaneously, and the second signal input terminal (201) is grounded, so that resistance-change memory
The resistance states of device are low resistance state；Again by the way that the third signal input part (202) is applied logical signal p, and described the
One signal input part (200) ground connection applies logical signal q in the second signal input terminal (201) to realize that logical AND is non-Logical operation；
When carrying out logical AND pq logical operation, by defeated in the second signal input terminal (201) and the third signal
Enter end (202) while applying forward voltage pulse, and first signal input part (200) is grounded, so that resistance-variable storing device
Resistance states be changed into high-impedance state；Again by the way that the third signal input part (202) is applied logical signal p, and described
First signal input part (200) applies logical signal q, is grounded in the second signal input terminal (201) to realize logical AND p
Q logical operation；
When carrying out logic or non-When logical operation, by defeated in the second signal input terminal (201) and the third signal
Enter end (202) while applying forward voltage pulse, and first signal input part (200) is grounded, so that resistance-variable storing device
Resistance states be changed into high-impedance state；Again by the way that first signal input part (200) is applied logical signalDescribed second
Signal input part (201) ground connection, the third signal input part (202) apply forward voltage pulse, complete initialization resistance shape
State isLogical operation, then by the way that the third signal input part (202) is applied logical signal p, and in first signal
Input terminal (200) applies logical signal q, applies forward voltage pulse in the second signal input terminal (201) and patrols to realize to set
It collects or non-Logical operation.
4. operating method as described in claim 1, which is characterized in that
When progress logicWhen logical operation, by first signal input part (200) and third signal input
End (202) applies forward voltage pulse simultaneously, and the second signal input terminal (201) is grounded, so that resistance-variable storing device
Resistance states are low resistance state；Again by the way that the third signal input part (202) is connect forward voltage pulse, and in first letter
Number input terminal (200) applies logical signal p, applies logical signal q in the second signal input terminal (201) to realize logicLogical operation；
When progress logicWhen logical operation, by first signal input part (200) and third signal input
End (202) applies forward voltage pulse simultaneously, and the second signal input terminal (201) is grounded, so that resistance-variable storing device
Resistance states are low resistance state；Again by the way that the third signal input part (202) is applied logical signal p, and in first letter
Number input terminal (200) applies logical signal q, applies forward voltage pulse in the second signal input terminal (201) and patrols to realize
VolumeLogical operation；
When progress logicWhen logical operation, by the second signal input terminal (201) and the third signal input part
(202) apply forward voltage pulse simultaneously, and first signal input part (200) is grounded, so that the electricity of resistance-variable storing device
Resistance state is changed into high-impedance state；Again by the way that the third signal input part (202) is applied forward voltage pulse, and described the
One signal input part (200) applies logical signal q, applies logical signal p in the second signal input terminal (201) and patrols to realize
VolumeLogical operation；
When progress logicWhen logical operation, by the second signal input terminal (201) and the third signal input part
(202) apply forward voltage pulse simultaneously, and first signal input part (200) is grounded, so that the electricity of resistance-variable storing device
Resistance state is changed into high-impedance state；Again by the way that the third signal input part (202) is applied forward voltage pulse, and described the
One signal input part (200) applies logical signal p, applies logical signal q in the second signal input terminal (201) and patrols to realize
VolumeLogical operation.
5. operating method as described in claim 1, which is characterized in that
When progress logic exclusive orWhen logical operation, by the second signal input terminal (201) and the third
Signal input part (202) applies forward voltage pulse simultaneously, and first signal input part (200) is grounded, so that resistive
The resistance states of memory are changed into high-impedance state；Again by the way that first signal input part (200) is applied logical signal p, institute
Second signal input terminal (201) ground connection is stated, the third signal input part (202) applies forward voltage pulse, completes initialization
Resistance states are the logical operation of p, then by the way that the third signal input part (202) is applied logical signal q, and described the
One signal input part (200) applies logical signalApply logical signal p in the second signal input terminal (201) to realize
Logic exclusive orLogical operation；
When carry out logic with orWhen logical operation, by the second signal input terminal (201) and the third
Signal input part (202) applies forward voltage pulse simultaneously, and first signal input part (200) is grounded, so that resistive
The resistance states of memory are changed into high-impedance state；Again by the way that first signal input part (200) is applied logical signalInstitute
Second signal input terminal (201) ground connection is stated, the third signal input part (202) applies forward voltage pulse, completes initialization
Resistance states areLogical operation, then by the way that the third signal input part (202) is applied logical signal p, and described the
One signal input part (200) applies logical signal q, applies logical signal in the second signal input terminal (201)It is set to realize
Logic with orLogical operation.
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| CN108092658B (en) * | 2017-12-12 | 2020-05-19 | 华中科技大学 | Logic circuit operation method |
| CN108111162B (en) * | 2017-12-17 | 2020-12-08 | 华中科技大学 | Operation circuit and operation method |
| CN109388853B (en) * | 2018-09-07 | 2023-03-24 | 北京大学 | Single-pole and double-pole mixed efficient memristor logic circuit and control method thereof |
| CN109660250B (en) * | 2018-12-03 | 2023-03-24 | 北京大学深圳研究生院 | Multi-state gate based on resistive random access memory |
| CN109994139B (en) * | 2019-03-15 | 2020-11-03 | 北京大学 | Complete non-volatile logic implementation method based on unipolar memristor and application thereof |
| CN110390074B (en) * | 2019-07-01 | 2021-04-20 | 浙江大学 | Computing system of resistance type memory |
| CN110445489B (en) * | 2019-07-24 | 2020-12-18 | 华中科技大学 | Digital comparison circuit and operation method thereof |
| CN110827898B (en) * | 2019-10-21 | 2021-07-27 | 华中科技大学 | Voltage-resistance type reversible logic circuit based on memristor and operation method thereof |
| CN112015367B (en) * | 2020-08-26 | 2024-05-31 | 上海新氦类脑智能科技有限公司 | Nonvolatile Boolean logic operation unit, method and device |
| CN112543022A (en) * | 2021-01-26 | 2021-03-23 | 兰州大学 | Basic logic operation unit circuit |
| CN113380298A (en) * | 2021-05-07 | 2021-09-10 | 中国科学院上海微系统与信息技术研究所 | Nonvolatile Boolean logic two-bit multiplier and operation method |
| CN113380296A (en) * | 2021-05-07 | 2021-09-10 | 中国科学院上海微系统与信息技术研究所 | Image processing device and method of Boolean logic of phase change memory cell |
| CN113643741B (en) * | 2021-08-16 | 2023-12-15 | 湖北大学 | 1S 1R-based logic operation unit and operation method |
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