CN113380298A - Nonvolatile Boolean logic two-bit multiplier and operation method - Google Patents
Nonvolatile Boolean logic two-bit multiplier and operation method Download PDFInfo
- Publication number
- CN113380298A CN113380298A CN202110494509.6A CN202110494509A CN113380298A CN 113380298 A CN113380298 A CN 113380298A CN 202110494509 A CN202110494509 A CN 202110494509A CN 113380298 A CN113380298 A CN 113380298A
- Authority
- CN
- China
- Prior art keywords
- resistance
- resistance state
- logic
- input
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000004364 calculation method Methods 0.000 claims abstract description 56
- 230000002093 peripheral effect Effects 0.000 claims abstract description 14
- 230000015654 memory Effects 0.000 claims description 58
- 230000008859 change Effects 0.000 description 58
- 238000010586 diagram Methods 0.000 description 6
- 238000011160 research Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 238000013528 artificial neural network Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- -1 chalcogenide compounds Chemical class 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
Abstract
本发明涉及一种非易失布尔逻辑两位乘法器及运算方法，乘法器包括四个多阻态器件、选通器件和外围控制电路，多阻态器件的一端作为顶端电极输入端，另一端与选通器件的漏端相连，选通器件的栅端作为多阻态器件的字线，源端连接底端电极输入端；多阻态器件用于实现非易失布尔逻辑运算，并将运算结果直接以多阻态器件的阻值状态进行存储；选通器件用于选通四个多阻态器件中的任意一个实现逻辑运算；外围控制电路，用于向选通的多阻态器件施加操作信号以使得多阻态器件实现逻辑操作，并在进行下一步逻辑操作之前进行状态级联使得前一步的计算结果作为下一步的逻辑输入存储在所述多阻态器件中。本发明使用少量的器件快捷实现非易失乘法操作。
The invention relates to a non-volatile Boolean logic two-bit multiplier and an operation method. The multiplier includes four multi-resistance devices, a gating device and a peripheral control circuit. One end of the multi-resistance device is used as the top electrode input end, and the other end is used as the top electrode input end. It is connected to the drain terminal of the gating device, the gate terminal of the gating device is used as the word line of the multi-resistance state device, and the source end is connected to the bottom electrode input end; The result is directly stored in the resistance state of the multi-resistance state device; the gating device is used to select any one of the four multi-resistance state devices to realize the logic operation; the peripheral control circuit is used to apply to the gated multi-resistance state device. The signal is operated so that the multi-resistance state device realizes the logic operation, and the state cascade is performed before the next logic operation is performed, so that the calculation result of the previous step is stored in the multi-resistance state device as the next logic input. The present invention uses a small number of devices to quickly realize the non-volatile multiplication operation.
Description
Technical Field
The invention relates to the technical field of nonvolatile storage calculation, in particular to a nonvolatile Boolean logic two-bit multiplier and an operation method.
Background
At present, communication, computer and personal consumer electronics products are developed, and the explosive increase of data volume makes the demand of the market for memories larger and larger, and promotes the development and the revolution of storage technology. Therefore, it is a hot spot of research to realize memories with higher speed, larger capacity, higher integration, stronger reliability and lower power consumption. Phase change memory is a new type of nonvolatile memory, and the research result that chalcogenide compounds can be reversibly transformed between high-resistance amorphous state and low-resistance polycrystalline state under the action of an electric field was published by Stanford r. In the artificial intelligence era, phase change memories play an important role in various fields, such as nonvolatile memories, neural network accelerators, boolean logic calculations, and the like.
With the continuous development of moore's law, the framework of von neumann framework calculation and storage separation hinders the further improvement of computational efficiency, in order to solve the bottleneck of storage wall and power consumption, combines calculation and storage, and the utilization of novel nonvolatile phase change memory to realize nonvolatile Boolean logic calculation in the in-memory calculation has wide research prospect. The existing nonvolatile logic calculation is mainly divided into two types, one type is state logic, input and output signals are represented by device resistance values, and cascaded signal conversion among devices is not needed; the other type is non-state logic, with the inputs typically represented by voltage signals and the results of the calculations stored as resistance values. In both non-volatile boolean logic operations, the result of the computation is stored directly in the form of a resistance value in the phase change memory computation cell.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a nonvolatile Boolean logic multiplier and an operation method, and the nonvolatile multiplication operation is quickly realized by using a small number of devices.
The technical scheme adopted by the invention for solving the technical problems is as follows: the non-volatile Boolean logic two-bit multiplier comprises four multi-resistance state devices, a gating device and a peripheral control circuit, wherein one end of each multi-resistance state device is used as a top electrode input end, the other end of each multi-resistance state device is connected with a drain end of the gating device, a gate end of the gating device is used as a word line of the multi-resistance state device, and a source end of the gating device is connected with a bottom electrode input end; the multi-resistance state device is used for realizing nonvolatile Boolean logic operation and directly storing an operation result in a resistance state of the multi-resistance state device; the gating device is used for gating any one of the four multi-resistance state devices to realize logic operation; the peripheral control circuit is used for applying an operation signal to the gated multi-resistance state device, enabling the operation signal and the resistance state of the multi-resistance state device to be used as input to realize logic operation, and carrying out state cascade before carrying out next logic operation so that a calculation result of the previous step is used as logic input of the next step and is stored in the multi-resistance state device.
After the multi-resistance state device applies an input pulse signal, the resistance state of the multi-resistance state device is subjected to threshold value overturning.
When an input pulse signal applied by the multi-resistance state device is a RESET input pulse, the multi-resistance state device is converted into a high-resistance state, and a calculation result corresponds to binary logic '0'; when the input pulse signal applied by the multi-resistance state device is an SET input pulse, the multi-resistance state device is converted into a low-resistance state, and the calculation result corresponds to binary logic '1'.
When the logic operation is initialization logic operation, the peripheral control circuit inputs a RESET input pulse to the four multi-resistance state devices, so that the four multi-resistance state devices are all in a high-resistance state.
When the logic operation is an AND logic operation, the peripheral control circuit converts a multiplicand into a pulse signal and applies the pulse signal to the input end of the top electrode, the multiplicand is stored in the multi-resistance state device in the form of the resistance state of the multi-resistance state device, and the output result is stored in the resistance state of the multi-resistance state device.
When the logic operation is an exclusive-or logic operation, the peripheral control circuit applies a logically input binary signal to the top electrode input terminal, reads out an initial state of the multi-resistance state device, and determines whether an input operation is a RESET operation or a SET operation based on the initial state.
The multi-resistance state device is a phase change memory unit.
The technical scheme adopted by the invention for solving the technical problems is as follows: the four multi-resistance state devices are marked as a multi-resistance state device C11Multi-resistance state device C12Multi-resistance state device C21And a multi-resistance state device C22The method comprises the following steps:
(1) for the multi-resistance state device C11Multi-resistance state device C12Multi-resistance state device C21And a multi-resistance state device C22Performing initialization operation, and respectively performing multiple resistance state devices C after the initialization operation is completed11Multi-resistance state device C12Multi-resistance state device C21And a multi-resistance state device C22In the middle of writing A0B0、A0B1、A1B1And A1B0；
(2) In the multi-resistance state device C11Performing a one-bit AND logic operation to obtain A0B0A1And reading out the multi-resistance state device C12And a multi-resistance state device C22Storing the result;
(3) in the multi-resistance state device C11Performing a one-bit AND logic operation to obtain A0B0A1B1The result read out in the step (2) is in a multi-resistance stateDevice C12Is subjected to XOR operation to obtain
(4) Readout multi-resistance state device C11The calculation result A in (1)0A1B0B1And in the multi-resistance state device C22Write in A0B0；
(5) In the multi-resistance state device C21Implementing an XOR operation to obtain
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention utilizes the characteristics of phase change storage threshold value conversion and nonvolatile storage to construct a phase change storage nonvolatile Boolean logic calculation two-bit multiplier, compared with the traditional logic calculation to realize two-bit multiplication operation, the nonvolatile Boolean logic realization method is beneficial to reducing power consumption and time consumption caused by frequent data transmission, realizing logic operation in a storage array and reducing energy consumption.
Drawings
FIG. 1 is a schematic diagram of a phase change memory cell 1T 1R;
FIG. 2 is a schematic diagram of an AND (AND) logic truth table;
FIG. 3 is a schematic diagram of a 2-bit multiplication calculation;
FIG. 4 is a schematic diagram of a logic operation device unit and operation steps;
FIG. 5 is a schematic diagram of the simulated input and output of the two-bit multiplier.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The embodiment of the invention relates to a nonvolatile Boolean logic two-bit multiplier, which comprises four multi-resistance state devices, a gating device and a peripheral control circuit, wherein one end of each multi-resistance state device is used as a top electrode input end, the other end of each multi-resistance state device is connected with a drain end of the gating device, a gate end of the gating device is used as a word line of the multi-resistance state device, and a source end of the gating device is connected with a bottom electrode input end; the multi-resistance state device is used for realizing nonvolatile Boolean logic operation and directly storing an operation result in a resistance state of the multi-resistance state device; the gating device is used for gating any one of the four multi-resistance state devices to realize logic operation; the peripheral control circuit is used for applying an operation signal to the gated multi-resistance state device, enabling the operation signal and the resistance state of the multi-resistance state device to be used as input to realize logic operation, and carrying out state cascade before carrying out next logic operation so that a calculation result of the previous step is used as logic input of the next step and is stored in the multi-resistance state device.
The multi-resistance state device used in this embodiment may be a phase change memory, and thus, this embodiment uses a 1T1R phase change memory cell structure to write an input signal into a nonvolatile cell, and the calculation result is directly stored in the resistance state of the phase change memory. The non-volatile two-bit multiplication can be completed in five steps with only 6 devices.
The phase change memory gating device realizes unit gating, a specific memory unit of the memory array is selected to be read and written to realize multiplication operation, and fig. 1 is a schematic structural diagram of a 1T1R unit with a MOS transistor as a gating device. The gate tube for realizing the logic calculation of the phase change memory unit is realized by an NMOS transistor (T), and the phase change material unit is equivalent to a variable resistor (R). In this structure, the Gate terminal (Gate) of the NMOS transistor is the Word Line (WL) of the memory cell, the Drain terminal (Drain) is connected to one terminal of the phase change cell, the other terminal of the phase change cell is the top electrode input terminal T1 of the cell, and the Source terminal (Source) of the transistor is connected to the bottom electrode input terminal T2.
When the input signal is defined as binary logic '1', the input pulse signal is SET or RESET; when the binary logic of the input signal is "0", it represents that the input electrode is connected to GND. The output signal of the nonvolatile Boolean logic is represented by a logic state, and the binary logic signal is defined to be 0 when the phase change memory cell is in a high resistance state, and the binary logic signal is defined to be 1 when the phase change memory cell is in a low resistance state.
The phase change memory applies input pulse signals, and the resistance state of the unit is subjected to threshold value inversion. When the applied signal of the phase change memory is a RESET input pulse, the phase change memory is converted into a high-resistance state, and the calculation result corresponds to binary logic '0'; when the applied signal of the phase change memory is SET input pulse, the phase change memory is converted into a low resistance state, and the calculation result corresponds to binary logic '1'.
AND outputting a four-bit calculation result by realizing two-bit multiplication operation, wherein the calculation needs device state initialization, logical AND (AND) AND exclusive OR (XOR) operation.
The logic computing device state initialization is that the four phase change memories are set to a uniform resistance state before computation starts, and computation is carried out after the initialization step. The initialization step can help the logic calculation process to be more accurate and reduce logic control misoperation. Initializing the logic operation: initializing before all logic calculation, automatically configuring the logic calculation to be in an optimal working state after each power-on, initializing all devices to be in a high-resistance state, and fully amorphizing the devices.
One-bit multiplication, i.e., one-bit AND (AND) logic operation, is implemented in boolean logic computations. In the nonvolatile phase-change memory device, the calculation result is directly stored in the phase-change memory calculation unit in the form of a resistance value, AND due to its nonvolatile characteristic, a logic calculation AND (AND) operation is greatly different in a writing AND logic manner after initially writing data AND storing the result.
In the initial data and logic writing process, all device units are initialized to be in a high-resistance state by RESET operation, subsequent logic operation is written on the basis of the high-resistance units, and the MOS is used as a multiplicand. In cell 1T1R, when the level of the word line input terminal gates the MOS gate transistor, the input pulse signal applied to the top electrode changes the resistance state of the logic cell according to the boolean logic calculation rule. When the gate selection tube is turned off, the input signal can not change the resistance state of the device. Therefore, the gating end and the top electrode input signal jointly realize the conversion of the device state, and the logic state is set to be a set logic value only when the effective level signal is input simultaneously.
In the phase change memory calculation unit, after initial data is stored, initial input data is stored in a phase change cell resistance state as a calculation result of a previous step due to the inherent nonvolatile characteristic of the phase change memory cell. Setting a nonvolatile and logic calculation rule to be combined with the characteristics of the nonvolatile phase-change memory device, and before the next logic operation is carried out, state cascade is required to be carried out, namely, the calculation result of the previous step is stored in a phase-change unit as the logic input of the next step. In the and logic operation, p is used as a multiplicand, and the multiplicand is converted into an input pulse signal control terminal T1; q is used as a multiplier and is stored in the computing unit in the form of the resistance value state of the phase change memory unit; the output z represents the result of the and logic calculation, stored in the cell as a resistance value. When the logic value p is 0, an input pulse signal is defined as RESET operation, the phase change memory state is changed according to the input pulse signal, and the resistance value of a phase change memory unit is set as a high resistance state, so that p.q operation is realized; when p has a logic value of 1, the state is not changed. The logic computation truth table is shown in fig. 2. Therefore, in the device unit of 1T1R, one-bit multiplication operation, i.e., and logic operation, defines two input variables as the amplitude of the input pulse signal and the state of the initialized resistance value, respectively, thereby implementing non-volatile boolean logic and calculation.
The logic calculation exclusive-or (XOR) operation takes the calculation result of the previous step as input and participates in XOR logic calculation in the two-bit multiplier, so that the initial state of the device is taken as logic input and the operation result is determined. The initial state of the device is RESET to be in a high-impedance state in the initialization process, a logic input binary signal p is applied to an input upper electrode, the initial state of the device is read out, and the input operation is determined to be the RESET operation or the SET operation. When the input logic value is '1' and the initialization state is a high-resistance state, a SET pulse signal is applied, when the input logic value is '0' and the initialization state is a low-resistance state, a RESET pulse signal is applied, when the input binary logic is '0', the input electrode is connected with GND, and the device keeps the initialization state.
Based on one-bit multiplication operation, the two-bit data is subjected to AND logic and XOR logic combination operation to complete a two-bit nonvolatile logic multiplier, and the two-bit multiplication operation is shown in FIG. 3, wherein C0、C1、C2、C3The results of the calculations of (a) are listed in the formula. The logic calculation result finally obtained by each bit unit device in the two-bit multiplier is directly stored in the phase change memory unit, and the realized results are respectively as follows:
C0＝A0A1B0B1；
C3＝A0B0；
AND (2) initializing AND setting to be an AND (AND) logic operation, selecting a multiplicand as a MOS gating signal, AND inputting the multiplicand as an SET setting signal into a top electrode. The binary logic value of the multiplier is 0, and the input electrode is connected with a GND signal; the multiplier binary logic value is "1" and the input electrode applies the SET signal. When the strobe tube is gated and the value of the input signal is not '0', the state of the device is binary logic '1'; otherwise, the device state is set to binary logic "0".
In this embodiment, only 6 device 5 steps are needed to realize the two-bit multiplier, and the resistance states of the phase change memory logic unit are respectively defined as a high resistance state and a low resistance state corresponding to a binary logic "0" and a binary logic "1". Logical operation device unit and operation steps as shown in fig. 4, for the step list the boxes represent OR logical operations, the circles represent READ operations, and the triangles represent XOR operations. The logic operation device unit and the operation steps are as follows:
step 1: after the initialization operation are respectivelyPhase change memory C11Phase change memory C12Phase change memory C21Phase change memory C22In the middle of writing A0B0、A0B1、A1B1、A1B0；
Step 2: in the phase change memory C11Performing a one-bit AND logic operation to obtain A0B0A1And phase change memory C12And a phase change memory C22Reading out the stored result in (1);
and step 3: in the phase change memory C11Performing a one-bit AND logic operation to obtain A0B0A1B1Converting the resistance state read in the previous step into C12Cell two terminal electrode logic input in phase change memory C12Is subjected to XOR operation to obtain
And 4, step 4: read in phase change memory C11The calculation result A in (1)0A1B0B1And in the phase change memory C22Write in A0B0；
And 5: in the phase change memory C21Performing one-step XOR operation to obtain
In the implementation of the phase change memory cell Boolean logic two-bit multiplier, only 4 phase change memory cells are used, and by utilizing the inherent nonvolatile physical characteristics and threshold conversion characteristics of the phase change memory cells, the logic operation result is divided into initial writing logic operation which does not need to participate in calculation in an initial state and logic cascade operation which needs to participate in the initial state, and the resistance value state of the previous logic calculation result is taken as the input result of the next operation to participate in calculation. Due to its non-volatility, intermediate results are directly retained and can be directly called when sub-computations are made.
And testing the function of the phase change storage nonvolatile Boolean logic multiplier by building an SPICE model of the phase change storage logic unit. As shown in fig. 5, when the input logic values are A0-1, a 1-1, B0-1 and B2-1, respectively, as a simulation result of the 2-bit binary multiplier based on the phase change memory cell, the obtained calculation result is directly stored in the phase change memory cell, which is shown as C0-A0B 0-1,
c3 ═ A0A1B0B1 ═ 1, where the calculation "0" was in the high resistance state and "1" was in the low resistance state. From simulation of fig. 5, it can be seen that the logic relationship between all the input signals and the output states of the two-bit binary multiplier conforms to the truth table of the 2-bit binary multiplier, and the 2-bit multiplier function can be accurately realized in 4 phase-change memory cells.
The invention designs a 2-bit binary multiplier of a phase change storage Boolean logic circuit based on the unit characteristics of a phase change memory. By combining the phase change memory nonvolatile logic AND and XOR, the 2-bit multiplier circuit calculation is completed in 5 steps in 4 phase change memory cells. Simulation analysis proves that the logic module can realize the function of a 2-bit multiplier, and compared with the conventional logic realization based on a CMOS logic circuit, the multiplier circuit greatly reduces the number of devices, directly stores a logic value in a phase change unit, does not need to erase the state of the device for multiple times, and reduces the power consumption and transmission time consumption of the device in the logic cascade process. And the phase change memory array can realize logic calculation and memory functions, so that a wider direction is provided for the research of a novel calculation architecture, and the phase change memory array is an excellent research scheme for replacing a von Neumann calculation architecture to realize efficient calculation.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110494509.6A CN113380298A (en) | 2021-05-07 | 2021-05-07 | Nonvolatile Boolean logic two-bit multiplier and operation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110494509.6A CN113380298A (en) | 2021-05-07 | 2021-05-07 | Nonvolatile Boolean logic two-bit multiplier and operation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113380298A true CN113380298A (en) | 2021-09-10 |
Family
ID=77570494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110494509.6A Pending CN113380298A (en) | 2021-05-07 | 2021-05-07 | Nonvolatile Boolean logic two-bit multiplier and operation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113380298A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5447539A (en) * | 1977-09-22 | 1979-04-14 | Nippon Telegr & Teleph Corp <Ntt> | Digital binary multiplier circuit |
| FR2475250A1 (en) * | 1980-01-31 | 1981-08-07 | Thomson Csf Mat Tel | Fast multiplier for long binary numbers - uses multiple and=gates to multiply one bit of first number simultaneously with every bit of second number and groups like weighted bits |
| CN102931206A (en) * | 2012-11-16 | 2013-02-13 | 中国科学院上海微系统与信息技术研究所 | Circuit structure of high-density phase change memory and manufacturing method for circuit structure |
| WO2014109771A1 (en) * | 2013-01-14 | 2014-07-17 | Hewlett-Packard Development Company, L.P. | Nonvolatile memory array logic |
| US9548741B1 (en) * | 2015-07-14 | 2017-01-17 | Technion Research And Development Foundation Ltd. | Memristive akers logic array |
| CN106374912A (en) * | 2016-09-12 | 2017-02-01 | 华中科技大学 | A logic operation circuit and operation method |
| CN109634557A (en) * | 2018-11-19 | 2019-04-16 | 华中科技大学 | A kind of multiplier and operation method based on 1T1R memory |
| CN110362291A (en) * | 2018-03-26 | 2019-10-22 | 北京大学 | A method of non-volatile complex calculation is carried out using memristor |
| CN111061454A (en) * | 2019-12-18 | 2020-04-24 | 北京大学 | Logic implementation method based on bipolar memristor |
| CN112015367A (en) * | 2020-08-26 | 2020-12-01 | 上海新氦类脑智能科技有限公司 | Nonvolatile Boolean logic operation unit, method and device |
-
2021
- 2021-05-07 CN CN202110494509.6A patent/CN113380298A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5447539A (en) * | 1977-09-22 | 1979-04-14 | Nippon Telegr & Teleph Corp <Ntt> | Digital binary multiplier circuit |
| FR2475250A1 (en) * | 1980-01-31 | 1981-08-07 | Thomson Csf Mat Tel | Fast multiplier for long binary numbers - uses multiple and=gates to multiply one bit of first number simultaneously with every bit of second number and groups like weighted bits |
| CN102931206A (en) * | 2012-11-16 | 2013-02-13 | 中国科学院上海微系统与信息技术研究所 | Circuit structure of high-density phase change memory and manufacturing method for circuit structure |
| WO2014109771A1 (en) * | 2013-01-14 | 2014-07-17 | Hewlett-Packard Development Company, L.P. | Nonvolatile memory array logic |
| US9548741B1 (en) * | 2015-07-14 | 2017-01-17 | Technion Research And Development Foundation Ltd. | Memristive akers logic array |
| CN106374912A (en) * | 2016-09-12 | 2017-02-01 | 华中科技大学 | A logic operation circuit and operation method |
| CN110362291A (en) * | 2018-03-26 | 2019-10-22 | 北京大学 | A method of non-volatile complex calculation is carried out using memristor |
| CN109634557A (en) * | 2018-11-19 | 2019-04-16 | 华中科技大学 | A kind of multiplier and operation method based on 1T1R memory |
| CN111061454A (en) * | 2019-12-18 | 2020-04-24 | 北京大学 | Logic implementation method based on bipolar memristor |
| CN112015367A (en) * | 2020-08-26 | 2020-12-01 | 上海新氦类脑智能科技有限公司 | Nonvolatile Boolean logic operation unit, method and device |
Non-Patent Citations (2)
| Title |
|---|
| 李;缪向水;: "基于忆阻器的存储与计算融合理论与实现", 国防科技, no. 06, 20 December 2016 (2016-12-20) * |
| 王光义;沈书航;刘公致;李付鹏;: "基于忆阻器的乘法器电路设计", 电子与信息学报, no. 04, 15 April 2020 (2020-04-15) * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109388853B (en) | Single-pole and double-pole mixed efficient memristor logic circuit and control method thereof | |
| CN113467751B (en) | Analog domain memory internal computing array structure based on magnetic random access memory | |
| CN109859786B (en) | A data computing method based on spin magnetic memory | |
| CN112636745B (en) | Logic unit, adder and multiplier | |
| CN109634557B (en) | A multiplier and operation method based on 1T1R memory | |
| CN111061454B (en) | A logic implementation method based on bipolar memristor | |
| CN106158017A (en) | The method and apparatus realizing logic and arithmetical operation based on resistance computing | |
| CN112015367B (en) | Nonvolatile Boolean logic operation unit, method and device | |
| CN110058839A (en) | A kind of circuit structure based on subtraction in Static RAM memory | |
| CN110827898B (en) | A memristor-based voltage-resistance reversible logic circuit and its operation method | |
| CN106374912A (en) | A logic operation circuit and operation method | |
| Ma et al. | In-memory computing: The next-generation ai computing paradigm | |
| CN109979503A (en) | A kind of Static RAM circuit structure realizing Hamming distance in memory and calculating | |
| WO2020173040A1 (en) | Reversible logic circuit and operation method thereof | |
| CN106373611A (en) | A storage and computing array structure and its operation method | |
| CN114496010A (en) | Analog domain near memory computing array structure based on magnetic random access memory | |
| CN115376581B (en) | Memristor-based in-memory computing array structure | |
| CN114974337A (en) | A time-domain in-memory computing circuit based on spin magnetic random access memory | |
| CN113658625A (en) | 1T1R array-based reconfigurable state logic operation circuit and method | |
| CN108154226B (en) | Neural network chip using analog computation | |
| Monga et al. | A novel decoder design for logic computation in SRAM: CiM-SRAM | |
| CN113315506B (en) | Phase-change memory time sequence reconfigurable Boolean logic circuit, method and device | |
| CN113380298A (en) | Nonvolatile Boolean logic two-bit multiplier and operation method | |
| Pan et al. | A mini tutorial of processing in memory: From principles, devices to prototypes | |
| CN113539327B (en) | Device for realizing quick logic calculation of phase change memory unit and data retrieval method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |