CN113380298A - Nonvolatile Boolean logic two-bit multiplier and operation method - Google Patents
Nonvolatile Boolean logic two-bit multiplier and operation method Download PDFInfo
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Abstract
The invention relates to a nonvolatile Boolean logic two-bit multiplier and an operation method, wherein the multiplier comprises four multi-resistance state devices, a gating device and a peripheral control circuit, one end of each multi-resistance state device is used as a top electrode input end, the other end of each multi-resistance state device is connected with a drain end of the gating device, a gate end of the gating device is used as a word line of the multi-resistance state device, and a source end of the gating device is connected with a bottom electrode input end; the multi-resistance state device is used for realizing nonvolatile Boolean logic operation and directly storing an operation result in a resistance state of the multi-resistance state device; the gating device is used for gating any one of the four multi-resistance state devices to realize logic operation; and the peripheral control circuit is used for applying an operation signal to the gated multi-resistance state device so as to enable the multi-resistance state device to realize logic operation, and performing state cascade before next logic operation so that a calculation result of the previous step is stored in the multi-resistance state device as logic input of the next step. The invention uses a small number of devices to quickly realize nonvolatile multiplication operation.
Description
Technical Field
The invention relates to the technical field of nonvolatile storage calculation, in particular to a nonvolatile Boolean logic two-bit multiplier and an operation method.
Background
At present, communication, computer and personal consumer electronics products are developed, and the explosive increase of data volume makes the demand of the market for memories larger and larger, and promotes the development and the revolution of storage technology. Therefore, it is a hot spot of research to realize memories with higher speed, larger capacity, higher integration, stronger reliability and lower power consumption. Phase change memory is a new type of nonvolatile memory, and the research result that chalcogenide compounds can be reversibly transformed between high-resistance amorphous state and low-resistance polycrystalline state under the action of an electric field was published by Stanford r. In the artificial intelligence era, phase change memories play an important role in various fields, such as nonvolatile memories, neural network accelerators, boolean logic calculations, and the like.
With the continuous development of moore's law, the framework of von neumann framework calculation and storage separation hinders the further improvement of computational efficiency, in order to solve the bottleneck of storage wall and power consumption, combines calculation and storage, and the utilization of novel nonvolatile phase change memory to realize nonvolatile Boolean logic calculation in the in-memory calculation has wide research prospect. The existing nonvolatile logic calculation is mainly divided into two types, one type is state logic, input and output signals are represented by device resistance values, and cascaded signal conversion among devices is not needed; the other type is non-state logic, with the inputs typically represented by voltage signals and the results of the calculations stored as resistance values. In both non-volatile boolean logic operations, the result of the computation is stored directly in the form of a resistance value in the phase change memory computation cell.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a nonvolatile Boolean logic multiplier and an operation method, and the nonvolatile multiplication operation is quickly realized by using a small number of devices.
The technical scheme adopted by the invention for solving the technical problems is as follows: the non-volatile Boolean logic two-bit multiplier comprises four multi-resistance state devices, a gating device and a peripheral control circuit, wherein one end of each multi-resistance state device is used as a top electrode input end, the other end of each multi-resistance state device is connected with a drain end of the gating device, a gate end of the gating device is used as a word line of the multi-resistance state device, and a source end of the gating device is connected with a bottom electrode input end; the multi-resistance state device is used for realizing nonvolatile Boolean logic operation and directly storing an operation result in a resistance state of the multi-resistance state device; the gating device is used for gating any one of the four multi-resistance state devices to realize logic operation; the peripheral control circuit is used for applying an operation signal to the gated multi-resistance state device, enabling the operation signal and the resistance state of the multi-resistance state device to be used as input to realize logic operation, and carrying out state cascade before carrying out next logic operation so that a calculation result of the previous step is used as logic input of the next step and is stored in the multi-resistance state device.
After the multi-resistance state device applies an input pulse signal, the resistance state of the multi-resistance state device is subjected to threshold value overturning.
When an input pulse signal applied by the multi-resistance state device is a RESET input pulse, the multi-resistance state device is converted into a high-resistance state, and a calculation result corresponds to binary logic '0'; when the input pulse signal applied by the multi-resistance state device is an SET input pulse, the multi-resistance state device is converted into a low-resistance state, and the calculation result corresponds to binary logic '1'.
When the logic operation is initialization logic operation, the peripheral control circuit inputs a RESET input pulse to the four multi-resistance state devices, so that the four multi-resistance state devices are all in a high-resistance state.
When the logic operation is an AND logic operation, the peripheral control circuit converts a multiplicand into a pulse signal and applies the pulse signal to the input end of the top electrode, the multiplicand is stored in the multi-resistance state device in the form of the resistance state of the multi-resistance state device, and the output result is stored in the resistance state of the multi-resistance state device.
When the logic operation is an exclusive-or logic operation, the peripheral control circuit applies a logically input binary signal to the top electrode input terminal, reads out an initial state of the multi-resistance state device, and determines whether an input operation is a RESET operation or a SET operation based on the initial state.
The multi-resistance state device is a phase change memory unit.
The technical scheme adopted by the invention for solving the technical problems is as follows: the four multi-resistance state devices are marked as a multi-resistance state device C11Multi-resistance state device C12Multi-resistance state device C21And a multi-resistance state device C22The method comprises the following steps:
(1) for the multi-resistance state device C11Multi-resistance state device C12Multi-resistance state device C21And a multi-resistance state device C22Performing initialization operation, and respectively performing multiple resistance state devices C after the initialization operation is completed11Multi-resistance state device C12Multi-resistance state device C21And a multi-resistance state device C22In the middle of writing A0B0、A0B1、A1B1And A1B0；
(2) In the multi-resistance state device C11Performing a one-bit AND logic operation to obtain A0B0A1And reading out the multi-resistance state device C12And a multi-resistance state device C22Storing the result;
(3) in the multi-resistance state device C11Performing a one-bit AND logic operation to obtain A0B0A1B1The result read out in the step (2) is in a multi-resistance stateDevice C12Is subjected to XOR operation to obtain
(4) Readout multi-resistance state device C11The calculation result A in (1)0A1B0B1And in the multi-resistance state device C22Write in A0B0；
(5) In the multi-resistance state device C21Implementing an XOR operation to obtain
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention utilizes the characteristics of phase change storage threshold value conversion and nonvolatile storage to construct a phase change storage nonvolatile Boolean logic calculation two-bit multiplier, compared with the traditional logic calculation to realize two-bit multiplication operation, the nonvolatile Boolean logic realization method is beneficial to reducing power consumption and time consumption caused by frequent data transmission, realizing logic operation in a storage array and reducing energy consumption.
Drawings
FIG. 1 is a schematic diagram of a phase change memory cell 1T 1R;
FIG. 2 is a schematic diagram of an AND (AND) logic truth table;
FIG. 3 is a schematic diagram of a 2-bit multiplication calculation;
FIG. 4 is a schematic diagram of a logic operation device unit and operation steps;
FIG. 5 is a schematic diagram of the simulated input and output of the two-bit multiplier.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The embodiment of the invention relates to a nonvolatile Boolean logic two-bit multiplier, which comprises four multi-resistance state devices, a gating device and a peripheral control circuit, wherein one end of each multi-resistance state device is used as a top electrode input end, the other end of each multi-resistance state device is connected with a drain end of the gating device, a gate end of the gating device is used as a word line of the multi-resistance state device, and a source end of the gating device is connected with a bottom electrode input end; the multi-resistance state device is used for realizing nonvolatile Boolean logic operation and directly storing an operation result in a resistance state of the multi-resistance state device; the gating device is used for gating any one of the four multi-resistance state devices to realize logic operation; the peripheral control circuit is used for applying an operation signal to the gated multi-resistance state device, enabling the operation signal and the resistance state of the multi-resistance state device to be used as input to realize logic operation, and carrying out state cascade before carrying out next logic operation so that a calculation result of the previous step is used as logic input of the next step and is stored in the multi-resistance state device.
The multi-resistance state device used in this embodiment may be a phase change memory, and thus, this embodiment uses a 1T1R phase change memory cell structure to write an input signal into a nonvolatile cell, and the calculation result is directly stored in the resistance state of the phase change memory. The non-volatile two-bit multiplication can be completed in five steps with only 6 devices.
The phase change memory gating device realizes unit gating, a specific memory unit of the memory array is selected to be read and written to realize multiplication operation, and fig. 1 is a schematic structural diagram of a 1T1R unit with a MOS transistor as a gating device. The gate tube for realizing the logic calculation of the phase change memory unit is realized by an NMOS transistor (T), and the phase change material unit is equivalent to a variable resistor (R). In this structure, the Gate terminal (Gate) of the NMOS transistor is the Word Line (WL) of the memory cell, the Drain terminal (Drain) is connected to one terminal of the phase change cell, the other terminal of the phase change cell is the top electrode input terminal T1 of the cell, and the Source terminal (Source) of the transistor is connected to the bottom electrode input terminal T2.
When the input signal is defined as binary logic '1', the input pulse signal is SET or RESET; when the binary logic of the input signal is "0", it represents that the input electrode is connected to GND. The output signal of the nonvolatile Boolean logic is represented by a logic state, and the binary logic signal is defined to be 0 when the phase change memory cell is in a high resistance state, and the binary logic signal is defined to be 1 when the phase change memory cell is in a low resistance state.
The phase change memory applies input pulse signals, and the resistance state of the unit is subjected to threshold value inversion. When the applied signal of the phase change memory is a RESET input pulse, the phase change memory is converted into a high-resistance state, and the calculation result corresponds to binary logic '0'; when the applied signal of the phase change memory is SET input pulse, the phase change memory is converted into a low resistance state, and the calculation result corresponds to binary logic '1'.
AND outputting a four-bit calculation result by realizing two-bit multiplication operation, wherein the calculation needs device state initialization, logical AND (AND) AND exclusive OR (XOR) operation.
The logic computing device state initialization is that the four phase change memories are set to a uniform resistance state before computation starts, and computation is carried out after the initialization step. The initialization step can help the logic calculation process to be more accurate and reduce logic control misoperation. Initializing the logic operation: initializing before all logic calculation, automatically configuring the logic calculation to be in an optimal working state after each power-on, initializing all devices to be in a high-resistance state, and fully amorphizing the devices.
One-bit multiplication, i.e., one-bit AND (AND) logic operation, is implemented in boolean logic computations. In the nonvolatile phase-change memory device, the calculation result is directly stored in the phase-change memory calculation unit in the form of a resistance value, AND due to its nonvolatile characteristic, a logic calculation AND (AND) operation is greatly different in a writing AND logic manner after initially writing data AND storing the result.
In the initial data and logic writing process, all device units are initialized to be in a high-resistance state by RESET operation, subsequent logic operation is written on the basis of the high-resistance units, and the MOS is used as a multiplicand. In cell 1T1R, when the level of the word line input terminal gates the MOS gate transistor, the input pulse signal applied to the top electrode changes the resistance state of the logic cell according to the boolean logic calculation rule. When the gate selection tube is turned off, the input signal can not change the resistance state of the device. Therefore, the gating end and the top electrode input signal jointly realize the conversion of the device state, and the logic state is set to be a set logic value only when the effective level signal is input simultaneously.
In the phase change memory calculation unit, after initial data is stored, initial input data is stored in a phase change cell resistance state as a calculation result of a previous step due to the inherent nonvolatile characteristic of the phase change memory cell. Setting a nonvolatile and logic calculation rule to be combined with the characteristics of the nonvolatile phase-change memory device, and before the next logic operation is carried out, state cascade is required to be carried out, namely, the calculation result of the previous step is stored in a phase-change unit as the logic input of the next step. In the and logic operation, p is used as a multiplicand, and the multiplicand is converted into an input pulse signal control terminal T1; q is used as a multiplier and is stored in the computing unit in the form of the resistance value state of the phase change memory unit; the output z represents the result of the and logic calculation, stored in the cell as a resistance value. When the logic value p is 0, an input pulse signal is defined as RESET operation, the phase change memory state is changed according to the input pulse signal, and the resistance value of a phase change memory unit is set as a high resistance state, so that p.q operation is realized; when p has a logic value of 1, the state is not changed. The logic computation truth table is shown in fig. 2. Therefore, in the device unit of 1T1R, one-bit multiplication operation, i.e., and logic operation, defines two input variables as the amplitude of the input pulse signal and the state of the initialized resistance value, respectively, thereby implementing non-volatile boolean logic and calculation.
The logic calculation exclusive-or (XOR) operation takes the calculation result of the previous step as input and participates in XOR logic calculation in the two-bit multiplier, so that the initial state of the device is taken as logic input and the operation result is determined. The initial state of the device is RESET to be in a high-impedance state in the initialization process, a logic input binary signal p is applied to an input upper electrode, the initial state of the device is read out, and the input operation is determined to be the RESET operation or the SET operation. When the input logic value is '1' and the initialization state is a high-resistance state, a SET pulse signal is applied, when the input logic value is '0' and the initialization state is a low-resistance state, a RESET pulse signal is applied, when the input binary logic is '0', the input electrode is connected with GND, and the device keeps the initialization state.
Based on one-bit multiplication operation, the two-bit data is subjected to AND logic and XOR logic combination operation to complete a two-bit nonvolatile logic multiplier, and the two-bit multiplication operation is shown in FIG. 3, wherein C0、C1、C2、C3The results of the calculations of (a) are listed in the formula. The logic calculation result finally obtained by each bit unit device in the two-bit multiplier is directly stored in the phase change memory unit, and the realized results are respectively as follows:
C0＝A0A1B0B1；
C3＝A0B0；
AND (2) initializing AND setting to be an AND (AND) logic operation, selecting a multiplicand as a MOS gating signal, AND inputting the multiplicand as an SET setting signal into a top electrode. The binary logic value of the multiplier is 0, and the input electrode is connected with a GND signal; the multiplier binary logic value is "1" and the input electrode applies the SET signal. When the strobe tube is gated and the value of the input signal is not '0', the state of the device is binary logic '1'; otherwise, the device state is set to binary logic "0".
In this embodiment, only 6 device 5 steps are needed to realize the two-bit multiplier, and the resistance states of the phase change memory logic unit are respectively defined as a high resistance state and a low resistance state corresponding to a binary logic "0" and a binary logic "1". Logical operation device unit and operation steps as shown in fig. 4, for the step list the boxes represent OR logical operations, the circles represent READ operations, and the triangles represent XOR operations. The logic operation device unit and the operation steps are as follows:
step 1: after the initialization operation are respectivelyPhase change memory C11Phase change memory C12Phase change memory C21Phase change memory C22In the middle of writing A0B0、A0B1、A1B1、A1B0；
Step 2: in the phase change memory C11Performing a one-bit AND logic operation to obtain A0B0A1And phase change memory C12And a phase change memory C22Reading out the stored result in (1);
and step 3: in the phase change memory C11Performing a one-bit AND logic operation to obtain A0B0A1B1Converting the resistance state read in the previous step into C12Cell two terminal electrode logic input in phase change memory C12Is subjected to XOR operation to obtain
And 4, step 4: read in phase change memory C11The calculation result A in (1)0A1B0B1And in the phase change memory C22Write in A0B0；
And 5: in the phase change memory C21Performing one-step XOR operation to obtain
In the implementation of the phase change memory cell Boolean logic two-bit multiplier, only 4 phase change memory cells are used, and by utilizing the inherent nonvolatile physical characteristics and threshold conversion characteristics of the phase change memory cells, the logic operation result is divided into initial writing logic operation which does not need to participate in calculation in an initial state and logic cascade operation which needs to participate in the initial state, and the resistance value state of the previous logic calculation result is taken as the input result of the next operation to participate in calculation. Due to its non-volatility, intermediate results are directly retained and can be directly called when sub-computations are made.
And testing the function of the phase change storage nonvolatile Boolean logic multiplier by building an SPICE model of the phase change storage logic unit. As shown in fig. 5, when the input logic values are A0-1, a 1-1, B0-1 and B2-1, respectively, as a simulation result of the 2-bit binary multiplier based on the phase change memory cell, the obtained calculation result is directly stored in the phase change memory cell, which is shown as C0-A0B 0-1,
c3 ═ A0A1B0B1 ═ 1, where the calculation "0" was in the high resistance state and "1" was in the low resistance state. From simulation of fig. 5, it can be seen that the logic relationship between all the input signals and the output states of the two-bit binary multiplier conforms to the truth table of the 2-bit binary multiplier, and the 2-bit multiplier function can be accurately realized in 4 phase-change memory cells.
The invention designs a 2-bit binary multiplier of a phase change storage Boolean logic circuit based on the unit characteristics of a phase change memory. By combining the phase change memory nonvolatile logic AND and XOR, the 2-bit multiplier circuit calculation is completed in 5 steps in 4 phase change memory cells. Simulation analysis proves that the logic module can realize the function of a 2-bit multiplier, and compared with the conventional logic realization based on a CMOS logic circuit, the multiplier circuit greatly reduces the number of devices, directly stores a logic value in a phase change unit, does not need to erase the state of the device for multiple times, and reduces the power consumption and transmission time consumption of the device in the logic cascade process. And the phase change memory array can realize logic calculation and memory functions, so that a wider direction is provided for the research of a novel calculation architecture, and the phase change memory array is an excellent research scheme for replacing a von Neumann calculation architecture to realize efficient calculation.
Claims (8)
1. A nonvolatile Boolean logic two-bit multiplier is characterized by comprising four multi-resistance state devices, a gating device and a peripheral control circuit, wherein one end of each multi-resistance state device is used as a top electrode input end, the other end of each multi-resistance state device is connected with a drain end of the gating device, a gate end of the gating device is used as a word line of the multi-resistance state device, and a source end of the gating device is connected with a bottom electrode input end; the multi-resistance state device is used for realizing nonvolatile Boolean logic operation and directly storing an operation result in a resistance state of the multi-resistance state device; the gating device is used for gating any one of the four multi-resistance state devices to realize logic operation; the peripheral control circuit is used for applying an operation signal to the gated multi-resistance state device, enabling the operation signal and the resistance state of the multi-resistance state device to be used as input to realize logic operation, and carrying out state cascade before carrying out next logic operation so that a calculation result of the previous step is used as logic input of the next step and is stored in the multi-resistance state device.
2. The non-volatile Boolean logic two-bit multiplier of claim 1, wherein the resistance state of the multi-resistance state device is threshold flipped after the input pulse signal is applied to the multi-resistance state device.
3. The two-bit non-volatile boolean logic multiplier according to claim 2, characterized in that said multi-resistance state device is changed into a high-resistance state when an input pulse signal applied by said multi-resistance state device is a RESET input pulse, the calculation result corresponding to a binary logic "0"; when the input pulse signal applied by the multi-resistance state device is an SET input pulse, the multi-resistance state device is converted into a low-resistance state, and the calculation result corresponds to binary logic '1'.
4. The non-volatile boolean logic two-bit multiplier of claim 1 wherein when the logic operation is an initialization logic operation, the peripheral control circuit inputs a RESET input pulse to the four multi-resistance state devices such that the four multi-resistance state devices are all in a high resistance state.
5. The non-volatile boolean logic two-bit multiplier of claim 1 wherein when the logic operation is an and logic operation, the peripheral control circuit converts a multiplicand into a pulse signal and applies the pulse signal to the top electrode input, the multiplier is stored in the multi-resistance state device in the form of a resistance state of the multi-resistance state device, and the output result is stored in the resistance state of the multi-resistance state device.
6. The non-volatile boolean logic two-bit multiplier according to claim 1, characterized in that when the logic operation is an exclusive or logic operation, the peripheral control circuit applies a logic input binary signal to the top electrode input, reads out an initial state of the multi-resistance state device, and decides based on the initial state that the input operation is a RESET operation or a SET operation.
7. The non-volatile boolean logic two-bit multiplier of claim 1 wherein the multi-resistance state device is a phase change memory cell.
8. An operating method of the non-volatile boolean logic two-bit multiplier as claimed in any one of claims 1 to 7, characterized in that four multi-resistance state devices are denoted as multi-resistance state devices C11Multi-resistance state device C12Multi-resistance state device C21And a multi-resistance state device C22The method comprises the following steps:
(1) for the multi-resistance state device C11Multi-resistance state device C12Multi-resistance state device C21And a multi-resistance state device C22Performing initialization operation, and respectively performing multiple resistance state devices C after the initialization operation is completed11Multi-resistance state device C12Multi-resistance state device C21And a multi-resistance state device C22In the middle of writing A0B0、A0B1、A1B1And A1B0；
(2) In the multi-resistance state device C11Performing a one-bit AND logic operation to obtain A0B0A1And reading out the multi-resistance state device C12And a multi-resistance state device C22Storing the result;
(3) in the multi-resistance state device C11Performing a one-bit AND logic operation to obtain A0B0A1B1Reading the result in step (2) in multipleResistive device C12Performing XOR operation to obtain A0B1⊕A1B0；
(4) Readout multi-resistance state device C11The calculation result A in (1)0A1B0B1And in the multi-resistance state device C22Write in A0B0；
(5) In the multi-resistance state device C21Implementing an XOR operation to obtain A0A1B0B1⊕A1B1。
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