CN102931206A - Circuit structure of high-density phase change memory and manufacturing method for circuit structure - Google Patents
Circuit structure of high-density phase change memory and manufacturing method for circuit structure Download PDFInfo
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- CN102931206A CN102931206A CN2012104617139A CN201210461713A CN102931206A CN 102931206 A CN102931206 A CN 102931206A CN 2012104617139 A CN2012104617139 A CN 2012104617139A CN 201210461713 A CN201210461713 A CN 201210461713A CN 102931206 A CN102931206 A CN 102931206A
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Abstract
The invention relates to a circuit structure of a high-density phase change memory and a manufacturing method for the circuit structure. The structure of the phase change memory comprises a gate tube and n phase change resistors, wherein a source terminal of the gate tube is grounded; a gate terminal of the gate tube is connected with a word line WL; the n phase change resistors are arranged in parallel; one ends of various phase change resistors are commonly connected to a drain terminal of the gate tube; and the other ends of various phase change resistors are respectively connected with respective bit lines, wherein n is an integer and is not smaller than 2. According to the circuit structure disclosed by the invention, on the premise that the size of the gate tube is not changed, the density of the phase change memory is improved by changing a phase change storage unit and a layout structure thereof and further the high-density phase change memory is obtained.
Description
Technical field
The invention belongs to micro-nano electronic technology field, relate to a kind of information-storing device, particularly relate to a kind of high-density phase-change memory circuit structure and preparation method thereof.
Background technology
Phase-change memory cell is based on that conception that the phase-change thin film that proposes beginning of the seventies late 1960s can be applied to the phase change memory medium sets up, and is the memory device of a kind of low price, stable performance.Phase-change memory cell can be made on silicon wafer or the SOI substrate, and its critical material is recordable phase-change thin film, heating electrode material, heat-insulating material and extraction electrode material, and its study hotspot also just launches around device technology.The physical mechanism research of device comprises how reducing device material etc.The basic principle of phase-change memory cell is to act on the device cell with electric impulse signal, make phase-change material between amorphous state and polycrystalline attitude reversible transition occur, the low-resistance the when high resistant during by the resolution amorphous state and polycrystalline attitude realizes writing, wipe and read operation of information.
The advantages such as phase transition storage owing to have reads at a high speed, high erasable number of times, non-volatile, component size is little, strong motion low in energy consumption, anti-and radioresistance are thought flash memories that most possible replacement is present by international semiconductor TIA and are become following memory main product and become at first the device of commercial product.
The reading and writing of phase transition storage, wiping operation are exactly voltage or the current pulse signal that applies different in width and height at device cell: wipe and operate (RESET), after adding a phase-change material temperature in the short and strong pulse enable signal device cell and being elevated to more than the fusion temperature, through thereby cooling realization phase-change material polycrystalline attitude is to amorphous conversion fast, namely one state is to the conversion of " 0 " attitude again; Write operation (SET), a pulse enable signal phase-change material temperature long and moderate strength is raised under the fusion temperature when applying, on the crystallization temperature after, and keep a period of time to impel nucleus growth, thus realize amorphous state to the conversion of polycrystalline attitude, namely " 0 " attitude is to the conversion of one state; Read operation after adding a very weak pulse signal that can not exert an influence to the state of phase-change material, is read its state by the resistance value of measuring element unit.
The present common storage organization of phase transition storage is 11R (namely 1 transistor and 1 phase change resistor (phase changeresistor, PCR) consist of 1 memory cell, such as Fig. 1), three kinds of structures of 1D1R and 1B1R.The 1T1R structure because technique is simple, fully compatible and do not need to increase extra light shield and become first-selected structure with CMOS technique.But phase transition storage has lot of advantages, and its shortcoming is exactly that operating current is larger, thereby has caused the area of one-cell switching pipe in the 1T1R structure large and affect density and the cost of memory.Because phase change memory resistance is the device of a nano-scale, so density is the size that is limited by gate tube, under the prerequisite that does not change the gate tube size, we change memory cell structure and domain structure thereof, can improve the density of phase transition storage.
Summary of the invention
The shortcoming of prior art the object of the present invention is to provide a kind of high-density phase-change memory circuit structure in view of the above, under the prerequisite that does not change the gate tube size, by changing phase-change memory cell and domain structure thereof, improves the density of phase transition storage.
Reach for achieving the above object other relevant purposes, the invention provides a kind of high-density phase-change memory circuit structure, described phase change memory structure comprises gate tube and n phase change resistor, the source ground connection of described gate tube, grid termination word line WL; A described n phase change resistor is arranged side by side, and respectively an end of this phase change resistor is connected to the drain terminal of described gate tube jointly, and respectively the other end of this phase change resistor connects respectively bit line separately, and wherein n is integer, n 〉=2.
Preferably, the value of n is 4～6.
Preferably, described gate tube is metal-oxide-semiconductor, diode or triode.
The invention still further relates to a kind of high-density phase-change memory device architecture preparation method, the method may further comprise the steps:
1) provides semi-conductive substrate, form epitaxial loayer in described Semiconductor substrate;
2) on described epitaxial loayer, form sti structure, active area and gate region and the isolation structure around this gate region according to common process;
3) form the first insulating barrier that is provided with contact hole;
4) fill the tungsten plug to described contact hole;
5) sediment phase change thin-film material;
6) the described phase change film material of etching forms n phase change resistor, and wherein n is integer, n 〉=2;
7) preparation metal level and be etched into bit line;
8) prepare all the other metal levels interconnected.
The present invention also comprises a kind of high-density phase-change memory device architecture, and this phase-change memory device structure comprises n phase change resistor and Semiconductor substrate;
Be positioned at the epitaxial loayer on this Semiconductor substrate;
The sti structure that is positioned at the active area on this epitaxial loayer and is used for isolating described active area;
Be positioned at gate region and the isolation structure around this gate region on the described active area;
Be positioned at the insulating barrier on active area, gate region and the sti structure;
Be arranged at the contact hole in the insulating barrier;
Be positioned at the some metal levels on the insulating barrier;
Be filled with metal in the described contact hole and be used for connecting described metal level and active area;
Described phase change resistor links to each other with the source region of gate tube by hearth electrode between the first metal layer and active area.
The invention still further relates to a kind of high-density phase-change memory device architecture, this phase-change memory device structure comprises n phase change resistor and Semiconductor substrate;
Be positioned at the epitaxial loayer on this Semiconductor substrate;
The sti structure that is positioned at the active area on this epitaxial loayer and is used for isolating described active area;
Be positioned at gate region and the isolation structure around this gate region on the described active area;
Be positioned at the insulating barrier on active area, gate region and the sti structure;
Be arranged at the contact hole in the insulating barrier;
Be positioned at the some metal levels on the insulating barrier;
Be filled with metal in the described contact hole and be used for connecting described metal level and active area;
Described phase change resistor is arbitrarily between the two-layer adjacent metal level, and the metal level by low one deck links to each other with the source region of gate tube.
As mentioned above, a kind of high-density phase-change memory structure of the present invention has following beneficial effect: under the prerequisite that does not change the gate tube size, by a plurality of phase transition storages and a gate tube are in series, can improve the density of phase transition storage, obtain high-density phase-change memory.
Description of drawings
Fig. 1 is shown as 11R structural phase transition memory cell schematic diagram.
Fig. 2 is shown as 1TnR structural phase transition memory cell schematic diagram.
Fig. 3 is shown as 1T4R structural phase transition memory cell schematic diagram.
Fig. 4 is shown as phase change resistor and places 1T4R structural phase transition memory cell structure schematic diagram between metal level a and the active area.
Fig. 5 a-5b is shown as phase change resistor and places 1T4R structural phase transition memory cell structure schematic diagram between metal level a and the metal level b.
Fig. 6 is shown as phase change resistor and places 1T5R structural phase transition memory cell structure schematic diagram between metal level a and the metal level b.
Fig. 7 a-7b is shown as phase change resistor and places 1T6R structural phase transition memory cell structure schematic diagram between metal level m-1 and the metal level m.
The element numbers explanation
1 active area
2 grid
3 contact holes
4 the first metal layers
6 through holes
7 second metal levels
8 metal level m-1
9 top layer through holes
10 top layer metallic layer m
BL, BLk, BL0～BLn-1 bit line
R, Rk, R0～Rn-1 phase change resistor
WL word line
The T transistor
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
As shown in Figure 1 be 1T1R structural phase transition memory cell schematic diagram, 1 transistor T and 1 phase change resistor R are in series.The source ground connection of transistor T, grid termination word line WL, drain terminal connects the end of phase change resistor R, another termination bit line BL of phase change resistor R.This is normally used basic structure.
See also Fig. 2 to Fig. 4.Need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also may be more complicated.
As shown in Figure 2, the present invention adopts 1TnR structural phase transition memory cell, and n is greater than 1 and be 1 transistor T of integer and n phase change resistor R0, Rn-1 consists of the phase change memory elementary cell, n phase change resistor R0 ... the end of Rn-1 all links to each other with the drain terminal of transistor T, n phase change resistor R0 ..., the other end of Rn-1 meets bit line BL0 separately, BL1 ... BLn-1.The grid termination word line WL of transistor T.The number of n depends on size and the laying out pattern of transistor T.For the 1T1R structure, n phase change resistor R0 ..., the shared area of Rn-1 is n the area that transistor T is shared, and for 1TnR, n phase change resistor R0 ..., the Rn-1 area occupied is 1 area that transistor T is shared.
When phase-change memory cell is selected, 1 n phase change resistor R0 that transistor T connects ..., Rn-1 can not choose simultaneously, can only select 1 phase change resistor wherein at every turn.In the time will selecting one of them phase change resistor, word line WL conducting, n phase change resistor R0 ..., there is and only has the bit line BL conducting of a connection among the Rn-1, all the other phase change resistors that connect on this transistor T are in suspended state.During gating, word line WL is not in off state, and bit line BL is in suspended state.Table 1 is 1TnR structural phase transition state of memory cells table.BLk is n phase change resistor R0 ..., the bit line of any one among the Rn-1.When any one the phase change resistor Rk in this element is selected, the transistor T conducting that this unit connects, i.e. WL conducting, the bit line BLk conducting of the upper connection of Rk, the bit line that all the other phase change resistors connect all suspends, and has realized the selection to Rk.There is and only has the bit line conducting of 1 phase change resistor.When this phase-change memory cell was not selected, WL closed, n phase change resistor R0 ..., the bit line of Rn-1 is in suspended state.
Table 1
Fig. 3 gets the 1T4R structural phase transition memory cell schematic diagrames that n is 4 formations.In the embodiments of figure 3,1 transistor T and 4 phase change resistor R0, R1, R2 and R3 consist of phase-change memory cell, 4 phase change resistor R0, R1, the end of R2 and R3 is connected to the drain terminal of transistor T, the other end connects bit line BL0 separately, BL1, BL2, BL3, the source ground connection of transistor T, grid termination word line WL.
Fig. 4 is bring to Front memory cell structure schematic diagram between electrode metal layer a and the active area of phase change resistor.Among Fig. 4, the source of transistor T is connected to ground, and the transistor T drain terminal has connected 4 phase change resistor R0, R1, and R2 and R3, these 4 phase change resistor R0, R1, R2 links to each other by the active area of hearth electrode with the transistor T drain terminal with R3.Here being to illustrate take 4 as example, might not be to place 4 phase change resistors, decide according to size and the shared area of phase change resistor of active area.The number of the phase change resistor in the following domain schematic diagram also is like this.
Fig. 5 a is bring to Front memory cell domain structure schematic diagram between electrode metal layer a and the low layer of metal layer b of phase change resistor unit 5.Fig. 5 b is the profile of Fig. 5 a.The source of transistor T is connected to ground among Fig. 5 a, and the transistor T drain terminal has connected 4 phase change resistor R0, R1, and R2 and R3, these 4 phase change resistor R0, R1, R2 links to each other with the active area of transistor T drain terminal by top layer electrode metal layer a with R3.
The preparation process of this memory cell device is as follows:
1) provides semi-conductive substrate, form epitaxial loayer in described Semiconductor substrate;
2) on described epitaxial loayer, form sti structure, active area 1 and gate region 2 and the isolation structure around this gate region according to common process;
3) form the insulating barrier that is provided with contact hole 3;
4) fill the tungsten plug to described contact hole 3;
5) sediment phase change thin-film material;
6) the described phase change film material of etching forms n phase change resistor 5, and n is 4 in the present embodiment;
7) preparation the first metal layer 4 and be etched into bit line;
8) finish remaining interconnection line.
In the present embodiment, described phase change resistor 5 links to each other with the source region of gate tube by hearth electrode between the first metal layer 4 and active area 1.
Fig. 6 is bring to Front memory cell structure schematic diagram between electrode metal layer 4 and the metal level 6 of phase change resistor 5.The source of transistor T is connected to ground among Fig. 6, and the transistor T drain terminal has connected 5 phase change resistor R0, R1, and R2, R3 and R4, these 5 phase change resistor R0, R1, R2, R3 links to each other with the active area 1 of transistor T drain terminal by top layer electrode metal layer 4 with R4.Phase power transformation R0, R1, R2, R3 and R4 bring to Front between electrode metal layer 4 and the metal level 6.Owing between metal level 4 and the metal 6 more space being arranged, and phase change resistor R0, R1, R2, the hearth electrode of R3 and R4 no longer are fixed on directly over the active area 1 of transistor T, can link to each other with active area 1 by metal level 4, so phase change resistor R0, R1, R2, R3 and R4 place the number between metal level 4 and the metal level 6 to place number below the metal level 4 more than phase change resistor 5.
Its preparation technology and embodiment 1 are similar, and gate region 2 is positioned on the active area 1, and contact hole 3 is filled behind the metals together with metal level 4 and active area 1.
Fig. 7 a is that phase change resistor places the memory cell domain structure schematic diagram between multicycle top electrode metal level m-1 and the metal level m.For phase transition storage, the periodicity of multiply periodic top electrode generally is 3 to 8 layers.Metal level m is the top layer electrode metal layer.The source of transistor T is connected to ground among Fig. 7 a, and the transistor T drain terminal has connected 6 phase change resistor R0, R1, R2, R3, R4 and R5, these 6 phase change resistor R0, R1, R2, R3, R4 links to each other with the active area of transistor T drain terminal by metal level m-1 and the following metal of metal level m-1 thereof with R5.Phase change resistor R places between metal level m and the metal level m-1.Because during to metal level m-1, a lot of wirings are all finished, between metal m and the metal m-1 more space is arranged, and phase change resistor R0, R1, R2, R3, the hearth electrode of R4 and R5 no longer is fixed on directly over the active area of transistor T, can link to each other with active area by the following metal level of metal m-1 and metal m-1, so place phase change resistor R the number between metal m and the metal m-1 to place the following number of metal 1 more than phase change resistor R.
See also shown in Fig. 7 b, a kind of high-density phase-change memory device architecture, this phase-change memory device structure comprises n phase change resistor 5 and Semiconductor substrate; Be positioned at the epitaxial loayer on this Semiconductor substrate; The sti structure that is positioned at the active area 1 on this epitaxial loayer and is used for isolating described active area; Be positioned at gate region 2 and the isolation structure around this gate region on the described active area 1; Be positioned at the insulating barrier on active area, gate region and the sti structure; Be arranged at the contact hole 3 in the insulating barrier; Be positioned at the metal level on the insulating barrier; Be filled with metal in the described contact hole 3 and be used for connecting described metal level and active area 1;
In the present embodiment, metal level comprises the first metal layer 4 and is located at the second metal level 7 on the described the first metal layer 4 and connects described the first metal layer and the through hole 6 of this second metal level.Also be provided with m-1 layer metal level 8 and m metal level 10 adjacent with described m-1 layer metal level 8 and that be located thereon on described the second metal level, and the top layer through hole 9 that connects these two metal levels.Described phase change resistor links to each other with the source region of gate tube by m metal level 10 between m-1 layer metal level 8 and m metal level.The m metal level is top layer metallic layer.
Among the present invention, described phase change resistor 5 is arbitrarily between the two-layer adjacent metal level, and the metal level by low one deck links to each other with the source region of gate tube.
In sum, the present invention relates to a kind of being in series with a plurality of phase change resistors and a gate tube and consist of high-density phase-change memory structure and the structure thereof of phase-change memory cell, purpose is under the prerequisite that does not change the gate tube size, improves the density of phase transition storage.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can be under spirit of the present invention and category, and above-described embodiment is modified or changed.Therefore, have in the technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of finishing under disclosed spirit and the technological thought, must be contained by claim of the present invention.
Claims (7)
1. high-density phase-change memory circuit structure, it is characterized in that: described phase change memory structure comprises gate tube and n phase change resistor, the source ground connection of described gate tube, grid termination word line WL; A described n phase change resistor is arranged side by side, and respectively an end of this phase change resistor is connected to the drain terminal of described gate tube jointly, and respectively the other end of this phase change resistor connects respectively bit line separately, and wherein n is integer, n＞=2.
2. a kind of high-density phase-change memory structure according to claim 1, it is characterized in that: the value of n is 4～6.
3. a kind of high-density phase-change memory structure according to claim 1, it is characterized in that: described gate tube is metal-oxide-semiconductor, diode or triode.
4. high-density phase-change memory device architecture preparation method, it is characterized in that: the method may further comprise the steps:
1) provides semi-conductive substrate, form epitaxial loayer in described Semiconductor substrate;
2) on described epitaxial loayer, form sti structure, active area and gate region and the isolation structure around this gate region according to common process;
3) form the insulating barrier that is provided with contact hole;
4) fill the tungsten plug to described contact hole;
5) sediment phase change thin-film material;
6) the described phase change film material of etching forms n phase change resistor, and wherein n is integer, n＞=2;
7) preparation metal level and be etched into bit line;
8) prepare all the other metal levels interconnected.
5. high-density phase-change memory device architecture preparation method according to claim 4, it is characterized in that: the value of n is 4～6 in the described step 6).
6. high-density phase-change memory device architecture, it is characterized in that: this phase-change memory device structure comprises n phase change resistor and Semiconductor substrate;
Be positioned at the epitaxial loayer on this Semiconductor substrate;
The sti structure that is positioned at the active area on this epitaxial loayer and is used for isolating described active area;
Be positioned at gate region and the isolation structure around this gate region on the described active area;
Be positioned at the insulating barrier on active area, gate region and the sti structure;
Be arranged at the contact hole in the insulating barrier;
Be positioned at the some metal levels on the insulating barrier;
Be filled with metal in the described contact hole and be used for connecting described metal level and active area;
Described phase change resistor links to each other with the source region of gate tube by hearth electrode between the first metal layer and active area.
7. high-density phase-change memory device architecture, it is characterized in that: this phase-change memory device structure comprises n phase change resistor and Semiconductor substrate;
Be positioned at the epitaxial loayer on this Semiconductor substrate;
The sti structure that is positioned at the active area on this epitaxial loayer and is used for isolating described active area;
Be positioned at gate region and the isolation structure around this gate region on the described active area;
Be positioned at the insulating barrier on active area, gate region and the sti structure;
Be arranged at the contact hole in the insulating barrier;
Be positioned at the some metal levels on the insulating barrier;
Be filled with metal in the described contact hole and be used for connecting described metal level and active area;
Described phase change resistor is arbitrarily between the two-layer adjacent metal level, and the metal level by low one deck links to each other with the source region of gate tube.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104716259A (en) * | 2013-12-13 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | Three-dimensional multi-layer resistive random access memory |
| CN110635026A (en) * | 2019-08-15 | 2019-12-31 | 北京大学 | Preparation method of 1TnR storage and calculation array unit |
| CN110718569A (en) * | 2019-09-02 | 2020-01-21 | 北京大学 | 1T2R memory cell based on resistive random access memory and preparation method thereof |
| CN110943102A (en) * | 2019-11-12 | 2020-03-31 | 华中科技大学 | High-density phase change memory three-dimensional integrated circuit structure |
| CN113380298A (en) * | 2021-05-07 | 2021-09-10 | 中国科学院上海微系统与信息技术研究所 | Nonvolatile Boolean logic two-bit multiplier and operation method |
| WO2023221220A1 (en) * | 2022-05-18 | 2023-11-23 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US11948616B2 (en) | 2021-11-12 | 2024-04-02 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104716259A (en) * | 2013-12-13 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | Three-dimensional multi-layer resistive random access memory |
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| WO2023221220A1 (en) * | 2022-05-18 | 2023-11-23 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
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Application publication date: 20130213 |