WO2021102750A1

WO2021102750A1 - Spin logic device, circuit, control method and processing apparatus

Info

Publication number: WO2021102750A1
Application number: PCT/CN2019/121323
Authority: WO
Inventors: 秦健鹰
Original assignee: 华为技术有限公司
Priority date: 2019-11-27
Filing date: 2019-11-27
Publication date: 2021-06-03
Also published as: CN114641867A

Abstract

A spin logic device, relating to the technical field of circuits. The spin logic device comprises a first ferromagnetic layer, a first potential barrier layer, a fixed layer, a second potential barrier layer and a second ferromagnetic layer, which are successively arranged in a stacked manner, wherein the first ferromagnetic layer and the second ferromagnetic layer comprise a magnetic material; the first potential barrier layer and the second potential barrier layer comprise a metal oxide material; and the magnetization direction of the fixed layer is a fixed direction. The logic device relies on a magnetic tunnel junction and achieves a low current density, a high operating speed and low power consumption. The present invention further relates to a spin logic circuit, a control method and a processing apparatus.

Description

Spin logic device and spin logic circuit

Technical field

The embodiments of the present application relate to the field of circuit technology, and in particular, to a spin logic device and a spin logic circuit.

Background technique

Spin logic device is a kind of logic device proposed based on the magnetic moment dynamics process of the magnetic unit. It can significantly improve the work efficiency while limiting the power consumption to a low level, so it has been widely studied.

A spin logic device in the prior art can realize magnetic moment reversal based on the spin Hall effect. For example, a perpendicularly magnetized magnetic tunnel junction (MTJ) is placed on a cross-shaped heavy metal electrode, and two currents are passed through the electrodes perpendicular to each other, which are two input channels. By adjusting the input directions of the two currents and applying an auxiliary external magnetic field, 4 or more logic resistance states can be realized.

However, logic devices working with this method need the assistance of an external magnetic field to reverse the magnetic moment. This may affect the periphery of the device in a Complementary Metal-Oxide-Semiconductor (CMOS) circuit. The normal function of the work area, the greater the degree of dispersion of the magnetic field, which affects the close packing of the MTJ and reduces the storage density; moreover, when the magnetic moment is reversed based on the spin Hall effect, the applied current density is larger, the thermal effect and the power consumption Higher.

Summary of the invention

The embodiments of the present application provide a spin logic device and a spin logic circuit, which can utilize the voltage controlled magnetic anisotropy (Voltage Controlled Magnetization Anisotropy, VCMA) effect and the spin transfer torque (Spin Transfer Torque, STT) effect to realize the magnetic moment Flip, effectively reduce power consumption, speed up calculations, and improve operating efficiency.

In order to achieve the foregoing objectives, the following technical solutions are adopted in the embodiments of this application:

In a first aspect of the embodiments of the present application, a spin logic device is provided. The spin logic device includes a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, and a Two ferromagnetic layers, wherein: the first ferromagnetic layer and the second ferromagnetic layer comprise magnetic materials; the first barrier layer and the second barrier layer comprise metal oxide materials; the magnetization direction of the pinned layer is Fixed direction. Based on this solution, the first ferromagnetic layer, the first barrier layer and the pinned layer in the spin logic device can form the first MTJ, and the pinned layer, the second barrier layer and the second ferromagnetic layer can form the second MTJ. That is, the structure of the spin logic device includes two MTJs, so that when voltage pulses are input to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, the first ferromagnetic layer can be realized based on the VCMA effect and the STT effect. The magnetic moment of the second ferromagnetic layer and the second ferromagnetic layer are reversed, so that the first MTJ and the second MTJ can exhibit different resistance values, so that the spin logic device can exhibit different resistance states to implement logic operations. It is understandable that when the spin logic device implements magnetic moment reversal based on the VCMA effect and the STT effect, there is no need to introduce an external magnetic field, and therefore, the normal function of the working area around the device will not be affected. Moreover, when the magnetic moment reversal of the spin logic device is realized through the VCMA effect and the STT effect, the current is small, the power consumption is low, and the operating efficiency is improved.

With reference to the first aspect, in a possible implementation manner, the above-mentioned fixed layer includes a first sub-layer, a second sub-layer, a third sub-layer, a fourth sub-layer, and a fifth sub-layer that are stacked in sequence, wherein: The first sublayer and the fifth sublayer include magnetic materials; the second sublayer and the fourth sublayer include metal non-magnetic materials or alloy non-magnetic materials; the third sublayer includes a magnetic multilayer film [A _x / B _y ] _n , where A is a ferromagnetic metal element, B is a heavy metal element, x is the thickness of A, y is the thickness of B, and n is the number of periods _{of [A x} /B _{y ];} The first sublayer forms an antiferromagnetic coupling, and the third sublayer and the fifth sublayer form an antiferromagnetic coupling. Based on this solution, the coercive force of the pinned layer can be significantly higher than the coercive force of the first ferromagnetic layer and the second ferromagnetic layer by stacking five sublayers in sequence, so that the magnetic moment direction of the pinned layer is a fixed direction, The direction of the magnetic moment of the first ferromagnetic layer and the second ferromagnetic layer will be reversed depending on the input voltage. It can be understood that once the direction of the magnetic moment of the pinned layer is determined to be upward or downward during film deposition, the direction of the magnetic moment of the pinned layer will no longer change during the normal operation of the spin logic device.

Combining the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the foregoing A is one of cobalt, iron, and nickel, and the foregoing B is one of platinum, palladium, ruthenium, and tantalum. Based on this solution, the third sublayer can be a magnetic multilayer film, and the ratio of x, y and n can make the third sublayer have perpendicular anisotropy.

Combining the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the spin logic device further includes a first electrode, which conducts electricity between the first electrode and the third sublayer in the pinned layer. Contact, and the first electrode is isolated from the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer. Based on this solution, the first electrode is only in conductive contact with the third sublayer, and is in contact with the first sublayer, the second sublayer, the fourth sublayer, the fifth sublayer, the first ferromagnetic layer, and the first barrier layer. , The second barrier layer and the second ferromagnetic layer are separated by an insulating layer to prevent leakage.

Combining the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the foregoing magnetic material includes cobalt, iron, cobalt iron, cobalt iron boron, iron boron, cobalt platinum, nickel iron, cobalt palladium, cobalt nickel One or more combinations of cobalt and ruthenium. Based on this solution, the thickness of the magnetic material can make the magnetic moments in the first ferromagnetic layer, the second ferromagnetic layer, the first sublayer, and the fifth sublayer have perpendicular anisotropy.

Combining the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the foregoing metal oxide material includes magnesium oxide, aluminum oxide, zinc oxide, magnesium aluminum oxide compound MgAlOx (for example, MgAl ₂ Ox, MgAl ₂ O ₄ ), one of hafnium oxide. Based on this solution, the first barrier layer and the second barrier layer are insulating barrier layers.

Combining the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the shape of the spin logic device is cylindrical or elliptical. Based on this solution, the shape of the spin logic device can be cylindrical or elliptical.

In a second aspect of the embodiments of the present application, a spin logic circuit is provided. The spin logic circuit includes: a first controller, a spin logic device, and a read circuit; the spin logic device includes: a first ferromagnetic Layer, a first barrier layer, a pinned layer, a second barrier layer, a second ferromagnetic layer, and a first electrode; wherein the first ferromagnetic layer and the second ferromagnetic layer include a magnetic material; the first The barrier layer and the second barrier layer include a metal oxide material; the magnetization direction of the pinned layer is a fixed direction; the first electrode is in conductive contact with the pinned layer, and the first electrode is in contact with the first ferromagnetic material. Layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer are separated by an insulating layer; the first controller is used for grounding the first electrode, and is connected to the first iron A first voltage pulse and a second voltage pulse are input between the magnetic layer and the first electrode, and a third voltage pulse and a fourth voltage pulse are input between the second ferromagnetic layer and the first electrode; the first voltage pulse And the third voltage pulse is greater than the critical switching voltage, the second voltage pulse and the fourth voltage pulse are less than the critical switching voltage, and the critical switching voltage is the voltage at which the magnetic moment of the first ferromagnetic layer or the second ferromagnetic layer is inverted; The reading circuit is used to read the resistance value of the spin logic device and convert the resistance value of the spin logic device into a corresponding logic signal. Based on this solution, by inputting voltage pulses in the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, the magnetic moment reversal of the first ferromagnetic layer and the second ferromagnetic layer is realized based on the VCMA effect and the STT effect, The spin logic device can present different resistance states to realize a variety of logic operations. When the method is based on the VCMA effect and the STT effect to realize the magnetic moment reversal of the spin logic device, the current is small, the power consumption can be reduced, the calculation speed is accelerated, and the operating efficiency is improved.

With reference to the second aspect, in a possible implementation manner, the above-mentioned reading circuit includes: a second controller and a comparator, and the second controller is used to turn off the grounding setting of the above-mentioned first electrode, and in the above-mentioned automatic The first ferromagnetic layer and the second ferromagnetic layer of the spin logic device are inputted with a read voltage to read the resistance value of the spin logic device; the comparator is used to compare the resistance value of the spin logic device and The resistance value of the reference resistor is preset to output the corresponding logic signal. Based on this solution, by reading the resistance state of the spin logic device and comparing it with the comparator to output the corresponding logic signal, it is possible to implement, for example, logic NOR (NOR) operation and logic NAND (NAND) operation , And logical NOT operation.

Combining the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the above-mentioned reading circuit further includes: an inverter for inverting the logic signal output by the above-mentioned comparator . Based on this solution, by inverting the logic signal output by the comparator, for example, a logical OR (OR) operation, a logical AND (AND) operation, and a logical yes gate (BUF) operation can be realized.

Combining the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the resistance value of the preset reference resistor is greater than the resistance value R _{Mid of} the spin logic device in the intermediate resistance state and less than the spin logic device. _{The resistance value R High of the} device in the high resistance state, or the resistance value of the preset reference resistance is greater than the resistance value R _{Low of} the spin logic device in the low resistance state and less than the resistance value of the spin logic device in the intermediate resistance state R _Mid ; wherein, when the spin logic device is the resistance R _Mid of the intermediate resistance state, the direction of the magnetic moment of the first ferromagnetic layer and the pinned layer, and the magnetic moment of the second ferromagnetic layer and the pinned layer Among the directions, only one set is in the parallel state; when the spin logic device is in the high resistance state with a resistance value R _High , the magnetic moment directions of the first ferromagnetic layer, the pinned layer, and the second ferromagnetic layer are adjacent to each other. The two layers are in an anti-parallel state; when the spin logic device is in a low resistance state with a resistance value R _Low , the magnetic moment directions of the first ferromagnetic layer, the pinned layer, and the second ferromagnetic layer are two adjacent to each other. The layers are parallel. Based on this solution, the resistance of the preset reference resistor can be between R _Mid and R _High , or between R _Low and R _Mid . It is understandable that when the resistance value of the preset reference resistor is different, different logic operations can be implemented according to the difference of the input second voltage pulse and/or the fourth voltage pulse.

Combining the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the spin logic circuit is configured to perform logical AND gate (AND), logical OR gate (OR), logic is gate (BUF), logic NAND gate (NAND), logic NOR gate (NOR) or logic NOT gate (NOT). Based on this scheme, logic operations such as AND gates, OR gates, yes gates, NAND gates, NOR gates and NOT gates can be realized.

A third aspect of the embodiments of the present application provides a control method based on a spin logic device. The spin logic device includes: a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, and a second barrier layer. Two ferromagnetic layers, and a first electrode; wherein, the first ferromagnetic layer and the second ferromagnetic layer include a magnetic material; the first barrier layer and the second barrier layer include a metal oxide material; The magnetization direction of the layer is a fixed direction; the first electrode is in conductive contact with the fixed layer, and the first electrode is in contact with the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the first The two ferromagnetic layers are separated by an insulating layer; the above method includes: grounding the first electrode, and inputting a first voltage pulse and a second voltage pulse between the first ferromagnetic layer and the first electrode, respectively, A third voltage pulse and a fourth voltage pulse are input between the second ferromagnetic layer and the first electrode; the first voltage pulse and the third voltage pulse are greater than the critical switching voltage, the second voltage pulse and the fourth voltage The pulse is smaller than the above-mentioned critical switching voltage, which is the voltage at which the magnetic moment of the above-mentioned first ferromagnetic layer or the above-mentioned second ferromagnetic layer is inverted; the resistance value of the above-mentioned spin logic device is read and the above-mentioned spin logic device The resistance value is converted into the corresponding logic signal.

With reference to the third aspect, in a possible implementation manner, the reading of the resistance value of the spin logic device and converting the resistance value of the spin logic device into a corresponding logic signal includes: turning off the first electrode The grounding setting of the spin logic device, and the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, input a read voltage, read the resistance value of the spin logic device; compare the resistance of the spin logic device Value and the resistance value of the preset reference resistor to output the corresponding logic signal.

In combination with the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the foregoing method further includes: inverting the foregoing logic signal.

Combining the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the resistance value of the preset reference resistor is greater than the resistance value R _{Mid of} the spin logic device in the intermediate resistance state and less than the spin logic device. _{The resistance value R High of the} device in the high resistance state, or the resistance value of the preset reference resistance is greater than the resistance value R _{Low of} the spin logic device in the low resistance state and less than the resistance value of the spin logic device in the intermediate resistance state R _Mid ; wherein, when the spin logic device is the resistance R _Mid of the intermediate resistance state, the direction of the magnetic moment of the first ferromagnetic layer and the pinned layer, and the magnetic moment of the second ferromagnetic layer and the pinned layer Among the directions, only one set is in the parallel state; when the spin logic device is in the high resistance state with a resistance value R _High , the magnetic moment directions of the first ferromagnetic layer, the pinned layer, and the second ferromagnetic layer are adjacent to each other. The two layers are in an anti-parallel state; when the spin logic device is in a low resistance state with a resistance value R _Low , the magnetic moment directions of the first ferromagnetic layer, the pinned layer, and the second ferromagnetic layer are two adjacent to each other. The layers are parallel.

Combining the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the spin logic device is configured to perform logical AND gates (AND), logical OR gates (OR), logic yes gates (BUF), Logic NAND gate (NAND), NOR gate (NOR) or logic NOT gate (NOT).

For the description of the effects of the foregoing third aspect and various implementation manners of the third aspect, reference may be made to the description of the corresponding effects of the second aspect and various implementation manners of the second aspect, and details are not repeated here.

In a fourth aspect of the embodiments of the present application, a processing device is provided. The processing device includes a memory and at least one spin logic circuit as described in the above second aspect, and the at least one spin logic circuit is respectively connected to the memory coupling.

Description of the drawings

FIG. 1 is a schematic structural diagram of a spin logic device provided by an embodiment of the application;

2 is a schematic structural diagram of a fixed layer in a spin logic device provided by an embodiment of the application;

3 is a schematic structural diagram of another spin logic device provided by an embodiment of the application;

4 is a schematic diagram of the magnetic moment direction in a spin logic device provided by an embodiment of this application;

5 is a schematic diagram of the magnetic moment direction in another spin logic device provided by an embodiment of the application;

6 is a schematic diagram of the correspondence between the magnetic moment direction of a spin logic device and the resistance state of the spin logic device according to an embodiment of the application;

FIG. 7 is a schematic flowchart of a control method based on a spin logic device according to an embodiment of the application;

FIG. 8 is an application schematic diagram of a control method based on a spin logic device provided by an embodiment of the application;

FIG. 9 is an application schematic diagram of another control method based on a spin logic device provided by an embodiment of the application;

FIG. 10 is a schematic flowchart of another control method based on a spin logic device according to an embodiment of the application;

FIG. 11 is an application schematic diagram of another control method based on a spin logic device provided by an embodiment of the application;

FIG. 12 is a schematic diagram of implementing a logic NOR gate in a control method based on a spin logic device according to an embodiment of the application; FIG.

FIG. 13 is a schematic diagram of implementing a logic NAND gate in a control method based on a spin logic device according to an embodiment of the application; FIG.

FIG. 14 is a schematic diagram of a control method based on a spin logic device provided by an embodiment of the application to implement a logic NOT gate;

15 is a schematic diagram of another spin logic device-based control method provided by an embodiment of the application to implement a logic NOT gate;

16 is an application schematic diagram of another spin logic device-based control method provided by an embodiment of the application;

FIG. 17 is a schematic diagram of implementing a logic OR gate in a control method based on a spin logic device according to an embodiment of the application; FIG.

FIG. 18 is a schematic diagram of a control method based on a spin logic device provided by an embodiment of the application to implement a logic AND gate;

FIG. 19 is a schematic diagram of a control method based on a spin logic device provided by an embodiment of the application to realize a logic gate;

20 is a schematic diagram of another spin logic device-based control method provided by an embodiment of the application to implement a logic OR gate;

FIG. 21 is a schematic structural diagram of a spin logic circuit provided by an embodiment of the application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In this application, "at least one" refers to one or more, and "multiple" refers to two or more. "And/or" describes the association relationship of the associated objects, indicating that there can be three relationships, for example, X and/or Y, which can mean: X exists alone, X and Y exist at the same time, and Y exists alone, where X, Y can be singular or plural. "The following at least one item (a)" or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a). For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c or a and b and c, where a, b and c can be It can be single or multiple.

It should be noted that in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or illustrations. Any embodiment or design solution described as "exemplary" or "for example" in this application should not be construed as being more preferable or advantageous than other embodiments or design solutions. To be precise, words such as "exemplary" or "for example" are used to present related concepts in a specific manner.

It should be noted that the magnetic moment directions of the ferromagnetic layer and the pinned layer in the embodiments of the present application are parallel (or the magnetic moment directions of the ferromagnetic layer and the pinned layer are parallel), which refers to the magnetic moment direction of the ferromagnetic layer and the pinned layer. The magnetic moment direction of the ferromagnetic layer and the pinned layer are the same, and the magnetic moment directions of the ferromagnetic layer and the pinned layer are antiparallel (or, the magnetic moment directions of the ferromagnetic layer and the pinned layer are antiparallel) refer to the magnetic moment direction of the ferromagnetic layer and the pinned layer. The moments are in the opposite direction.

First, the terms involved in the embodiments of the present application are explained.

Magnetic tunnel junction MTJ: It is a "sandwich" structure in which two ferromagnetic layers are separated by an insulating barrier layer. When the magnetic moment directions of the two ferromagnetic layers are parallel to each other, the vertical tunneling resistance of the entire tunnel junction is at a low level. When the magnetic moment directions of the two ferromagnetic layers are anti-parallel, they are in a state of high resistance. The high and low resistance states of the tunnel junction can realize different logic operations.

Voltage-controlled magnetic anisotropy VCMA effect: refers to the phenomenon that the magnetism of a substance is adjusted with the direction by voltage. In the MTJ, the magnetic moment of the ferromagnetic layer 180 to be achieved if the flip (flat shape and antiparallel state between), the process of flipping to overcome the potential barrier E _b, E _b is the thermal stability of the MTJ decision of Δ Important indicators. For the MTJ with perpendicular magnetization of the magnetic moment, a voltage drop is introduced at both ends of the MTJ. Due to the charge accumulation between the barrier layer and the ferromagnetic layer, the magnetic anisotropy of the ferromagnetic layer will gradually decrease until the magnetic moment is at Under the action, an in-plane arrangement is formed, and the perpendicular magnetic anisotropy disappears completely, that is, the VCMA effect. At this time, the potential barrier E _b of the magnetic moment flip is 0. It should be noted that the final action form of the VCMA effect is to make the magnetic moment of the ferromagnetic layer in the perpendicularly magnetized MTJ arranged in the plane, which cannot achieve the determination of 180° Sex flip. The above function works by applying a voltage across the MTJ to form an electric field across the internal barrier layer of the MTJ. The amplitude of the current passing through the MTJ can be small, so the overall power consumption of the device can be significantly reduced. Conducive to the practical application of spin logic devices.

The spin transfer torque STT effect refers to the phenomenon that the current in the magnetic multilayer film manipulates the magnetic moment. The STT effect can control the magnetization direction of the magnetic film by the current without the need for an external magnetic field. Only the STT effect can cause the magnetic moment in the MTJ to have a 180° deterministic reversal. The voltage drop applied across the MTJ corresponding to the STT intensity required to make the magnetic moment 180° deterministic inversion is called the critical switching voltage V _c . Different from the VCMA effect, the STT effect relies on the current passing through the MTJ to work. Therefore, the MTJ that only relies on the STT effect to work has greater power consumption. It needs to be pointed out that the 180° deterministic reversal of the magnetic moment driven by the STT effect is divided into two stages: the first stage, the magnetic moment flips from 0° to 90°; the second stage, the magnetic moment flips from 90° to 90° 180°. The power consumption caused by the magnetic moment flipping from 0° to 90° is much larger than the power loss caused by the magnetic moment flipping from 90° to 180°. Therefore, the power consumption of the magnetic moment flipping caused by the STT effect is mainly concentrated in the first stage. In the embodiment of the application, the magnetic moment is flipped from 0° to 90° through the VCMA effect (the first stage), and the magnetic moment is flipped from 90° to 180° through the STT effect. Therefore, the VCMA effect and the STT effect are combined to achieve the magnetic moment flip. When the power consumption is low, the operating efficiency of the spin logic device can be improved.

It should be noted that the spin transfer torque STT effect in the embodiments of the present application may also be referred to as the spin transfer torque STT effect or the spin torque STT effect.

Exemplarily, when a first voltage drop higher than the critical switching voltage V _c is applied to the MTJ, the direction of the magnetic moment is in-plane, and then when the voltage drop is reduced to a second voltage drop _{below the critical switching voltage V c,} The magnetic moment in the in-plane orientation is reversed under the action of the STT current. For the process of reciprocating reversal between the flat state and the anti-parallel state, the polarity of the first voltage drop does not change, while the polarity of the second voltage drop is related to the reversal direction.

In order to reduce the power consumption of the spin logic device, accelerate the operation speed, and improve the operation efficiency, a spin logic device according to the embodiment of the present application has low current density, high operation speed, and power when implementing logic operations. Low consumption.

As shown in FIG. 1, a spin logic device provided by an embodiment of this application, the spin logic device includes a first ferromagnetic layer, a first barrier layer, a fixed layer, and a second barrier layer that are stacked in sequence. , And the second ferromagnetic layer. For example, as shown in FIG. 1, the spin logic device includes from top to bottom: a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, and a second ferromagnetic layer.

Wherein, the first ferromagnetic layer and the second ferromagnetic layer comprise magnetic materials. The magnetic material may include one or more combinations of cobalt, iron, cobalt iron, cobalt iron boron, iron boron, cobalt platinum, nickel iron, cobalt palladium, cobalt nickel, and cobalt ruthenium. For example, the first ferromagnetic layer and the second ferromagnetic layer may be made of magnetic materials with perpendicular anisotropy such as Co, Fe, CoFe, CoFeB, FeB, or a combination thereof. The first ferromagnetic layer and the second ferromagnetic layer The thickness of the layer can support the magnetic moment in the first ferromagnetic layer and the second ferromagnetic layer to have perpendicular anisotropy.

The first barrier layer and the second barrier layer include a metal oxide material. Exemplarily, the metal oxide material includes one of magnesium oxide, aluminum oxide, zinc oxide, magnesium aluminum oxide compound MgAlOx (for example, MgAl ₂ Ox, MgAl ₂ O ₄ ), and hafnium oxide. For example, the first barrier layer and the second barrier layer may be made of metal oxides such as MgO, AlOx, MgAlOx, etc., and the first barrier layer and the second barrier layer are insulating barrier layers.

The magnetization direction of the above-mentioned pinned layer is a fixed direction. For example, the magnetization direction of the pinned layer is upward or downward. The coercivity of the pinned layer is significantly higher than the coercivity of the first ferromagnetic layer and the second ferromagnetic layer.

In one implementation, the fixed layer may be a composite layer of a multilayer film, the magnetic moment of which has perpendicular anisotropy. As shown in FIG. 2, the fixed layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked in sequence.

Wherein, the first sub-layer and the fifth sub-layer include magnetic materials. Exemplarily, the above-mentioned first sublayer and fifth sublayer may be made of Co, Fe, CoFe, CoFeB, FeB, and other magnetic materials with perpendicular anisotropy or a combination thereof, and the thickness of the first sublayer and the fifth sublayer may support the first sublayer and the second sublayer. The magnetic moments in the five sublayers have perpendicular anisotropy.

The second sub-layer and the fourth sub-layer include metallic non-magnetic materials or alloy non-magnetic materials. For example, the second sub-layer and the fourth sub-layer may be made of metal non-magnetic materials or alloy non-magnetic materials such as PtMn, IrMn, Ru, Ta, Pd.

The third sublayer includes a magnetic multilayer film [A _x /B _y ] _n , where A is a ferromagnetic metal element, B is a heavy metal element, x is the thickness of A, y is the thickness of B, and n is [A _x / The number of cycles of _{B y ].} [A _x /B _y ] _n indicates that in the film preparation process, in the direction perpendicular to the film surface, x-thick A and y-thick B films are alternately prepared. Exemplarily, A may be one of cobalt, iron, and nickel, and B may be one of platinum, palladium, ruthenium, and tantalum. For example, the third sublayer may be a magnetic multilayer film [Co _x /Pt _y ] _n , and the ratio of x, y and n may make the third sublayer have perpendicular anisotropy.

Exemplarily, as shown in FIG. 3, the above-mentioned spin logic device further includes a first electrode, and the first electrode is in conductive contact with the third sublayer in the fixed layer, and is used between other sublayers in the fixed layer. The insulating layer is isolated, and the first electrode is isolated from the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer. As shown in Figure 3, the first electrode is only in conductive contact with the third sub-layer, and is in contact with the first sub-layer, the second sub-layer, the fourth sub-layer, the fifth sub-layer, the first ferromagnetic layer, and the first potential. The barrier layer, the second barrier layer and the second ferromagnetic layer are separated by an insulating layer to prevent leakage.

Exemplarily, the thickness and composition of the second sublayer can make the first sublayer and the third sublayer form an antiferromagnetic coupling, and the thickness and composition of the fourth sublayer can make the third sublayer and the fifth sublayer form an antiferromagnetic coupling. An antiferromagnetic coupling is formed between the sublayers. Due to the existence of antiferromagnetic coupling between the first sublayer and the third sublayer, and between the third sublayer and the fifth sublayer, the magnetic moment directions of the first sublayer and the third sublayer are antiparallel. The magnetic moment directions of the third and fifth sublayers are also antiparallel. The direction of the magnetic moment of the pinned layer is consistent with the first and fifth sublayers.

For example, as shown in Figure 4, the magnetic moment direction of the third sublayer is downward, the magnetic moment direction of the first sublayer is upward, and the magnetic moment direction of the fifth sublayer is also upward. The directions of the magnetic moments of the three sub-layers are anti-parallel, and the directions of the magnetic moments of the third sub-layer and the fifth sub-layer are also anti-parallel. The direction of the magnetic moment of the pinned layer is consistent with the first and fifth sublayers, and is upward.

For another example, as shown in FIG. 5, the magnetic moment direction of the third sublayer is upward, the magnetic moment direction of the first sublayer is downward, and the magnetic moment direction of the fifth sublayer is also downward, that is, the first sublayer The direction of the magnetic moment of the third sub-layer is anti-parallel, and the direction of the magnetic moment of the third sub-layer and the fifth sub-layer are also anti-parallel. The direction of the magnetic moment of the pinned layer is the same as that of the first sublayer and the fifth sublayer, and is downward.

V1 and V2 in Figures 4 and 5 are input voltages. By inputting voltages V1 and V2 to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, respectively, the first ferromagnetic layer and the second ferromagnetic layer can be The magnetic moment of the ferromagnetic layer is reversed. As shown in Figures 4 and 5, the direction of the magnetic moment of the first ferromagnetic layer and the direction of the magnetic moment of the second ferromagnetic layer are different depending on the polarity of the input voltage, which may be upward or downward, while the direction of magnetic moment of the fixed layer Will not change.

It can be understood that the direction of the magnetic moment of the above-mentioned pinned layer has been determined during film deposition, or annealing after film preparation, or annealing after film preparation into MTJ devices, as shown in Figs. 4 and 5, this The direction of the magnetic moment of the pinned layer can be upward or downward. It should be noted that once the magnetic moment direction of the pinned layer is determined to be up or down during film deposition (or annealing after film preparation, or annealing after film preparation into MTJ devices), spin logic devices work normally During the process, the direction of the magnetic moment of the pinned layer will not change any more. That is to say, when the spin logic device is destroyed, the orientation of the pinned layer may change, which is different from the magnetic properties determined during film deposition (or annealing after film preparation, or annealing after film preparation into MTJ devices). The moment directions are inconsistent.

Exemplarily, the shape of the spin logic device is cylindrical or elliptical. The embodiment of the present application does not limit the specific shape of the spin logic device, and is only an exemplary description here.

In combination with the spin logic device shown in FIGS. 3 to 5 above, it can be seen that the first ferromagnetic layer, the first barrier layer, and the pinned layer in the spin logic device can form a first MTJ, a pinned layer, and a second barrier layer. The layer and the second ferromagnetic layer may constitute a second MTJ. That is, the structure of the spin logic device can form two MTJs, so that when the magnetic moment directions of the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device change, the first MTJ and the second MTJ can be different. Therefore, the spin logic device can exhibit different resistance states.

Exemplarily, when the magnetic moment directions of the first ferromagnetic layer and the pinned layer are parallel, and the magnetic moment directions of the second ferromagnetic layer and the pinned layer are anti-parallel, the resistance of the first MTJ is lower and the second The resistance of the MTJ is relatively high, so the spin logic device is in an intermediate resistance state, and the resistance of the intermediate resistance state can be denoted as R _Mid . When the direction of the magnetic moment of the first ferromagnetic layer and the pinned layer is antiparallel, and the direction of the magnetic moment of the second ferromagnetic layer and the pinned layer are parallel, the resistance of the first MTJ is higher, and the resistance of the second MTJ Is lower, so the spin logic device is also in the intermediate resistance state. That is, when only one of the magnetic moment directions between the first ferromagnetic layer and the pinned layer and the second ferromagnetic layer and the pinned layer is in a parallel state, the resistance of the spin logic device is R _Mid .

For example, as shown in (a) of FIG. 6, the magnetic moment direction of the pinned layer is downward as an example. When the magnetic moment direction of the first ferromagnetic layer (upward) and the magnetic moment direction of the pinned layer (downward) are antiparallel, and the magnetic moment direction of the second ferromagnetic layer (downward) and the magnetic moment direction of the pinned layer (toward Bottom) When parallel, the resistance R _Total of the spin logic device is in the intermediate resistance state R _Mid . When the direction of the magnetic moment of the first ferromagnetic layer (downward) and the direction of the magnetic moment of the fixed layer (downward) are parallel, and the direction of the magnetic moment of the second ferromagnetic layer (upward) and the direction of the magnetic moment of the fixed layer (downward) ) When anti-parallel, the resistance R _{Total of the} spin logic device is also in the intermediate resistance state R _Mid .

As another example, as shown in (b) of FIG. 6, the magnetic moment direction of the pinned layer is upward as an example. When the direction of the magnetic moment of the first ferromagnetic layer (upward) and the direction of the magnetic moment of the pinned layer (up) are parallel, and the direction of the magnetic moment of the second ferromagnetic layer (down) and the direction of the magnetic moment of the pinned layer (up) are opposite When parallel, the resistance R _Total of the spin logic device is in the intermediate resistance state R _Mid . When the direction of the magnetic moment of the first ferromagnetic layer (downward) and the direction of the magnetic moment of the pinned layer (up) are antiparallel, and the direction of the magnetic moment of the second ferromagnetic layer (up) and the direction of the magnetic moment of the pinned layer (up) When parallel, the resistance R _{Total of the} spin logic device is also in the intermediate resistance state R _Mid .

Exemplarily, when the magnetic moment directions of the first ferromagnetic layer and the pinned layer are parallel, and the magnetic moment directions of the second ferromagnetic layer and the pinned layer are also parallel, the resistance of the first MTJ is lower and the second The resistance value of the MTJ is also low, so the spin logic device is in a low resistance state, and the resistance value of the low resistance state can be denoted as R _Low . That is, in the magnetic moment directions of the first ferromagnetic layer, the fixed layer, and the second ferromagnetic layer, when two adjacent layers are in a parallel state, the resistance of the spin logic device is R _Low .

For example, as shown in (a) of FIG. 6, the magnetic moment direction of the pinned layer is downward as an example. When the magnetic moment direction of the first ferromagnetic layer (downward) and the magnetic moment direction of the pinned layer (downward) are parallel, and the magnetic moment direction of the second ferromagnetic layer (downward) and the magnetic moment direction of the pinned layer (toward When the bottom) is also parallel, the resistance R _Total of the spin logic device is in the low resistance state R _Low .

As another example, as shown in (b) of FIG. 6, the magnetic moment direction of the pinned layer is upward as an example. When the direction of the magnetic moment of the first ferromagnetic layer (up) and the direction of the magnetic moment of the pinned layer (up) are parallel, and the direction of the magnetic moment of the second ferromagnetic layer (up) and the direction of the magnetic moment of the pinned layer (up) are also parallel When, the resistance R _Total of the spin logic device is in the low resistance state R _Low .

Exemplarily, when the magnetic moment directions of the first ferromagnetic layer and the pinned layer are in an anti-parallel state, and the magnetic moment directions of the second ferromagnetic layer and the pinned layer are also in an anti-parallel state, the resistance of the first MTJ is higher, The resistance of the second MTJ is also higher, so the spin logic device is in a high-impedance state, and the resistance of the high-impedance state can be denoted as R _High . That is, in the magnetic moment directions of the first ferromagnetic layer, the fixed layer, and the second ferromagnetic layer, when the two adjacent layers are in an antiparallel state, the resistance of the spin logic device is R _High .

For example, as shown in (a) of FIG. 6, the magnetic moment direction of the pinned layer is downward as an example. When the direction of the magnetic moment of the first ferromagnetic layer (upward) and the direction of the magnetic moment of the pinned layer (down) are antiparallel, and the direction of the magnetic moment of the second ferromagnetic layer (up) and the direction of the magnetic moment of the pinned layer (down) When) is also anti-parallel, the resistance R _Total of the spin logic device is in a high-impedance state R _High .

As another example, as shown in (b) of FIG. 6, the magnetic moment direction of the pinned layer is upward as an example. When the magnetic moment direction of the first ferromagnetic layer (downward) and the magnetic moment direction of the pinned layer (upward) are antiparallel, and the magnetic moment direction of the second ferromagnetic layer (downward) and the magnetic moment direction of the pinned layer (upward) When) is also anti-parallel, the resistance R _Total of the spin logic device is in a high-impedance state R _High .

It is understandable that the structure of the spin logic device in the embodiments of the present application can be composed of two MTJs, and the magnetization direction of the pinned layer in the spin logic device is fixed, so that the magnetization direction of the first ferromagnetic layer and the second ferromagnetic layer is fixed. When the direction of the magnetic moment is different, the entire spin logic device can present different resistance states to implement logic operations.

With reference to FIGS. 3 to 6, as shown in FIG. 7, a control method based on a spin logic device is provided in an embodiment of this application, and the spin logic device in the control method is any one shown in FIGS. 3 to 5 Spin logic device. The method includes steps S701-S702.

S701. Ground the first electrode, and input a first voltage pulse and a second voltage pulse between the first ferromagnetic layer and the first electrode, and input a third voltage pulse between the second ferromagnetic layer and the first electrode. And the fourth voltage pulse.

It can be understood that the above step S701 may be executed by the controller. For example, the controller can ground the first electrode through a switch.

Exemplarily, the first voltage pulse and the third voltage pulse are greater than the critical switching voltage, and the second voltage pulse and the fourth voltage pulse are less than the critical switching voltage, and the critical switching voltage is capable of making the first ferromagnetic layer or the second ferromagnetic layer The voltage at which the magnetic moment of the layer is reversed. This critical switching voltage can be denoted as Vc.

Optionally, the time interval between the first voltage pulse and the second voltage pulse is less than a preset threshold, and the preset threshold is not enough time to change the magnetic moment of the first ferromagnetic layer. That is, after the first voltage pulse is input on the first ferromagnetic layer, when the second voltage pulse is input at a first interval, the direction of the magnetic moment of the first ferromagnetic layer will not change, and the first duration is less than the preset threshold. Similarly, the time interval between the third voltage pulse and the fourth voltage pulse is also less than the preset threshold. In the following embodiments, only the time interval between the first voltage pulse and the second voltage pulse is 0, and the time interval between the third voltage pulse and the fourth voltage pulse is 0 as an example for description. That is, the first voltage pulse and the second voltage pulse are continuous in time, and the third voltage pulse and the fourth voltage pulse are continuous in time.

Exemplarily, after a first voltage pulse greater than the critical switching voltage is input to the first ferromagnetic layer, based on the VCMA effect, the magnetic moment of the first ferromagnetic layer is oriented in-plane. Then, after the input voltage of the first ferromagnetic layer is reduced to a second voltage pulse that is less than the critical switching voltage, the magnetic moment of the first ferromagnetic layer is reversed based on the STT effect. In other words, the above-mentioned first voltage pulse is used to orient the magnetic moment of the first ferromagnetic layer in-plane, and the second voltage pulse is used to reverse the magnetic moment of the first ferromagnetic layer.

The polarity of the above-mentioned second voltage pulse is related to the inversion direction of the first ferromagnetic layer. Take the example that the potential of the first ferromagnetic layer is higher than the potential of the pinned layer as a positive voltage, and the potential of the first ferromagnetic layer is lower than the potential of the pinned layer as a negative voltage. When the second voltage pulse is greater than 0 (the potential of the first ferromagnetic layer is higher than the potential of the pinned layer), the magnetic moment of the first ferromagnetic layer flips to a parallel state, that is, the direction of the magnetic moments of the first ferromagnetic layer and the pinned layer Is a parallel state, when the second voltage pulse is less than 0 (the potential of the first ferromagnetic layer is lower than that of the fixed layer), the magnetic moment of the first ferromagnetic layer reverses to the anti-parallel state, that is, the first ferromagnetic layer and the fixed layer The direction of the magnetic moment of the layer is antiparallel.

Exemplarily, after a third voltage pulse greater than the critical switching voltage is input to the second ferromagnetic layer, based on the VCMA effect, the magnetic moment of the second ferromagnetic layer is oriented in-plane. Then, after the input voltage of the second ferromagnetic layer is reduced to a fourth voltage pulse that is less than the critical switching voltage, the magnetic moment of the second ferromagnetic layer is reversed based on the STT effect. In other words, the third voltage pulse is used to orient the magnetic moment of the second ferromagnetic layer in-plane, and the fourth voltage pulse is used to reverse the magnetic moment of the second ferromagnetic layer.

The polarity of the fourth voltage pulse described above is related to the inversion direction of the second ferromagnetic layer. Take, for example, that the potential of the second ferromagnetic layer is higher than the potential of the pinned layer as a positive voltage, and the potential of the second ferromagnetic layer is lower than the potential of the pinned layer as a negative voltage. When the fourth voltage pulse is greater than 0 (the potential of the second ferromagnetic layer is higher than that of the pinned layer), the magnetic moment of the second ferromagnetic layer flips to a parallel state, that is, the direction of the magnetic moments of the second ferromagnetic layer and the pinned layer Is a parallel state, when the fourth voltage pulse is less than 0 (the potential of the second ferromagnetic layer is lower than the potential of the fixed layer), the magnetic moment of the second ferromagnetic layer reverses to the anti-parallel state, that is, the second ferromagnetic layer and the fixed layer The direction of the magnetic moment of the layer is antiparallel.

It should be noted that the amplitude of the first voltage pulse and the amplitude of the third voltage pulse may be the same or different, and the amplitude of the second voltage pulse and the amplitude of the fourth voltage pulse may be the same, or If they are not the same, the embodiments of the present application do not limit this.

Exemplarily, as shown in FIG. 8, the controller may ground the first electrode, and input V1 (the first voltage pulse and the second voltage pulse that are continuous in time) in the first ferromagnetic layer, and the second voltage pulse in the second ferromagnetic layer Input V2 (the third voltage pulse and the fourth voltage pulse that are continuous in time), and the input time of V1 and V2 can be the same or different.

With reference to Figure 8, as shown in Figure 9(a), the first voltage pulse and the second voltage pulse that are continuous in the input time of the first ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic field of the first ferromagnetic layer The moment is flipped. Since the second voltage pulse is greater than 0, the direction of the magnetic moment of the first ferromagnetic layer is the same as the direction of the magnetic moment of the pinned layer. The third voltage pulse and the fourth voltage pulse that are continuous in the input time of the second ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic moment of the second ferromagnetic layer is reversed. Since the fourth voltage pulse is greater than 0, the direction of the magnetic moment of the second ferromagnetic layer is the same as the direction of the magnetic moment of the pinned layer. Therefore, the resistance R _Total of the spin logic device is in the low resistance state R _Low . As shown in (a) of FIG. 9, when the input second voltage pulse and the fourth voltage pulse are both "1", the resistance R _Total of the spin logic device is in the low resistance state R _Low .

With reference to Figure 8, as shown in Figure 9(b), the first voltage pulse and the second voltage pulse that are continuous in the input time of the first ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic field of the first ferromagnetic layer The moment is flipped. Since the second voltage pulse is greater than 0, the direction of the magnetic moment of the first ferromagnetic layer is the same as the direction of the magnetic moment of the pinned layer. The third voltage pulse and the fourth voltage pulse that are continuous in the input time of the second ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic moment of the second ferromagnetic layer is reversed. Since the fourth voltage pulse is less than 0, the direction of the magnetic moment of the second ferromagnetic layer is opposite to the direction of the magnetic moment of the pinned layer. Therefore, the resistance R _Total of the spin logic device is in the intermediate resistance state R _Mid . As shown in FIG. 9(b), when the input second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance R _Total of the spin logic device is in the intermediate resistance state R _Mid .

In conjunction with Figure 8, as shown in Figure 9(c), the first voltage pulse and the second voltage pulse that are continuous in the input time of the first ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic field of the first ferromagnetic layer The moment is flipped. Since the second voltage pulse is less than 0, the direction of the magnetic moment of the first ferromagnetic layer is opposite to the direction of the magnetic moment of the pinned layer. The third voltage pulse and the fourth voltage pulse that are continuous in the input time of the second ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic moment of the second ferromagnetic layer is reversed. Since the fourth voltage pulse is greater than 0, the direction of the magnetic moment of the second ferromagnetic layer is the same as the direction of the magnetic moment of the pinned layer. Therefore, the resistance R _Total of the spin logic device is in the intermediate resistance state R _Mid . As shown in (c) of FIG. 9, when the input second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance R _Total of the spin logic device is in the intermediate resistance state R _Mid .

With reference to Figure 8, as shown in Figure 9(d), the first voltage pulse and the second voltage pulse that are continuous in the input time of the first ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic field of the first ferromagnetic layer The moment is flipped. Since the second voltage pulse is less than 0, the direction of the magnetic moment of the first ferromagnetic layer is opposite to the direction of the magnetic moment of the pinned layer. The third voltage pulse and the fourth voltage pulse that are continuous in the input time of the second ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic moment of the second ferromagnetic layer is reversed. Since the fourth voltage pulse is less than 0, the direction of the magnetic moment of the second ferromagnetic layer is opposite to the direction of the magnetic moment of the pinned layer. Therefore, the resistance R _Total of the spin logic device is in the high resistance state R _High . As shown in (d) of FIG. 9, when the input second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance R _Total of the spin logic device is in the high resistance state R _High .

It is understandable that when different voltage pulses are input to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, the magnetic moment directions of the first ferromagnetic layer and the second ferromagnetic layer are different, and the spin logic device Can exhibit different resistance states.

Optionally, the pulse width of the first voltage pulse and the third voltage pulse may be less than (but not limited to) 2ns, and the pulse width of the second voltage pulse and the fourth voltage pulse may be less than (but not limited to) 10ns to reduce Energy consumption of spin logic devices.

S702. Read the resistance value of the spin logic device and convert the resistance value of the spin logic device into a corresponding logic signal.

It can be understood that the above step S702 can be implemented by a reading circuit. The reading circuit may include a controller and a comparator.

Exemplarily, after the above step S701, the spin logic device will present different resistance states. The resistance value of the spin logic device can be read and the resistance value of the spin logic device can be converted into a corresponding logic signal to achieve different resistance states. The logical operation.

Exemplarily, as shown in FIG. 10, the above step S702 may include steps S7021-S7022.

S7021. Turn off the grounding setting of the first electrode, and input a read voltage to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, and read the resistance value of the spin logic device.

It can be understood that the above step S7021 can be implemented by the controller in the reading circuit.

Exemplarily, as shown in FIG. 11, the controller in the read circuit can turn off the grounding setting of the first electrode in the spin logic device through a switch, and it is located between the first ferromagnetic layer and the second ferromagnetic layer. Input the read voltage and read the resistance value of the spin logic device. The read circuit shown in FIG. 11 can implement logical NOR (NOR) operation, logical NAND (NAND) operation, and logical NOT (NOT) operation.

Optionally, an inverter may be added after the comparator in the reading circuit shown in FIG. 11 to implement other logic operations. For example, logical OR (OR) operation, logical AND (AND) operation, and logical is gate (BUF) operation.

It is understandable that the voltage value of the aforementioned input voltage is not sufficient to change the direction of the magnetic moment of the spin logic device, that is, the input of the aforementioned input voltage will not change the resistance value of the spin logic device, and the spin logic read in step S7021 The resistance value of the device is still the resistance value present after step S701.

Exemplarily, the controller in the above-mentioned reading circuit may read the resistance value of the spin logic device based on Ohm's law.

S7022. Compare the resistance value of the spin logic device with the resistance value of the preset reference resistance to output a corresponding logic signal.

It can be understood that the above step S7021 can be implemented by a comparator in the reading circuit.

Exemplarily, the resistance value of the preset reference resistor may be greater than the resistance value R _{Mid of the} _{spin logic device in the intermediate resistance state and less than the resistance value R High} of the spin logic device in the high resistance state, and the resistance of the preset reference resistor The value is denoted as R ¹ _Ref ; or, if the resistance of the preset reference resistance is greater than the resistance value R _{Low of the} _{spin logic device in the low resistance state and less than the resistance value R Mid} of the spin logic device in the intermediate resistance state, the preset reference The resistance value of the resistor is denoted as R ² _Ref .

_{Exemplarily, when the resistance R Total} of the spin logic device of the input comparator is greater than the resistance value of the preset reference resistance, the output high level is recorded as "1"; when the resistance R of the spin logic device of the input comparator is _{When Total is} less than the resistance value of the preset reference resistor, the output low level is recorded as "0". That is, the input and output logic signal processors depend on the value of the preset reference voltage, and different logic operations can be implemented when the preset reference voltage is different.

For example, in conjunction with FIG. 9 and FIG. 11, as shown in FIG. 12, the resistance value of the preset reference resistor is R ¹ _Ref as an example. As shown in Figure 9, when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Low} . Since R _{Low is} less than R ¹ _Ref , the output is low. Level, recorded as "0". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} less than R ¹ _Ref , the output low level is marked as "0". When the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} less than R ¹ _Ref , the output low level is marked as "0". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R High} . Since R _{High is} greater than R ¹ _Ref , the output high level is marked as "1". That is, as shown in FIG. 12, ^{when the resistance value of the preset reference resistor is R 1} _Ref , a logic NOR (NOR) operation can be implemented according to the difference between the input second voltage pulse and the fourth voltage pulse.

For example, in conjunction with FIG. 9 and FIG. 11, as shown in FIG. 13, the resistance value of the preset reference resistor is R ² _Ref as an example. As shown in Figure 9, when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Low} . Since R _{Low is} less than R ² _Ref , the output is low. Level, recorded as "0". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} greater than R ² _Ref , the output is high, which is marked as "1". When the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} greater than R ² _Ref , the output is high, which is marked as "1". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R High} . Since R _{High is} greater than R ² _Ref , the output high level is marked as "1". That is, as shown in FIG. 13, ^{when the resistance value of the preset reference resistor is R 2} _Ref , a logic NAND gate (NAND) operation can be implemented according to the difference between the input second voltage pulse and the fourth voltage pulse.

Exemplarily, an implementation method when implementing the NOT operation is to initialize any one of the second voltage pulse and the fourth voltage pulse by ^{setting the resistance value of the preset reference resistor to R 1} _Ref To input "0", only the uninitialized end of the second voltage pulse and the fourth voltage pulse is used as an input to realize a logical NOT (NOT) operation.

For example, take the initialization of the second voltage pulse to "0" as an example. With reference to FIG. 9 and FIG. 11, as shown in (a) of FIG. 14, the resistance value of the preset reference resistor is R ¹ _Ref as an example. As shown in Figure 9, when the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} less than R ¹ _Ref , the output is low. Level, recorded as "0". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R High} . Since R _{High is} greater than R ¹ _Ref , the output high level is recorded as "1"". That is, as shown in Figure 14 (a), the resistance value of the preset reference resistor is R ¹ _Ref , and the second voltage pulse is initialized to "0", according to the input fourth voltage pulse, the logic NOT gate can be realized (NOT) operation.

For another example, take the initialization of the fourth voltage pulse to "0" as an example. With reference to FIG. 9 and FIG. 11, as shown in (b) of FIG. 14, the resistance value of the preset reference resistor is R ¹ _Ref as an example. As shown in Figure 9, when the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R High} . Since R _{High is} greater than R ¹ _Ref , the output is high. Level, recorded as "1". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} less than R ¹ _Ref , the output low level is recorded as "0"". That is, as shown in Figure 14 (b), the resistance value of the preset reference resistor is R ¹ _Ref , and when the fourth voltage pulse is initialized to "0", the logic NOT gate can be realized according to the difference of the input second voltage pulse (NOT) operation.

Exemplarily, another way to realize the NOT operation is to initialize any of the second voltage pulse and the fourth voltage pulse by ^{setting the resistance value of the preset reference resistor to R 2} _Ref One is the input "1", and only the uninitialized end of the second voltage pulse and the fourth voltage pulse is used as an input to realize a logical NOT (NOT) operation.

For example, take the initialization of the second voltage pulse to "1" as an example. With reference to FIG. 9 and FIG. 11, as shown in (a) of FIG. 15, the resistance value of the preset reference resistor is R ² _Ref as an example. As shown in Figure 9, when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Low} . Since R _{Low is} less than R ² _Ref , the output is low. Level, recorded as "0". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} greater than R ² _Ref , the output is high, which is recorded as "1"". That is, as shown in Figure 15 (a), the resistance value of the preset reference resistor is R ² _Ref , and when the second voltage pulse is initialized to "1", the logic NOT gate can be realized according to the difference of the input fourth voltage pulse (NOT) operation.

For another example, take the initialization of the fourth voltage pulse to "1" as an example. With reference to FIG. 9 and FIG. 11, as shown in (b) of FIG. 15, the resistance value of the preset reference resistor is R ² _Ref as an example. As shown in Figure 9, when the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} greater than R ² _Ref , the output is high. Level, recorded as "1". When the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Low} , and since R _{Low is} less than R ² _Ref , the output low level is recorded as "0"". That is, as shown in Figure 15 (b), the resistance value of the preset reference resistor is R ² _Ref , and when the fourth voltage pulse is initialized to "1", the logic NOT gate can be realized according to the difference of the input second voltage pulse (NOT) operation.

Optionally, as shown in Figure 16, when implementing logical OR (OR) operations, logical AND (AND) operations, and logic is gate (BUF) operations, you can add an inverted phase after the comparator shown in Figure 11 The high-level and low-level output are interchanged.

Exemplarily, as shown in FIG. 16, when implementing a logical OR (OR) operation, the resistance value of the preset reference resistor is set to R ¹ _Ref , according to the difference between the input second voltage pulse and the fourth voltage pulse, The OR logic can be realized.

For example, in conjunction with FIG. 9 and FIG. 16, as shown in FIG. 17, the resistance value of the preset reference resistor is R ¹ _Ref as an example. As shown in Figure 9, when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Low} . Since R _{Low is} less than R ¹ _Ref , the comparator's The output is low level, and after the inverter is inverted, the output is high level, which is recorded as "1". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} less than R ¹ _Ref , the output of the comparator is low level , And then inverted by the inverter, the output is high, which is recorded as "1". When the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} less than R ¹ _Ref , the output of the comparator is low level , And then inverted by the inverter, the output is high, which is recorded as "1". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R High} . Since R _{High is} greater than R ¹ _Ref , the output of the comparator is high , And then inverted by the inverter, the output is low level, which is recorded as "0". That is, as shown in FIG. 16 and FIG. 17, ^{when the resistance value of the preset reference resistor is R 1} _Ref , according to the difference between the input second voltage pulse and the fourth voltage pulse, a logical OR (OR) operation can be implemented.

Exemplarily, as shown in FIG. 16, when the AND operation is implemented, the resistance value of the preset reference resistor is set to R ² _Ref , according to the difference between the input second voltage pulse and the fourth voltage pulse, Then AND logic can be realized.

For example, in conjunction with FIG. 9 and FIG. 16, as shown in FIG. 18, the resistance value of the preset reference resistor is R ² _Ref as an example. As shown in Figure 9, when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Low} , and since R _{Low is} less than R ² _Ref , the comparator's The output is low level, and after the inverter is inverted, the output is high level, which is recorded as "1". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} greater than R ² _Ref , the output of the comparator is high , And then inverted by the inverter, the output is low level, which is recorded as "0". When the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} greater than R ² _Ref , the output of the comparator is high , And then inverted by the inverter, the output is low level, which is recorded as "0". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R High} . Since R _{High is} greater than R ² _Ref , the output of the comparator is high , And then inverted by the inverter, the output is low level, which is recorded as "0". That is, as shown in FIGS. 16 and 18, ^{when the resistance value of the preset reference resistor is R 2} _Ref , according to the difference between the input second voltage pulse and the fourth voltage pulse, a logical AND gate (AND) operation can be implemented.

Exemplarily, in conjunction with FIG. 16, when implementing a logic gate (BUF) operation, one implementation method is to initialize the second voltage pulse and the fourth voltage pulse by ^{setting the resistance value of the preset reference resistor to R 1} _Ref Any one of the voltage pulses is the input "0", and only the uninitialized end of the second voltage pulse and the fourth voltage pulse is used as the input, and the logic is gate (BUF) operation can be realized.

For example, take the initialization of the second voltage pulse to "0" as an example. With reference to FIG. 9 and FIG. 16, as shown in (a) of FIG. 19, the resistance value of the preset reference resistor is R ¹ _Ref as an example. As shown in Figure 9, when the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} less than R ¹ _Ref , the comparator's The output is low level, and after the inverter is inverted, the output is high level, which is recorded as "1". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R High} . Since R _{High is} greater than R ¹ _Ref , the output of the comparator is high. After being inverted by the inverter, the output is low level, which is recorded as "0". That is, in combination with Figure 16 and Figure 19 (a), the resistance value of the preset reference resistor is R ¹ _Ref , and the second voltage pulse is initialized to "0", according to the difference of the input fourth voltage pulse, it can be realized Logic is the gate (BUF) operation.

For another example, take the initialization of the fourth voltage pulse to "0" as an example. With reference to FIG. 9 and FIG. 16, as shown in (b) of FIG. 19, the resistance value of the preset reference resistor is R ¹ _Ref as an example. As shown in Figure 9, when the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R High} . Since R _{High is} greater than R ¹ _Ref , the comparator's The output is high level, and after the inverter is inverted, the output is low level, which is recorded as "0". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} less than R ¹ _Ref , the output of the comparator is low, After the inverter is inverted, the output is high, which is recorded as "1". That is, as shown in (b) of Figure 16 and Figure 19, the resistance value of the preset reference resistor is R ¹ _Ref , and the fourth voltage pulse is initialized to "0", according to the difference of the input second voltage pulse, it can be realized Logic is the gate (BUF) operation.

Exemplarily, in conjunction with FIG. 16, another implementation method when implementing a logic gate (BUF) operation is to initialize the second voltage pulse and the first voltage pulse by ^{setting the resistance value of the preset reference resistor to R 2} _Ref Any one of the four voltage pulses is the input "1", and only the uninitialized end of the second voltage pulse and the fourth voltage pulse is used as the input, and the logic is gate (BUF) operation can be realized.

For example, take the initialization of the second voltage pulse to "1" as an example. With reference to FIG. 9 and FIG. 16, as shown in (a) of FIG. 20, the resistance value of the preset reference resistor is R ² _Ref as an example. As shown in Figure 9, when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Low} , and since R _{Low is} less than R ² _Ref , the comparator's The output is low level, and after the inverter is inverted, the output is high level, which is recorded as "1". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} greater than R ² _Ref , the output of the comparator is high. After being inverted by the inverter, the output is low level, which is recorded as "0". That is, in conjunction with Figure 16 and Figure 20 (a), the resistance value of the preset reference resistor is R ² _Ref , and the second voltage pulse is initialized to "1", according to the difference of the input fourth voltage pulse, it can be realized Logic is the gate (BUF) operation.

For another example, take the initialization of the fourth voltage pulse to "1" as an example. With reference to FIG. 9 and FIG. 16, as shown in (b) of FIG. 20, the resistance value of the preset reference resistor is R ² _Ref as an example. As shown in Figure 9, when the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Mid} . Since R _{Mid is} greater than R ² _Ref , the comparator's The output is high level, and after the inverter is inverted, the output is low level, which is recorded as "0". When the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance R _Total of the _{spin logic device is R Low} . Since R _{Low is} less than R ² _Ref , the output of the comparator is low, After the inverter is inverted, the output is high, which is recorded as "1". That is, as shown in (b) of FIG. 16 and FIG. 20, the resistance value of the preset reference resistor is R ² _Ref , and the fourth voltage pulse is initialized to "1", according to the difference of the input second voltage pulse, it can be realized Logic is the gate (BUF) operation.

It should be noted that, in the embodiment of the present application, different resistance values can be selected as the resistance value of the preset reference resistance, and different logics can be realized in combination with the above scheme according to the difference of the second voltage pulse and/or the fourth voltage pulse input. Operation.

It is understandable that the spin logic device-based control method provided by the embodiments of the present application implements the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device by inputting voltage pulses, and based on the VCMA effect and the STT effect. The magnetic moments of the first ferromagnetic layer and the second ferromagnetic layer are reversed, so that the spin logic device can exhibit different resistance states, so that a variety of logic operations can be implemented when the output is compared with the comparator. When the method is based on the VCMA effect and the STT effect to realize the magnetic moment reversal of the spin logic device, the current is small, the power consumption can be reduced, the calculation speed is accelerated, and the operating efficiency is improved.

As shown in FIG. 21, a spin logic circuit 2100 provided in this embodiment of the application, the spin logic circuit 2100 includes a first controller 2101, a read circuit 2102, and a spin logic device 2103. The spin logic device 2103 can be any one of the spin logic devices shown in FIGS. 3 to 5.

The above-mentioned first controller 2101 is used to ground the first electrode in the spin logic device 2103, and respectively input the first voltage pulse and the second voltage pulse between the first ferromagnetic layer and the first electrode in the spin logic device 2103. Voltage pulse, a third voltage pulse and a fourth voltage pulse are input between the second ferromagnetic layer and the first electrode. The first voltage pulse and the third voltage pulse are greater than the critical switching voltage, the second voltage pulse and the fourth voltage pulse are less than the critical switching voltage, and the critical switching voltage is capable of making the magnetic moment of the first ferromagnetic layer or the second ferromagnetic layer The voltage at which the flip occurs.

The reading circuit 2102 is used to read the resistance value of the spin logic device 2103 and convert the resistance value of the spin logic device 2103 into a corresponding logic signal.

Exemplarily, the above-mentioned reading circuit 2102 may include a second controller 2102a and a comparator 2102b, wherein the second controller 2102a is used to turn off the grounding setting of the first electrode, and is used for the first iron of the spin logic device 2103. The magnetic layer and the second ferromagnetic layer are inputted with a read voltage, and the resistance value of the spin logic device 2103 is read. The comparator 2102b is used to compare the resistance value of the spin logic device 2103 with the resistance value of a preset reference resistance to output a corresponding logic signal. The reading circuit 2102 can be used to implement, for example, a logical NOR (NOR) operation, a logical NAND (NAND) operation, and a logical NOT (NOT) operation.

Optionally, the above-mentioned reading circuit 2102 may further include an inverter 2102c, which is used to invert the logic signal output by the comparator 2102b to implement, for example, a logical OR (OR) operation and a logical AND gate. (AND) operation, logic is gate (BUF) operation.

Among them, all relevant content of the steps involved in the foregoing method embodiments can be cited in the functional description of the circuit module corresponding to the spin logic circuit 2100, which will not be repeated here.

Exemplarily, an embodiment of the present application further provides a processing device, the processing device includes a memory, and at least one spin logic circuit 2100 as shown in FIG. 21, the at least one spin logic circuit 2100 and the memory respectively coupling.

The steps of the method or algorithm described in combination with the disclosure of the present application may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions. Software instructions can be composed of corresponding software modules, which can be stored in random access memory (Random Access Memory, RAM), flash memory, erasable programmable read-only memory (Erasable Programmable ROM, EPROM), and electrically erasable Programming read-only memory (Electrically EPROM, EEPROM), registers, hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and can write information to the storage medium. Of course, the storage medium may also be an integral part of the processor. The processor and the storage medium may be located in the ASIC. In addition, the ASIC may be located in the core network interface device. Of course, the processor and the storage medium may also exist as discrete components in the core network interface device.

Those skilled in the art should be aware that, in one or more of the foregoing examples, the functions described in this application can be implemented by hardware, software, firmware, or any combination thereof. When implemented by software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on the computer-readable medium. The computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another. The storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.

The specific implementations described above further describe the purpose, technical solutions, and beneficial effects of the application in detail. It should be understood that the foregoing are only specific implementations of the application and are not intended to limit the scope of the application. The scope of protection, any modification, equivalent replacement, improvement, etc. made on the basis of the technical solution of this application shall be included in the scope of protection of this application.

Claims

A spin logic device, characterized in that the spin logic device comprises a first ferromagnetic layer, a first barrier layer, a pinned layer, a second barrier layer, and a second ferromagnetic layer which are sequentially stacked and arranged, among them:

The first ferromagnetic layer and the second ferromagnetic layer include a magnetic material; the first barrier layer and the second barrier layer include a metal oxide material; the magnetization direction of the pinned layer is a fixed direction .
The spin logic device according to claim 1, wherein the pinned layer comprises a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked in sequence, among them:

The first sublayer and the fifth sublayer include magnetic materials; the second sublayer and the fourth sublayer include metal non-magnetic materials or alloy non-magnetic materials; the third sublayer includes magnetic materials. Layer film [A x /B y ] n , where A is a ferromagnetic metal element, B is a heavy metal element, x is the thickness of A, y is the thickness of B, and n is the number of cycles of [A x /B y ]; The third sublayer and the first sublayer form an antiferromagnetic coupling, and the third sublayer and the fifth sublayer form an antiferromagnetic coupling.
The spin logic device according to claim 2, wherein the A is one of cobalt, iron, and nickel, and the B is one of platinum, palladium, ruthenium, and tantalum.
The spin logic device according to claim 2 or 3, wherein the spin logic device further comprises a first electrode, between the first electrode and the third sublayer in the pinned layer Conductive contact, and the first electrode is isolated from the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer.
The spin logic device according to any one of claims 1 to 4, wherein the magnetic material comprises cobalt, iron, cobalt iron, cobalt iron boron, iron boron, cobalt platinum, nickel iron, cobalt palladium, One or more combinations of cobalt nickel and cobalt ruthenium.
The spin logic device according to any one of claims 1 to 5, wherein the metal oxide material comprises one of magnesium oxide, aluminum oxide, zinc oxide, MgAlOx, and hafnium oxide.
The spin logic device according to any one of claims 1 to 6, wherein the shape of the spin logic device is cylindrical or elliptical.
A spin logic circuit, wherein the spin logic circuit includes: a first controller, a spin logic device, and a read circuit; the spin logic device includes: a first ferromagnetic layer, a first A barrier layer, a pinned layer, a second barrier layer, a second ferromagnetic layer, and a first electrode; wherein the first ferromagnetic layer and the second ferromagnetic layer include a magnetic material; the first potential The barrier layer and the second barrier layer include a metal oxide material; the magnetization direction of the pinned layer is a fixed direction; the first electrode is in conductive contact with the pinned layer, and the first electrode is in contact with the pinned layer. The first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer are separated by an insulating layer;

The first controller is used for grounding the first electrode, and inputting a first voltage pulse and a second voltage pulse between the first ferromagnetic layer and the first electrode. A third voltage pulse and a fourth voltage pulse are input between the ferromagnetic layer and the first electrode; the first voltage pulse and the third voltage pulse are greater than the critical switching voltage, and the second voltage pulse and the first voltage pulse Four voltage pulses are less than the critical switching voltage, and the critical switching voltage is the voltage at which the magnetic moment of the first ferromagnetic layer or the second ferromagnetic layer is inverted;

The reading circuit is used to read the resistance value of the spin logic device and convert the resistance value of the spin logic device into a corresponding logic signal.
The spin logic circuit according to claim 8, wherein the read circuit comprises: a second controller and a comparator,

The second controller is used to turn off the grounding setting of the first electrode, and input a read voltage to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, Reading the resistance value of the spin logic device;

The comparator is used to compare the resistance value of the spin logic device with the resistance value of a preset reference resistance to output a corresponding logic signal.
The spin logic circuit according to claim 9, wherein the read circuit further comprises: an inverter,

The inverter is used to invert the logic signal output by the comparator.
The spin logic circuit according to claim 9 or 10, wherein the resistance value of the preset reference resistor is greater than the resistance value R Mid of the spin logic device in an intermediate resistance state and smaller than the resistance value R Mid of the spin logic device. The resistance value R High of the device in the high resistance state, or the resistance value of the preset reference resistance is greater than the resistance value R Low of the spin logic device in the low resistance state and smaller than the resistance value R Low of the spin logic device in the middle resistance state The resistance R Mid of the spin logic device; when the spin logic device is the resistance R Mid of the intermediate resistance state, the magnetic moment direction of the first ferromagnetic layer and the pinned layer, and the second ferromagnetic layer In the direction of the magnetic moment with the pinned layer, only one set is in a parallel state; when the spin logic device is in the high-resistance state with a resistance value R High , the first ferromagnetic layer, the pinned layer and the The magnetic moment direction of the second ferromagnetic layer is in an antiparallel state between two adjacent layers; when the spin logic device has a resistance value R Low in the low resistance state, the first ferromagnetic layer and the pinned layer The magnetic moment direction of the second ferromagnetic layer is parallel to the two adjacent layers.
The spin logic circuit according to any one of claims 8-11, wherein the spin logic circuit is configured to perform logical AND gates, logical OR gates, logical yes gates, logical NAND gates, logical OR NOT gate or logic NOT gate.
A control method based on a spin logic device, characterized in that the spin logic device comprises: a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, and a second ferromagnetic layer, And a first electrode; wherein the first ferromagnetic layer and the second ferromagnetic layer include a magnetic material; the first barrier layer and the second barrier layer include a metal oxide material; the fixed The magnetization direction of the layer is a fixed direction; the first electrode is in conductive contact with the fixed layer, and the first electrode is in contact with the first ferromagnetic layer, the first barrier layer, and the second The barrier layer and the second ferromagnetic layer are separated by an insulating layer; the method includes:

The first electrode is grounded, and a first voltage pulse and a second voltage pulse are input between the first ferromagnetic layer and the first electrode, respectively, in the second ferromagnetic layer and the first A third voltage pulse and a fourth voltage pulse are input between the electrodes; the first voltage pulse and the third voltage pulse are greater than the critical switching voltage, and the second voltage pulse and the fourth voltage pulse are less than the critical switching voltage Voltage, the critical switching voltage is a voltage at which the magnetic moment of the first ferromagnetic layer or the second ferromagnetic layer is inverted;

The resistance value of the spin logic device is read and the resistance value of the spin logic device is converted into a corresponding logic signal.
The method according to claim 13, wherein the reading the resistance value of the spin logic device and converting the resistance value of the spin logic device into a corresponding logic signal comprises:

Turn off the ground setting of the first electrode, and input a read voltage to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device to read the spin logic device resistance;

The resistance value of the spin logic device is compared with the resistance value of the preset reference resistance to output a corresponding logic signal.
The method according to claim 14, wherein the method further comprises:

The logic signal is inverted.
The method according to claim 14 or 15, wherein the resistance value of the preset reference resistance is greater than the resistance value R Mid of the spin logic device in an intermediate resistance state and less than the resistance value R Mid of the spin logic device. The resistance value R High of the resistance state, or the resistance value of the preset reference resistance is greater than the resistance value R Low of the spin logic device in the low resistance state and less than the resistance value of the spin logic device in the middle resistance state R Mid ; wherein, when the spin logic device has an intermediate resistance state resistance R Mid , the magnetic moment direction of the first ferromagnetic layer and the pinned layer, and the second ferromagnetic layer and the In the direction of the magnetic moment of the pinned layer, only one set is in the parallel state; when the spin logic device is in the high-resistance state, the resistance value R High , the first ferromagnetic layer, the pinned layer and the second iron The direction of the magnetic moment of the magnetic layer is in an anti-parallel state between two adjacent layers; when the spin logic device has a resistance value R Low in the low resistance state, the first ferromagnetic layer, the pinned layer and the The direction of the magnetic moment of the second ferromagnetic layer is parallel between two adjacent layers.
The method according to any one of claims 13-16, wherein the spin logic device is configured to perform logic AND gates, logic OR gates, logic yes gates, logic NAND gates, logic NOR gates, or Logic NOT gate.
A processing device, wherein the processing device comprises a memory, and at least one spin logic circuit according to any one of claims 8-12, and the at least one spin logic circuit is respectively connected to the memory coupling.