CN110459254B - Spintronic device and memory logic computing device - Google Patents
Spintronic device and memory logic computing device Download PDFInfo
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- CN110459254B CN110459254B CN201910705776.6A CN201910705776A CN110459254B CN 110459254 B CN110459254 B CN 110459254B CN 201910705776 A CN201910705776 A CN 201910705776A CN 110459254 B CN110459254 B CN 110459254B
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
Abstract
The invention provides a spintronic device and a memory logic computing device. The spintronic device comprises: a metal layer; a free magnetic layer having a magnetization direction that changes in response to an external magnetic field; a fixed magnetic layer having a fixed magnetization direction; an oxide layer including a first oxide layer and a second oxide layer; the first oxide layer is positioned between the metal layer and the free magnetic layer; the second oxide layer is located between the free magnetic layer and the fixed magnetic layer. The invention can realize storage and logic processing of a single device at the same time, is convenient to process and reduces transmission power consumption and manufacturing cost.
Description
Technical Field
The invention relates to the technical field of nano electronic devices, in particular to a spintronic device and a memory logic computing device.
Background
With the rapid development of applications such as internet of things, big data, artificial intelligence and the like, the data volume is increased explosively, but the data processing unit is separated from the data storage unit by the traditional von neumann architecture, so that data is frequently migrated between the storage unit and the processing unit, and the transmission power consumption generated by the data processing unit even far exceeds the power consumption of actual data processing, thereby causing the problem of power consumption wall. Therefore, it is one of the important research directions to realize data processing in the memory.
In recent years, a new type of nonvolatile spin transfer torque magnetic random access memory (STT-MRAM) based on spintronics provides practical possibilities for implementing an in-memory processing technology, a core device of the spintronics is a magnetic tunnel junction with a sandwich structure, which is mainly composed of an upper ferromagnetic metal layer (e.g., CoFeB) and a lower ferromagnetic metal layer (e.g., CoFeB) sandwiching a metal oxide layer (e.g., MgO), wherein one of the magnetic metal layers is a fixed layer, and the other magnetic metal layer is a free layer, and the magnetic tunnel junction can exhibit two different resistance states (a low resistance state and a high resistance state) according to different relative magnetization directions (parallel state or antiparallel state) of the upper ferromagnetic metal layer and the lower ferromagnetic metal layer, and is used for storing data information. The spin transfer torque effect is an important writing mechanism of the STT-MRAM, and when a current of a certain magnitude is passed through a magnetic tunnel junction structure (fixed layer/isolation layer/free layer), a spin polarized current generated after passing through the fixed layer generates a torque on the magnetic moment of the free layer, thereby realizing the magnetization direction reversal (i.e., writing process) of the free layer. The spin memory has the advantages of non-volatility (namely, power-off data is not lost), high density, high speed, high durability and the like, and has better compatibility with the current CMOS process.
The availability of a large spin transfer torque is an important factor in utilizing the spin transfer torque to act on the magnetic free layer. Due to the limitation of the spin current injection efficiency of the magnetic tunnel junction, a large current density is often required to generate a spin transfer torque of sufficient magnitude, and thus the operating power consumption of the STT-MRAM is increased, which causes inconvenience for practical application thereof. At present, no electronic device for data processing in the memory exists, so that the electronic device generates huge transmission power consumption.
Disclosure of Invention
The embodiments of the present invention mainly aim to provide a spintronic device and a memory logic computing device, which can enable a single device to simultaneously implement storage and logic processing, and are convenient to process, and reduce transmission power consumption and manufacturing cost.
In order to achieve the above object, an embodiment of the present invention provides a spintronic device including:
a metal layer;
a free magnetic layer having a magnetization direction that changes in response to an external magnetic field;
a fixed magnetic layer having a fixed magnetization direction;
an oxide layer including a first oxide layer and a second oxide layer;
the first oxide layer is positioned between the metal layer and the free magnetic layer;
the second oxide layer is located between the free magnetic layer and the fixed magnetic layer.
In one embodiment, the metal layer has a thickness greater than 10 nanometers and less than 200 nanometers.
In one embodiment, the free magnetic layer has a thickness greater than 0 nanometers and less than 3 nanometers;
the thickness of the fixed magnetic layer is greater than 0 nm and less than 3 nm.
In one embodiment, the thickness of the first oxide layer is greater than 0 nm and less than 3 nm;
the thickness of the second oxide layer is greater than 0 nm and less than 2 nm.
In one embodiment, the metal layer is at least one of tantalum, aluminum, and copper.
In one embodiment, the free magnetic layer comprises one or any combination of cofe, cofeb, and nife;
the fixed magnetic layer comprises one or any combination of cobalt iron, cobalt iron boron and nickel iron.
In one embodiment, the oxide layer comprises magnesium oxide or aluminum oxide.
The spin electronic device comprises a metal layer, a free magnetic layer, a fixed magnetic layer and an oxide layer; the first oxide layer is located between the metal layer and the free magnetic layer, and the second oxide layer is located between the free magnetic layer and the fixed magnetic layer, so that a single device can simultaneously realize storage and logic processing, the processing is convenient, and the transmission power consumption and the manufacturing cost are reduced.
An embodiment of the present invention further provides an in-memory logic computing device, including:
the first switch tube, the second switch tube and the spintronic device are arranged in the cavity;
the metal layer of the spin electronic device is connected with the first end of the first switching tube;
the second end of the first switch tube is connected with the logic line, and the grid electrode of the first switch tube is connected with the logic control line;
the free magnetic layer of the spin electronic device is connected with the first end of the second switch tube;
the second end of the second switch tube is connected with a source line, and the grid electrode of the second switch tube is connected with a word line;
the fixed magnetic layer of the spintronic device is connected to the bit line.
In one embodiment, the first end of the first switch tube is a source electrode, and the second end of the first switch tube is a drain electrode; or the like, or, alternatively,
the second end of the first switch tube is a source electrode, and the first end of the first switch tube is a drain electrode.
In one embodiment, the first end of the second switch tube is a source, and the second end of the second switch tube is a drain; or the like, or, alternatively,
the second end of the second switch tube is a source electrode, and the first end of the second switch tube is a drain electrode.
The memory logic computing device comprises a first switching tube, a second switching tube and a spintronic device; the metal layer of the spin electronic device is connected with the logic line through the first switch tube, the free magnetic layer is connected with the source line through the second switch tube, and the fixed magnetic layer is connected with the bit line, so that the single device can simultaneously realize storage and logic processing, the processing is convenient, and the transmission power consumption and the manufacturing cost are reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a spintronic device in an embodiment of the invention;
FIG. 2 is a schematic diagram of the operation of a spintronic device in an embodiment of the invention;
FIG. 3 is a diagram of the IMP logic timing for a spintronic device in an embodiment of the present invention;
FIG. 4 is a NAND logic timing diagram of a spintronic device in an embodiment of the invention;
FIG. 5 is a schematic diagram of a spintronic device in a first embodiment of the invention;
FIG. 6 is a schematic diagram of a spintronic device in a second embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In view of the fact that the electronic device does not have an electronic device for data processing in the memory at present, and therefore the electronic device generates huge transmission power consumption, the embodiment of the invention provides a spintronic device and a memory logic computing device, which can enable a single device to simultaneously realize storage and logic processing, are convenient to process, and reduce transmission power consumption and manufacturing cost. The present invention will be described in detail below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a spintronic device in an embodiment of the present invention. As shown in fig. 1, a spintronic device, comprising:
a metal layer; the metal layer is at least one of tantalum, aluminum and copper, and the thickness of the metal layer is more than 10 nanometers and less than 200 nanometers.
A free magnetic layer having a magnetization direction that changes in response to an external magnetic field; the free magnetic layer comprises one or any combination of cobalt iron, cobalt iron boron and nickel iron, and the thickness of the free magnetic layer is more than 0 nanometer and less than 3 nanometers.
A fixed magnetic layer having a fixed magnetization direction; the fixed magnetic layer comprises one or any combination of cobalt iron, cobalt iron boron and nickel iron, and the thickness of the fixed magnetic layer is more than 0 nanometer and less than 3 nanometers.
The oxide layer comprises a first oxide layer and a second oxide layer and is used for generating a tunneling effect to transmit a spin signal; the first oxide layer and the second oxide layer can both comprise magnesium oxide or aluminum oxide, the thickness of the first oxide layer is larger than 0 nanometer and smaller than 3 nanometers, and the thickness of the second oxide layer is larger than 0 nanometer and smaller than 2 nanometers.
The first oxide layer is positioned between the metal layer and the free magnetic layer;
the second oxide layer is located between the free magnetic layer and the fixed magnetic layer.
The spintronic device is square, rectangular (the length-width ratio can be any value), circular or elliptical (the length-width ratio can be any value), namely the spintronic device is one of square, rectangular, circular and elliptical, and the size is nano-scale.
The preparation process of the spintronic device comprises magnetron sputtering, Molecular Beam Epitaxy (MBE), Ion Beam Deposition (IBD), physical vapor deposition (CVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD), and the photoetching mode can comprise ultraviolet photoetching (UVL) and ion beam photoetching (EBL); the etching manner may include non-metal oxide or metal hard mask, Reactive Ion Etching (RIE), Ion Beam Etching (IBE), Chemical Mechanical Planarization (CMP). It should be noted that the deposition, photolithography and etching processes are selected from, but not limited to, the above-mentioned types, and may also be combined with a plurality of processes, specifically related to the composition of the magnetic tunnel junction and the resistive material.
Wherein, the fixed magnetic layer and the free magnetic layer adopt an annealing magnetic field vertical to the film surface in the preparation process, so that the easy magnetization axis directions are vertical to the film surface. The spin electron device is prepared by plating each layer of substance on a substrate in the sequence from bottom to top by adopting the traditional methods of ion beam epitaxy, atomic layer deposition, magnetron sputtering and the like, and then carrying out the traditional nanometer device processing technologies of photoetching, etching and the like.
In summary, the spintronic device of the embodiment of the invention comprises a metal layer, a free magnetic layer, a fixed magnetic layer and an oxide layer; the first oxide layer is located between the metal layer and the free magnetic layer, and the second oxide layer is located between the free magnetic layer and the fixed magnetic layer, so that a single device can simultaneously realize storage and logic processing, the processing is convenient, and the transmission power consumption and the manufacturing cost are reduced.
FIG. 2 is a schematic diagram of the operation of a spintronic device in an embodiment of the present invention. As shown in fig. 1 and 2, the first port is connected to the metal layer, the second port is connected to the free magnetic layer, and the third port is connected to the fixed magnetic layer. And the direct-current voltage source is applied to two ends of the first port and the second port and is used for regulating and controlling the magnetic anisotropy of the free ferromagnetic metal layer, and when a positive voltage is applied, the magnetic effective field of the free ferromagnetic metal layer is weakened, and otherwise, the magnetic effective field of the free ferromagnetic metal layer is strengthened. The direct current source is applied to two ends of the second port and the third port, when current flows from the fixed magnetic layer to the free magnetic layer, spin polarization current can be generated, driving torque is generated in the free magnetic layer for writing, a resistance state reading circuit between the fixed magnetic layer and the free magnetic layer is used for measuring the self resistance of the MTJ to serve as an output parameter of logic calculation, and memory logic calculation can be achieved by combining voltage regulation magnetic anisotropy and a spin transfer torque effect.
For example, after a voltage is applied, since the energy barrier is weakened, a Spin Transfer Torque (STT) current is more likely to act on the magnetization direction of the free magnetic layer, and at this time, there must be a voltage value that acts on the magnetization direction of the free magnetic layer according to the current direction when it is positive; when the value of the current is negative, the magnetization direction of the free magnetic layer is not affected regardless of the direction of the current. Therefore, an IMP logic operation as well as a NAND logic operation can be realized by using an electric field-modulated magnetic anisotropy (VCMA) effect and a spin transfer torque effect according to a difference in initial states of magnetic tunnel junctions (MTJs including a free magnetic layer, a second oxide layer, and a fixed magnetic layer).
TABLE 1
Table 1 is a truth table for IMP logic. FIG. 3 is a diagram of the IMP logic timing for a spintronic device in an embodiment of the present invention. As shown in table 1 and fig. 3, when implementing IMP logic operation using a spintronic device, it is necessary to set the initial state of the magnetic tunnel junction to be an antiparallel resistance state, and the voltages applied to the first port and the second port are used as Input parameters p. When a voltage (V) is appliedVCMA) When the value is negative, p is 0, otherwise p is 1. The current applied between the third port and the second port is used as an Input parameter q, the applied current (I)STT) When the value is negative, q is 0, otherwise q is 1. Using MTJ resistance state (R)AP) As an Output parameter s, s is equal to 1 when it is in the anti-parallel resistance state, otherwise s is equal to 0. When a negative working voltage acts on the free magnetic layer to increase its effective magnetic field to a certain value, the injected spin-polarized current will not affect the magnetization direction of the free magnetic layer, and when a positive working voltage acts on the metal layer to weaken its effective magnetic field to a certain value, the injected spin-polarized current will easily flip the magnetic field of the free magnetic layerIn the conversion direction, the absolute values of the two working voltages should be the same, and the injection currents are the same. In addition, the voltage and the current required by the spintronic device during operation are fixed values and are not particularly limited, and can be calculated and selected according to the actual prepared device.
TABLE 2
Table 2 is a truth table for NAND logic. FIG. 4 is a NAND logic timing diagram for a spintronic device in an embodiment of the invention. As shown in table 2 and fig. 4, when implementing NAND logic operation using spintronic devices, it is necessary to set the initial state of the magnetic tunnel junction to be a parallel resistance state, and the voltages applied to the first port and the second port are used as the Input parameter p. When a voltage (V) is appliedVCMA) When the value is negative, p is 0, otherwise p is 1. The current applied between the third port and the second port is used as an Input parameter q, the applied current (I)STT) When the value is negative, q is 0, otherwise q is 1. Using MTJ resistance state (R)AP) As an Output parameter s, when it is in the parallel resistance state, s is equal to 1, otherwise s is equal to 0. When the magnetic effective field applied to the metal layer with a certain negative working voltage is increased to a certain proper value, the injected spin-polarized current cannot influence the magnetization direction of the layer, and when the magnetic effective field applied to the metal layer with a certain positive working voltage is decreased to a certain proper value, the injected spin-polarized current can easily reverse the magnetization direction of the layer, wherein the absolute values of the two working voltages are the same, and the magnitudes of the injected currents are the same. In addition, the voltage and the current required by the spintronic device during operation are fixed values and are not particularly limited, and can be calculated and selected according to the actual prepared device. In addition, NAND logic gates are general purpose logic gates with which all boolean logic operations can be implemented in combination.
FIG. 5 is a schematic view of a spintronic device in a first embodiment of the invention. FIG. 6 is a schematic diagram of a spintronic device in a second embodiment of the invention. As shown in fig. 5 to 6, the memory logic computing device includes:
a first switch tube 1, a second switch tube 2 and the spintronic device;
the metal layer of the spin electronic device is connected with the first end of the first switching tube 1;
a second end of the first switch tube 1 is connected with a Logic Line (LL, Logic Line), and a gate of the first switch tube 1 is connected with a Logic Control Line (LCL, Logic Control Line);
the free magnetic layer of the spin electronic device is connected with the first end of the second switch tube 2;
a second end of the second switch tube 2 is connected with a Source Line (SL), and a grid electrode of the second switch tube 2 is connected with a Word Line (WL);
the fixed magnetic layer of the spintronic device is connected to the Bit Line (BL).
In one embodiment, the first end of the first switch tube is a source electrode, and the second end of the first switch tube is a drain electrode; or, the second end of the first switch tube is a source electrode, and the first end of the first switch tube is a drain electrode. The first end of the second switch tube is a source electrode, and the second end of the second switch tube is a drain electrode; or the second end of the second switch tube is a source electrode, and the first end of the second switch tube is a drain electrode.
The memory logic computing device operates in the following mode:
1. storage mode
Turning on the WL, turning on the first switching transistor 1, and completing the writing and reading of the memory logic computing device as a memory device by turning on the SL and BL, as shown in fig. 5, operates in the same manner as a conventional spin transfer torque magnetic random access memory (STT-MRAM).
2. In-memory logic computation mode
As shown in fig. 6, turning on LL, turning on the second switch tube 2, turning on BL and SL as current inputs by turning on LCL and SL as voltage inputs, reading the result by BL and SL after the logic calculation operation, as the implementation of the memory logic calculation device, may include the following steps:
1. voltage is input between the metal layer and the free magnetic layer, and current is input between the fixed magnetic layer and the free magnetic layer to complete a corresponding logic operation.
2. The magnetic tunnel junction resistance state is read out by external circuitry as a result of the logic operation.
In summary, the memory logic computing device of the embodiment of the invention comprises a first switching tube, a second switching tube and a spintronic device; the metal layer of the spin electronic device is connected with the logic line through the first switch tube, the free magnetic layer is connected with the source line through the second switch tube, and the fixed magnetic layer is connected with the bit line, so that the single device can simultaneously realize storage and logic processing, the processing is convenient, and the transmission power consumption and the manufacturing cost are reduced.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (3)
1. An in-memory logic computing device, comprising:
the device comprises a first switching tube, a second switching tube and a spintronic device;
the spintronic device comprises: a metal layer; a free magnetic layer having a magnetization direction that changes in response to an external magnetic field; a fixed magnetic layer having a fixed magnetization direction; an oxide layer including a first oxide layer and a second oxide layer; the first oxide layer is located between the metal layer and the free magnetic layer; the second oxide layer is located between the free magnetic layer and the fixed magnetic layer;
the metal layer of the spintronic device is connected with the first end of the first switching tube;
the second end of the first switching tube is connected with a logic line, and the grid electrode of the first switching tube is connected with a logic control line;
the free magnetic layer of the spintronic device is connected with the first end of the second switch tube;
the second end of the second switch tube is connected with a source line, and the grid electrode of the second switch tube is connected with a word line;
the fixed magnetic layer of the spintronic device is connected with the bit line.
2. The memory logic computation device of claim 1,
the first end of the first switch tube is a source electrode, and the second end of the first switch tube is a drain electrode; or the like, or, alternatively,
the second end of the first switch tube is a source electrode, and the first end of the first switch tube is a drain electrode.
3. The memory logic computation device of claim 1,
the first end of the second switch tube is a source electrode, and the second end of the second switch tube is a drain electrode; or the like, or, alternatively,
the second end of the second switch tube is a source electrode, and the first end of the second switch tube is a drain electrode.
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