CN203661035U - Phase change memory-based nonvolatile logic gate circuit - Google Patents
Phase change memory-based nonvolatile logic gate circuit Download PDFInfo
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- CN203661035U CN203661035U CN201320865071.9U CN201320865071U CN203661035U CN 203661035 U CN203661035 U CN 203661035U CN 201320865071 U CN201320865071 U CN 201320865071U CN 203661035 U CN203661035 U CN 203661035U
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Abstract
The utility model discloses a phase change memory-based nonvolatile logic gate circuit, which comprises a first phase change memory, a second phase change memory, a first controllable switch element and a first resistor, wherein the first end of the first phase change memory serves as the first input end of an AND gate circuit; the first end of the second phase change memory serves as the second input end of the AND gate circuit; the first end of the first controllable switch element is connected with the second end of the first phase change memory; the second end of the first controllable switch element is grounded; one end of the first resistor and the first end of the second phase change memory are connected, and the other end of the first resistor is grounded; and the first end of the second phase change memory serves as the output end of the AND gate circuit. AND, OR, and NOT three kinds of basic Boolean logic calculation can be realized by nonvolatile resistance change based on material crystalline-amorphous phase change, information storage and processing in one logic gate circuit can be realized.
Description
Technical field
The utility model belongs to field of microelectronic devices, more specifically, relates to a kind of non-volatile logic gate circuit based on phase transition storage.
Background technology
In tradition von neumann machine framework, information storage separates with processing, and the storage memory of information and the processor of process information carry out the mutual of information by bus.But, along with the arrival of large data age, although memory and processor are at development, but still occur that so-called " von Neumann bottleneck " restricting computer and processing the performance of real time mass data and further improve: neither the Information Access speed of memory, information processing rate that neither processor, but connect both limited bus data transmission rate, limit memory and arithmetic unit and carrying out the transmission of mass data.The architectural framework that novel information Storage and Processing of future generation merges and electronic device are considered to break through the effective ways of this bottleneck.
The basic comprising unit of existing message handler is CMOS transistor logic door, carries out the processing of data based on level logic, and data result after treatment need to be transferred to special memory cell and store as internal memory, external memory.One can only be carried out information processing like this, and the gate that can not realize information storage cannot be applicable to the computer architecture that following Storage and Processing merges.Therefore, need a kind of novel non-volatile logic gate circuit, can either carry out information processing as boolean calculation, can realize again the non-volatile memories function of information simultaneously.Device shown in Chinese patent " a kind of logic gates based on memristor " (application number: 201210234665.X, date of application: on July 9th, 2012), the Nonvolatile resistance state of value based on memristor part changes to realize logical operation.But because leakage current cross-interference issue in device consistency, integrity problem and the array of memristor part is still unresolved, never can carry out mass market production.
Utility model content
For above defect or the Improvement requirement of prior art, the purpose of this utility model has been to provide a kind of logic gates that can simultaneously realize logical operation and information non-volatile memories.
For achieving the above object, according to an aspect of the present utility model, provide a kind of non-volatile logic gate circuit based on phase transition storage, comprised first-phase transition storage, second-phase transition storage, the first controllable switch element and the first resistance; The first end of first-phase transition storage is as the first input end of AND circuit, and the first end of described second-phase transition storage is as the second input of AND circuit; The first end of the first controllable switch element is connected with the second end of first-phase transition storage and the second end of second-phase transition storage, the second end ground connection of described the first controllable switch element; One end of described the first resistance is connected with the first end of described second-phase transition storage, the other end ground connection of described the first resistance; The first end of second-phase transition storage is as the output of AND circuit; When work, by closed the first controllable switch element, at described first input end input logic 0 or logical one, described first-phase transition storage is written to high-impedance state or low resistance state; And at described the second input input logic 0 or logical one, described second-phase transition storage is written to high-impedance state or low resistance state and realizes logical AND operation; By disconnecting the first controllable switch element, in described first input end input read pulse, and described the second input is unsettled, and realizes read operation by the output output of described AND circuit with operation result.
Wherein the low resistance state of the resistance of the first resistance and first-phase transition storage is at the same order of magnitude.
The utility model provides a kind of non-volatile logic gate circuit based on phase transition storage, comprises third phase transition storage, the 4th phase transition storage, the second controllable switch element and the second resistance; The first end of described third phase transition storage is as the first input end of OR circuit, and the first end of the 4th phase transition storage is as the second input of OR circuit; The first end of the second controllable switch element is connected with the second end of third phase transition storage and the second end of the 4th phase transition storage, the second end ground connection of the second controllable switch element; The first end of the second resistance is connected with the second end of third phase transition storage and the second end of the 4th phase transition storage, the second end ground connection of the second resistance; The second end of third phase transition storage is as the output of OR circuit; When work, by closed the second controllable switch element, at first input end input logic 0 or logical one, third phase transition storage is written to high-impedance state or low resistance state; And at the second input input logic 0 or logical one, the 4th phase transition storage is written to high-impedance state or low resistance state and realizes logic OR operation; By disconnecting the second controllable switch element, input read pulse at first input end and the second input simultaneously, and realize read operation by the output output exclusive disjunction result of OR circuit.
Wherein, the low resistance state of the resistance value of the second resistance and described third phase transition storage is at the same order of magnitude.
The utility model provides a kind of non-volatile logic gate circuit based on phase transition storage, comprises the 5th phase transition storage and the 3rd resistance; The first end of described the 3rd resistance is as the input of reading of not circuit; Described the 3rd resistance and described the 5th phase transition storage series connection ground connection; Described the 3rd resistance and described the 5th phase transition storage be connected in series end as the output of logic input terminal and described not circuit; When work, by logic input terminal input logic 0 or logical one, described the 5th phase transition storage is written to high-impedance state or low resistance state is realized logic NOT operation; By reading input input read pulse, realize read operation by the output output inverse result of described not circuit.
Wherein, the high-impedance state of the resistance value of the 3rd resistance and described the 5th phase transition storage is at the same order of magnitude.
The non-volatile resistance state variation of the utility model based on the phase transformation of phase-change material crystalline state-amorphous state realizes "AND", "or", " non-" three kinds of basic boolean calculations, and can realize the beneficial effect that simultaneously carries out the Storage and Processing of information a logic gates, be expected to the novel computer architectural framework merging for building information Storage and Processing of future generation, break through in traditional computer framework because information Storage and Processing separates " von Neumann bottleneck " problem causing.
Accompanying drawing explanation
Fig. 1 (a) is the phase transition storage typical case I-V characteristic curve that the utility model embodiment provides.
Fig. 1 (b) is the phase transition storage typical pulse switching characteristic curve that the utility model embodiment provides.
Fig. 2 is the AND circuit schematic diagram that the utility model embodiment provides.
Fig. 3 is the AND circuit test waveform figure that the utility model embodiment provides.
Fig. 4 is the OR circuit schematic diagram that the utility model embodiment provides.
Fig. 5 is the OR circuit test waveform figure that the utility model embodiment provides.
Fig. 6 is the not circuit schematic diagram that the utility model embodiment provides.
Fig. 7 is the not circuit test waveform figure that the utility model embodiment provides.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.In addition,, in each execution mode of described the utility model, involved technical characterictic just can combine mutually as long as do not form each other conflict.
For the defect of prior art, the purpose of this utility model is to provide a kind of non-volatile logic gate circuit based on phase transition storage, comprises and door or door and three kinds of basic Boolean logic circuit of not gate; Be intended to the function of the Storage and Processing fusion of the information that realizes.Phase transition storage is considered to the next generation and has the nonvolatile semiconductor memory member of potentiality, has that access speed is fast, storage density is high, erasable number of times advantages of higher, and by mass market, is suitable for building non-volatile logic door.
The utility model compared with prior art, can the non-volatile resistance state variation based on the phase transformation of phase-change material crystalline state-amorphous state realize "AND", "or", " non-" three kinds of basic boolean calculations, and can realize the beneficial effect that simultaneously carries out the Storage and Processing of information a logic gates, be expected to the novel computer architectural framework merging for building information Storage and Processing of future generation, break through in traditional computer framework because information Storage and Processing separates " von Neumann bottleneck " problem causing.
Referring now to the accompanying drawing that one exemplary embodiment of the present utility model is shown, the utility model is more fully described.But, can implement the utility model by many different forms, and the utility model should not be construed and is limited to the embodiment listing here; Or rather, provide these embodiment so that the disclosure is more thoroughly with comprehensive, and pass on fully idea of the present utility model to those skilled in the art.
In the utility model, under the Joule heat effect producing at electric current as the phase transition storage of logic gates core devices, produce phase transformation, the SET pulse that represents logical one makes phase-change memory cell be transformed into low-resistance crystalline state from high-resistance amorphous state, represents that the RESET pulse of logical zero makes phase-change memory cell be transformed into high-resistance amorphous state from low-resistance crystalline state.
Fig. 1 (a) is the phase transition storage typical case I-V characteristic curve that the utility model embodiment provides.With reference to figure 1 (a), device initial state is high resistant amorphous state, exceedes its threshold value when applying voltage, and its state-transition becomes low-resistance crystalline state.High resistant amorphous state and low-resistance crystalline state are all non-volatile Resistance states.
Fig. 1 (b) is the phase transition storage typical pulse switching characteristic curve that the utility model embodiment provides.With reference to figure 1 (b), be 0.8V when device being applied to pulse amplitude, the SET pulse that pulse duration is 200ns, device is switched to low resistance state from high-impedance state; Be 2V when device being applied to pulse amplitude, the RESET pulse that pulse duration is 30ns, device is switched to high-impedance state from low resistance state.
Fig. 2 is of the present utility model based on phase transition storage AND circuit schematic diagram.With reference to figure 2, the AND circuit based on phase transition storage comprises: first-phase transition storage 101, second-phase transition storage 102, the first controllable switch element 103, the first resistance 104; The first end of first-phase transition storage 101 is as the first input end 105 of AND circuit, and the first end of second-phase transition storage 102 is as the second input 106 of AND circuit; The first end of the first controllable switch element 103 is connected with the second end of first-phase transition storage 101 and the second end of second-phase transition storage 102, the second end ground connection of the first controllable switch element 103; One end of the first resistance 104 is connected with the first end of second-phase transition storage 102, the other end ground connection of the first resistance 104; The first end of second-phase transition storage 102 is as the output 107 of AND circuit.
While carrying out logical operation, closed the first controllable switch element 103, at first end 105 input logic 0 or the logical ones of first-phase transition storage 101, is written to high-impedance state or low resistance state by first-phase transition storage 101; At second-phase transition storage 102 first end 106 input logic 0 or logical ones, second-phase transition storage 102 is written to high-impedance state or low resistance state.While carrying out read operation, disconnect the first controllable switch element 103, input read pulse at the first input end 105 of first-phase transition storage 101, the second input 106 is unsettled, is exported and operation result by output 107.
In the utility model embodiment, the low resistance state of the resistance value of the first resistance 104 and first-phase transition storage 101 and second-phase transition storage 102 is at the same order of magnitude, when first-phase transition storage 101 or second-phase transition storage 102 are in high-impedance state, be input as 00,01 or at 10 o'clock, the voltage drop of input is mainly distributed on first-phase transition storage 101 or second-phase transition storage 102, and the output pressure drop on the first resistance 104 is very little; Only have first-phase transition storage 101 and second-phase transition storage 102 all in low resistance state, be input as at 11 o'clock, the resistance value that first-phase transition storage 101 and second-phase transition storage 102 are connected is just less, and the first resistance 104 is on the same order of magnitude, exports larger voltage on the first resistance 104.
Fig. 3 is the embodiment oscillogram according to the utility model AND circuit, and in circuit, the high low resistance of first-phase transition storage 101 and second-phase transition storage 102 is all 200k Ω and 10k Ω, and the first resistance 104 is 10k Ω.The SET pulse that represents logical one is square wave, and pulse amplitude is 0.8V, and pulse duration is 200ns; The RESET pulse that represents logical zero is also square wave, and pulse amplitude is 2V, and pulse duration is 30ns.
With reference to figure 3, in the time that input logic signal is 00, first-phase transition storage 101 resistance are 200k Ω, and second-phase transition storage 102 resistance are also 200k Ω.While carrying out read operation, apply the read pulse of 200mV, a 10ms at the first end of first-phase transition storage 101, obtain the output signal of 1.98mV, a 10ms at the first end of second-phase transition storage 102; In the time that input logic signal is 01, first-phase transition storage 101 resistance are 200k Ω, and second-phase transition storage 102 resistance are 10k Ω.While carrying out read operation, apply the read pulse of 200mV, a 10ms at the first end of first-phase transition storage 101, obtain the output signal of 3.85mV, a 10ms at the first end of second-phase transition storage 102; In the time that input logic signal is 10, first-phase transition storage 101 resistance are 10k Ω, and second-phase transition storage 102 resistance are 200k Ω.While carrying out read operation, apply the read pulse of 200mV, a 10ms at the first end of first-phase transition storage 101, obtain the output signal of 3.85mV, a 10ms at the first end of second-phase transition storage 102; In the time that input logic signal is 11, first-phase transition storage 101 resistance are 10k Ω, and second-phase transition storage 102 resistance are also 10k Ω.While carrying out read operation, apply the read pulse of 200mV, a 10ms at the first end of first-phase transition storage 101, obtain the output signal of 66.7mV, a 10ms at the first end of second-phase transition storage 102.
Fig. 4 is of the present utility model based on phase transition storage OR circuit schematic diagram.With reference to figure 4, the OR circuit based on phase transition storage comprises: third phase transition storage 301, the 4th phase transition storage 302, the second controllable switch element 303, the second resistance 304; The first end 305 of third phase transition storage 301 is as the first input end of OR circuit, and the first end 306 of the 4th phase transition storage 302 is as the second input of OR circuit; The first end of the second controllable switch element 303 is connected with the second end of third phase transition storage 301 and the second end of the 4th phase transition storage 302, the second end ground connection of the second controllable switch element 303; The first end of the second resistance 304 is connected with the second end of third phase transition storage 301 and the second end of the 4th phase transition storage 302, the second end ground connection of the first resistance 104; The second end 307 of third phase transition storage 301 is as the output of OR circuit.
While carrying out logical operation, closed the second controllable switch element 303, at first end 305 input logic 0 or the logical ones of third phase transition storage 301, is written to high-impedance state or low resistance state by third phase transition storage 301; At the 4th phase transition storage 302 first end 306 input logic 0 or logical ones, the 4th phase transition storage 302 is written to high-impedance state or low resistance state.
While carrying out read operation, disconnect the second controllable switch element 303, input read pulse at the first end of third phase transition storage 301 and the first end of the 4th phase transition storage 302 simultaneously, the second end 307 of third phase transition storage 301 is exported operation result.
In the utility model embodiment, the low resistance state of the resistance value of the second resistance 304 and third phase transition storage 301 and the 4th phase transition storage 302 is at the same order of magnitude, when third phase transition storage 301 and the 4th phase transition storage 302 are all in high-impedance state, be input as at 00 o'clock, the voltage drop of input is mainly distributed on third phase transition storage 301 and the 4th phase transition storage 302, and the output pressure drop on the second resistance 304 is very little; When third phase transition storage 301 or the 4th phase transition storage 302 are in low resistance state, be input as 01,10 or at 11 o'clock, the resistance value of third phase transition storage 301 and the 4th phase transition storage 302 parallel connections is just less, on the same order of magnitude, on the second resistance 304, export larger voltage with the second resistance 304.
Fig. 5 is the embodiment oscillogram illustrating according to the utility model OR circuit, and in circuit, the high low resistance of third phase transition storage 301 and the 4th phase transition storage 302 is all 200k Ω and 10k Ω, and the second resistance 304 is 10k Ω.The SET pulse that represents logical one is square wave, and pulse amplitude is 0.8V, and pulse duration is 200ns; The RESET pulse that represents logical zero is also square wave, and pulse amplitude is 2V, and pulse duration is 30ns.
With reference to figure 5, in the time that input logic signal is 00, third phase transition storage 301 resistance are 200k Ω, and the 4th phase transition storage 302 resistance are also 200k Ω.While carrying out read operation, apply the read pulse of 200mV, a 10ms at the first end of third phase transition storage 301 and the first end of the 4th phase transition storage 302, obtain the output signal of 7.69mV, a 10ms at third phase transition storage 301 second ends.In the time that input logic signal is 01, third phase transition storage 301 resistance are 200k Ω, and the 4th phase transition storage 302 resistance are 10k Ω.While carrying out read operation, apply the read pulse of 200mV, 10ms at the first end of third phase transition storage 301 and the first end of the 4th phase transition storage 302, obtain the output signal of 101mV, a 10ms at the second end of third phase transition storage 301.In the time that input logic signal is 10, third phase transition storage 301 resistance are 10k Ω, and the 4th phase transition storage 302 resistance are 200k Ω.While carrying out read operation, apply the read pulse of 200mV, 10ms at the first end of third phase transition storage 301 and the first end of the 4th phase transition storage 302, obtain the output signal of 101mV, a 10ms at the second end of third phase transition storage 301.In the time that input logic signal is 11, third phase transition storage 301 resistance are 10k Ω, and the 4th phase transition storage 302 resistance are 10k Ω.While carrying out read operation, apply the read pulse of 200mV, 10ms at the first end of third phase transition storage 301 and the first end of the 4th phase transition storage 302, obtain the output signal of 133mV, a 10ms at the second end of third phase transition storage 301.
Fig. 6 is of the present utility model based on phase transition storage not circuit schematic diagram.With reference to figure 6, the not circuit based on phase transition storage comprises: the 5th phase transition storage 501 and the 3rd resistance 502; The first end 503 of the 3rd resistance 502 is as the input of reading of not circuit; The first end 504 of the 5th phase transition storage 501 is as logic input terminal and output; The 3rd resistance 502 and the 5th phase transition storage 501 ground connection of connecting.
While carrying out logical operation, at first end 504 input logic 0 or the logical ones of the 5th phase transition storage 501, the 5th phase transition storage 501 is written to high-impedance state or low resistance state.
While carrying out read operation, in the first end input read pulse of the 3rd resistance 502, the first end 504 of the 5th phase transition storage 501 is exported operation result.
In the utility model embodiment, the high-impedance state of the resistance value of the 3rd resistance 502 and the 5th phase transition storage 501 is at the same order of magnitude, when the 5th phase transition storage 501 is in low resistance state, be input as at 1 o'clock, the voltage drop of reading input is mainly distributed on the 3rd resistance 502, and the output pressure drop on the 5th phase transition storage 501 is very little; Only have the 5th phase transition storage 501 in high-impedance state, be input as at 0 o'clock, the asks that the resistance value of phase transition storage 501 is just larger, and the 3rd resistance 502 is on the same order of magnitude, the larger voltage of output on the 5th phase transition storage.
Fig. 7 is the embodiment oscillogram according to the utility model not circuit, and in circuit, the high low resistance of the 5th phase transition storage 501 is 200k Ω and 10k Ω, and the 3rd resistance 502 is 140k Ω.The SET pulse that represents logical one is square wave, and pulse amplitude is 0.8V, and pulse duration is 200ns; The RESET pulse that represents logical zero is also square wave, and pulse amplitude is 2V, and pulse duration is 30ns.
With reference to figure 7, in the time that input logic signal is 0, the 5th phase transition storage 501 resistance are 200k Ω.While carrying out read operation, apply the read pulse of 200mV, a 10ms at the first end of the 3rd resistance 502, obtain the output signal of 156mV, a 10ms at the first end 504 of the 5th phase transition storage 501; In the time that input logic signal is 1, the 5th phase transition storage 501 resistance are 10k Ω.While carrying out read operation, apply the read pulse of 200mV, a 10ms at the first end of the 3rd resistance 502, obtain the output signal of 13.3mV, a 10ms at the first end 504 of the 5th phase transition storage 501.
Directly non-volatile being stored in circuit state of its operation result of logic gates of the present utility model, calculates and is stored in thereby have the feature merging in individual unit or circuit.The realization of logical operation is the stable reversible transition characteristic based on device, can effectively reduce the misoperation of logical operation, guarantees the reproducibility and reliability of computing.In addition, "AND", "or" and " non-" are all concurrent operation, only need single stepping to complete, efficiently succinct.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.
Claims (6)
1. the non-volatile logic gate circuit based on phase transition storage, it is characterized in that, comprise first-phase transition storage (101), second-phase transition storage (102), the first controllable switch element (103) and the first resistance (104);
The first end of described first-phase transition storage (101) is as the first input end (105) of AND circuit, and the first end of described second-phase transition storage (102) is as second input (106) of AND circuit; The first end of described the first controllable switch element (103) is connected with the second end of first-phase transition storage (101) and the second end of second-phase transition storage (102), the second end ground connection of described the first controllable switch element (103); One end of described the first resistance (104) is connected with the first end of described second-phase transition storage (102), the other end ground connection of described the first resistance (104); The first end of second-phase transition storage (102) is as the output (107) of AND circuit;
When work, by closed the first controllable switch element (103), at described first input end (105) input logic 0 or logical one, described first-phase transition storage (101) is written to high-impedance state or low resistance state; And at described the second input (106) input logic 0 or logical one, described second-phase transition storage (102) is written to high-impedance state or low resistance state and realizes logical AND operation;
By disconnecting the first controllable switch element (103), in described first input end (105) input read pulse, and described the second input (106) is unsettled, and realize read operation by output (107) output of described AND circuit with operation result.
2. non-volatile logic gate circuit as claimed in claim 1, is characterized in that, the low resistance state of the resistance of described the first resistance (104) and described first-phase transition storage (101) is at the same order of magnitude.
3. the non-volatile logic gate circuit based on phase transition storage, it is characterized in that, comprise third phase transition storage (301), the 4th phase transition storage (302), the second controllable switch element (303) and the second resistance (304);
The first end of described third phase transition storage (301) is as the first input end (305) of OR circuit, and the first end of the 4th phase transition storage (302) is as second input (306) of OR circuit; The first end of the second controllable switch element (303) is connected with the second end of third phase transition storage (301) and the second end of the 4th phase transition storage (302), the second end ground connection of the second controllable switch element (303); The first end of the second resistance (304) is connected with the second end of third phase transition storage (301) and the second end of the 4th phase transition storage (302), the second end ground connection of the second resistance (304); The second end of third phase transition storage (301) is as the output (307) of OR circuit;
When work, by closed the second controllable switch element (303), at first input end (305) input logic 0 or logical one, third phase transition storage (301) is written to high-impedance state or low resistance state; And at the second input (306) input logic 0 or logical one, the 4th phase transition storage (302) is written to high-impedance state or low resistance state and realizes logic OR operation;
By disconnecting the second controllable switch element (303), input read pulse at first input end (305) and the second input (306) simultaneously, and realize read operation by output (307) the output exclusive disjunction result of OR circuit.
4. logic gates as claimed in claim 3, is characterized in that, the low resistance state of the resistance value of described the second resistance (304) and described third phase transition storage (301) is at the same order of magnitude.
5. the non-volatile logic gate circuit based on phase transition storage, is characterized in that, comprises the 5th phase transition storage (501) and the 3rd resistance (502);
The first end of described the 3rd resistance (502) is read input (503) as not circuit; Described the 3rd resistance (502) and described the 5th phase transition storage (501) series connection ground connection; Described the 3rd resistance (502) and described the 5th phase transition storage (501) be connected in series end as the output (505) of logic input terminal (504) and described not circuit;
When work, by logic input terminal (504) input logic 0 or logical one, described the 5th phase transition storage (501) is written to high-impedance state or low resistance state is realized logic NOT operation;
By reading input (503) input read pulse, realize read operation by output (505) the output inverse result of described not circuit.
6. logic gates as claimed in claim 5, is characterized in that, the high-impedance state of the resistance value of described the 3rd resistance (502) and described the 5th phase transition storage (501) is at the same order of magnitude.
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| CN201320865071.9U CN203661035U (en) | 2013-12-25 | 2013-12-25 | Phase change memory-based nonvolatile logic gate circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103716038A (en) * | 2013-12-25 | 2014-04-09 | 华中科技大学 | Nonvolatile logic gate circuit based on phase change memories |
| CN104851456A (en) * | 2015-04-24 | 2015-08-19 | 华中科技大学 | Universal programming module based on memristor and operation method thereof |
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2013
- 2013-12-25 CN CN201320865071.9U patent/CN203661035U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103716038A (en) * | 2013-12-25 | 2014-04-09 | 华中科技大学 | Nonvolatile logic gate circuit based on phase change memories |
| CN103716038B (en) * | 2013-12-25 | 2016-05-25 | 华中科技大学 | A kind of non-volatile logic gate circuit based on phase transition storage |
| CN104851456A (en) * | 2015-04-24 | 2015-08-19 | 华中科技大学 | Universal programming module based on memristor and operation method thereof |
| CN104851456B (en) * | 2015-04-24 | 2017-09-29 | 华中科技大学 | A kind of universal programming module and its operating method based on memristor |
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