CN107833892A - A kind of oxide fill method of top layer selection grid tangent line - Google Patents
A kind of oxide fill method of top layer selection grid tangent line Download PDFInfo
- Publication number
- CN107833892A CN107833892A CN201711167889.2A CN201711167889A CN107833892A CN 107833892 A CN107833892 A CN 107833892A CN 201711167889 A CN201711167889 A CN 201711167889A CN 107833892 A CN107833892 A CN 107833892A
- Authority
- CN
- China
- Prior art keywords
- layer
- tangent line
- cmp
- selection grid
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a kind of oxide fill method of top layer selection grid tangent line, by the way that the filling of oxide material in top layer selection grid tangent line raceway groove is used into high-density plasma chemical vapor deposition method (HDP CVD), obtained fill oxide can effectively resist harmful etching that fluoro-gas removes in follow-up tungsten grid forming process, filled so as to avoid the formation of etching raceway groove by tungsten deposition, and then unnecessary tungsten residual is avoided, improve the properties of product of 3D NAND flash memory structures.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of preparation method of 3D NAND flash memory structures, specifically
Filled out to avoid occurring in subsequent gate polar curve and tungsten common source forming process a kind of oxide of top layer selection grid tangent line of tungsten residual
Fill method.
Background technology
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges：Physics limit, the existing developing technique limit and storage electronics are close
Spend limit etc..In this context, the production that is difficult and pursuing lower unit storage unit run into for solution planar flash memory
Cost, a variety of three-dimensional (3D) flash memories structures are arisen at the historic moment, such as 3D NOR (3D or non-) flash memories and 3D
NAND (3D with non-) flash memory.
Wherein, storage element is used three dimensional pattern stacked in multi-layers by 3D NAND using its small size, Large Copacity as starting point
It is highly integrated be design concept, produce high unit area storage density, the memory of efficient storage unit performance,
Prevailing technology through being designed and produced as emerging memory.
Meanwhile in current 3D NAND structures, be by by memory cell be three-dimensionally disposed in substrate come
Integration density, wherein channel layer is improved to stand vertically on substrate, grid be divided into lower floor's selection gate, middle level control gate with
And top layer selection gate (Top Select Gate) three parts, by the way that signal is distributed in three groups of gate electrodes to reduce
Crosstalk between signal.Specifically, the device of the upper and lower is used as selection transistor --- and gate height/thickness is larger
Vertical MOSFET, gate dielectric layer are conventional individual layer high-g value；The device in middle level is used as memory cell string, and gate height/
Thickness is smaller, and gate dielectric layer is tunnel layer, accumulation layer, the stacked structure on barrier layer.
Wherein, top layer selection grid tangent line (Top Select Gate Cut) generally is provided with the middle part of finger memory block,
So that the top layer selection grid (Top Select Gate) for referring to memory block is divided into two parts, and top layer selection grid tangent line is usual
Formed by oxide material, and prepared using atom layer deposition process (ALD).Typically use top layer selection grid tangent line
The etching technics of (Top Select Gate Cut), the layer 2-3 (2-3Tiers) that ON is stacked to top layer etches away, as stop
(Block) raceway groove, specific preparation technology flow comprise the following steps (referring to Fig. 1 a-1f)：
S1：Multilayer lamination structure is formed, referring to Fig. 1 a, first, there is provided substrate 10, the substrate surface is formed with multilayer
The interlayer dielectric layer 20 and sacrificial dielectric layer 30 being staggeredly stacked, the sacrificial dielectric layer 30 are formed at adjacent interlayer dielectric layer
Between 20；The interlayer dielectric layer 20 is generally silica, the sacrificial dielectric layer 30, so as to form ON stacked structures (ON
Stacks)；
S2：The ledge structure of stacked structure is formed, referring to Fig. 1 b, prior art can be used by forming the technique of ledge structure
In conventional process；
S3：Connector oxide skin(coating) is deposited, is to deposit connector oxide skin(coating) to cover the Step-edge Junction first referring to Fig. 1 c
Structure, the connector oxide skin(coating) is then planarized using chemical mechanical milling tech (CMP)；
S4：Photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut), it is first referring specifically to Fig. 1 d
First, composite hard mask layer 40 is formed in the connector oxide layer surface of planarization, it is described to answer mask layer to include the nothing sequentially formed
The photoresist layer that the SiON layers 42 and SiON layer surfaces that amorphous carbon layer (A-C) 41, amorphous carbon layer (A-C) surface are formed are formed
43；Then photoetching is implemented to remove relevant position needing to be formed the position of selection grid tangent line (Top Select Gate Cut)
The photoresist layer 43 to form photoetching raceway groove 50；
S5：Performed etching to form top layer selection grid tangent line (Top Select Gate Cut), referring to Fig. 1 e, specifically
For using the etching technics of routine, along the photoetching raceway groove 50, etching forms top layer selection grid tangent line (Top Select downwards
Gate Cut) raceway groove 60, and composite hard mask layer is removed to expose connector oxide layer surface；In the process, it is desirable to etch
The position of the interlevel oxide dielectric layer 21 of ON stacked structures is rested on, and not destroy the silicon nitride sacrifice of oxide underlayer
Dielectric layer；
S6：Top layer selection grid tangent line (Top Select Gate Cut) raceway groove is filled, referring to Fig. 1 f, is specially
Top layer selection grid tangent line oxide material 70 is filled in raceway groove 60 using atom layer deposition process (ALD).
And back-end process (the Back after top layer selection grid tangent line (Top Select Gate Cut) technique is formed
End of Line, abbreviation BEOL) in (referring to Fig. 2 a-d, wherein 70 ' be ALD fill oxides, 80 be that tungsten is filled), also have
The forming step (referring to Fig. 2 a) of tungsten grid (W-Gate), tungsten common source (W-Array Common Source, abbreviation W-ACS)
Forming step (referring to Fig. 2 c) etc..
However, in above-mentioned steps S6, although carrying out oxide filling using atom layer deposition process (ALD) can obtain
The good filling effect of top layer selection grid tangent line raceway groove (Top Select Gate Cut Trench) is obtained, i.e., without obvious
Gap (Seam) or room (Void), but the oxide that so filling is formed has than the increasing of remainder using plasma
Prepared by the vapour deposition process (Plasma Enhanced Chemical Vapor Deposition, abbreviation PECVD) of extensive chemical
By the corrosion rate of the faster hydrofluoric acid of medium of oxides layer (HF) wet etching (Wet Etch) and the corrosion speed of fluoro-gas
Rate, therefore in follow-up annealing treating process step and the forming step of tungsten grid (W-Gate), it is easy to due to hydrofluoric acid
(HF) removing (Fluorin Outgas) of wet etching (Wet Etch) and/or fluoro-gas and cause ALD filling oxidation
Thing 70 ' is etched and causes top area (Top Area) butterfly (Dishing) shape defect occur, in addition formed groove 90 (referring to
Fig. 2 b), and groove 90 is in the forming step of follow-up tungsten common source (W-ACS), deposited tungsten filling 80 fill up (referring to
Fig. 2 c), and will also be difficult to be removed in follow-up tungsten common source (W-ACS) cmp (CMP) and be remained as tungsten
80 ' (W Residue) (referring to Fig. 2 d and Fig. 3), so as to directly affect the performance of three-dimensional (3D) flash memories.
Therefore, how to avoid in the tungsten gate line after top layer selection grid tangent line is formed and tungsten common source forming process
There is tungsten residual, it is most important for the preparation and performance for three-dimensional (3D) flash memories, it is always people in the art
Member endeavours the direction of research.
The content of the invention
It is an object of the invention to provide a kind of tungsten gate line avoided after top layer selection grid tangent line is formed and tungsten to be total to
Occur the oxide fill method of the top layer selection grid tangent line of tungsten residual in source electrode forming process, dodged so as to improve three-dimensional (3D)
Deposit the performance of memory.
To achieve these goals, the present invention proposes a kind of oxide fill method of top layer selection grid tangent line, including
Following steps：
Multilayer lamination structure is formed in substrate surface, specifically, first, there is provided substrate, the substrate surface is formed with more
The interlayer dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer that layer is staggeredly stacked are formed between adjacent interlayer dielectric layer；
Then, the smooth surface of top layer interlayer dielectric layer is obtained using chemical mechanical milling tech；
One layer of cmp cutoff layer is deposited on the smooth surface；
Photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, first in chemistry
Compound lithography layer is formed on the surface of mechanical lapping cutoff layer；Then needing to form selection grid tangent line (Top Select Gate
Cut photoetching is implemented in position)；
Performed etching to form top layer selection grid tangent line (Top Select Gate Cut), specifically, being carved using conventional
Etching technique forms the raceway groove of top layer selection grid tangent line (Top Select Gate Cut) in foregoing photoetching position, and described in removal
Compound lithography layer is to expose the surface of the cmp cutoff layer；
Top layer selection grid tangent line (Top Select Gate Cut) raceway groove is filled, specifically, using high density
Plasma chemical vapor deposition method (High Density Plasma CVD, HDP-CVD) deposits filling top in the raceway groove
Layer selection grid tangent line oxide material；
Unnecessary top layer selection grid tangent line oxide material is removed, specifically, using chemical mechanical milling tech, will be right
In the cmp cutoff layer table when top layer selection grid tangent line (Top Select Gate Cut) raceway groove is filled
The unnecessary top layer selection grid tangent line oxide material that face is formed removes, to expose cmp cut-off layer surface and shape
Into smooth surface；
Remove the cmp cutoff layer.
Further, the inter-level dielectric layer material is oxide, and the sacrificial dielectric layer material is silicon nitride, so as to
Form ON stacked structures (ON Stacks).
Further, the cmp cutoff layer is silicon nitride hardmask layer (SiN HM).
Further, the removal cmp cutoff layer, using phosphoric acid (H3PO4) solution.
Further, the compound lithography layer includes amorphous carbon layer (A-C), SiON layers and the photoresist sequentially formed
Layer.
Further, it is described to etch a certain interlayer dielectric layer for resting on stacked structure；
Especially preferred, the etching rests on 2nd, 3rd or 4th interlayer dielectric layer of the stacked structure since top.
Further, to unnecessary top layer selection grid tangent line (Top Select Gate Cut) raceway groove fill oxide
Remove, using chemical mechanical milling tech (CMP).
Further, the chemical mechanical milling tech (CMP) in the step of substrate surface forms multilayer lamination structure is
The relatively low cmp of grinding rate (Buffer CMP).
Further, after the cmp cutoff layer is removed, in addition to depositing trench connector oxide
(CH Plug Oxide), specifically, being deposited on the surface of top layer interlayer dielectric layer and top layer selection grid tangent line oxide material
Connector oxide, and form silicon nitride hardmask layer in connector oxide surface.
Compared with prior art, the beneficial effects are mainly as follows：
First, in top layer selection grid tangent line raceway groove of the invention the filling of oxide material use high-density plasma
Vapour deposition (HDP-CVD) is learned, obtained fill oxide can effectively be resisted fluorine-containing in follow-up tungsten grid forming process
Harmful etching of gas removal, filled so as to avoid the formation of etching raceway groove by tungsten deposition, and then avoid unnecessary tungsten
Residual；
Second, one layer of silicon nitride hardmask layer (SiN HM) of deposition is used as cmp cutoff layer, after enabling to
It is continuous unnecessary high-density plasma chemical vapor deposition method is effectively removed using chemical mechanical milling tech to deposit obtained oxidation
Thing material.
3rd, using phosphoric acid (H3PO4) solution, cmp cutoff layer is being removed meanwhile, it is capable to avoid for oxygen
The removal of compound material；
Pass through above-mentioned steps so that can't be produced in the back-end process that follow-up tungsten grid is formed and tungsten common source is formed
Raw tungsten residual, so as to improve the performance of three-dimensional (3D) flash memories.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is general for this area
Logical technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to this hair
Bright limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 a-f are the process flow diagram for forming top layer selection grid tangent line in the prior art；
Fig. 2 a-d are the process flow diagram for being subsequently formed tungsten grid and tungsten common source in the prior art；
Fig. 3 is the stereoscan photograph of tungsten residual in the prior art；
Fig. 4 a-g are the process flow diagram that top layer selection grid tangent line is formed in the present invention；
Fig. 5 a-c are the process flow diagram that tungsten grid and tungsten common source are subsequently formed in the present invention.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this is shown in accompanying drawing
Disclosed illustrative embodiments, it being understood, however, that may be realized in various forms the disclosure without that should be illustrated here
Embodiment is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can incite somebody to action
The scope of the present disclosure is completely communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known work(
Energy and structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that in any practical embodiments
In exploitation, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think this development be probably it is complicated and
It is time-consuming, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.According to following explanation and right
Claim, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing makes using very simplified form and
With non-accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 4 a-4g are refer to, in the present embodiment, it is proposed that a kind of etching process of top layer selection grid tangent line, bag
Include following steps：
S100：Multilayer lamination structure is formed in substrate surface, and obtains the smooth surface of top layer interlayer dielectric layer；
S200：One layer of cmp cutoff layer is deposited on the smooth surface；
S300：Photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut)；
S400：Performed etching to form top layer selection grid tangent line (Top Select Gate Cut)；
S500：Top layer selection grid tangent line (Top Select Gate Cut) raceway groove is filled；
S600：Remove unnecessary top layer selection grid tangent line oxide material；
S700：Remove the cmp cutoff layer；
S800：Depositing trench connector oxide.
Specifically, refer to Fig. 4 a, in the step s 100, step S110, the shape on the surface of substrate 100 are carried out first
Into multilayer lamination structure, the interlayer dielectric layer 110 of multi-layer intercrossed stacking is specially formed on the surface of substrate 100 and is sacrificed
Dielectric layer 120, the sacrificial dielectric layer 120 are formed between adjacent interlayer dielectric layer 110, wherein, the substrate 100 is
Silicon substrate, the interlayer dielectric layer 110 are oxide, and for example, tetraethyl orthosilicate (TEOS), the sacrificial dielectric layer 120 are
Nitride, for example, silicon nitride (SiN), so as to form the ON stacked structures of multilayer (ON Stacks)；Then carry out step
S120, the smooth surface 130 of top layer interlayer dielectric layer 110 is obtained using chemical mechanical milling tech (CMP), based on just
The characteristic of silester (TEOS), the chemical mechanical milling tech (CMP) in step S120 are relatively low using grinding rate
Cmp (Buffer CMP).
Fig. 4 b are refer to, in step s 200, one layer of cmp section are deposited on the smooth surface
Only layer 140, in order to give full play to the effect of cmp cut-off, the cmp cutoff layer 140 is hard material
The bed of material, preferably silicon nitride hardmask layer (SiN HM).
Fig. 4 c are refer to, in step S300, are entered to form top layer selection grid tangent line (Top Select Gate Cut)
Row photoetching, specifically, first carry out step S310, compound lithography layer 150 is formed on stacked structure surface, specifically include with
Lower step：S311, formation amorphous carbon layer (A-C) 151 is used as light-absorption layer on the surface of stacked structure；Optionally, walked
Rapid S312, SiON layers are formed on the surface of amorphous carbon layer (A-C) as anti-reflecting layer 152；Step S313 is carried out, compound
The surface of lithography layer 150 forms photoresist layer 153；Then step S320 is carried out, is needing to form selection grid tangent line (Top
Select Gate Cut) position implement photoetching and form photoetching raceway groove 160 to remove the photoresist 153 of relevant position；
Fig. 4 d are refer to, in step S400, are entered to form top layer selection grid tangent line (Top Select Gate Cut)
Row etching, specifically, using conventional etching technics, along the photoetching raceway groove 160, etching forms top layer selection grid tangent line downwards
(Top Select Gate Cut) raceway groove 170, and compound lithography layer 150 is removed to expose cmp cutoff layer 140
Surface.Wherein described etch-stop stays in a certain interlevel oxide dielectric layer 110 of stacked structure and can not be nitride sacrifice
Dielectric layer 120, in the present embodiment, preferably described etching rest on 3rd interlayer dielectric layer of the stacked structure since top
110, the number of plies of the interlevel oxide dielectric layer 110 specifically stopped certainly can be determined according to being actually needed completely, such as
Can also be the 2nd, the 4th since top or other layers.
Fig. 4 e are refer to, in step S500, to top layer selection grid tangent line (Top Select Gate Cut) raceway groove 170
Oxide 180 is carried out to fill, the technique of filling uses high-density plasma chemical vapor deposition method (HDP-CVD), and in order to fill
That divides is filled to top layer selection grid tangent line (Top Select Gate Cut) raceway groove 170, and the HDP-CVD's carried out is heavy
Product technique, will necessarily form unwanted layer of oxide material 180 ' on the surface of cmp cutoff layer 140.
Fig. 4 f are refer to, in step S600, remove unnecessary top layer selection grid tangent line layer of oxide material 180 ', such as
It is foregoing, due to inevitably foring and unwanted layer of oxide material 180 ', therefore in this step, using chemistry
Mechanical milling tech (CMP), unnecessary top layer selection grid tangent line layer of oxide material 180 ' is removed, until exposing
Learn the surface of mechanical lapping cutoff layer 140 and simultaneously form smooth surface 190, it is hard due to cmp cutoff layer 140
Matter characteristic, the effect of cut-off positioning is served, is easy to the removing of undesired oxide material layer 180 ' and the shape of smooth surface 190
Into.
Fig. 4 g are refer to, in step S700, remove the cmp cutoff layer 140 to expose top layer interlayer
Dielectric layer 110, cmp cutoff layer 140 is used as because present invention employs silicon nitride hardmask layer (SiN HM), and
Phosphoric acid (H3PO4) solution has excellent Etch selectivity for silicon nitride, interlevel oxide dielectric layer is removed without excessive,
Therefore phosphoric acid (H is used3PO4) solution wet method removal cmp cutoff layer 140.
In step S800 (not shown), after the cmp cutoff layer 140 is removed, step is carried out
S810, depositing trench connector oxide (CH Plug Oxide), specifically, being cut in top layer interlayer dielectric layer and top layer selection grid
The surface deposition connector oxide of line oxide material；Step S820 is then carried out, silicon nitride is formed in connector oxide surface
Hard mask layer.
The HDP-CVD fill oxides material 180 ' that the technique of the present invention is formed, because it has good hydrofluoric acid wet method
The corrosion resistance of etching and fluoro-gas, therefore be not in fill oxide in follow-up tungsten grid forming step
The etching raceway groove (referring to Fig. 5 a) at the place of material 180 ', so as to what will not also be deposited in follow-up tungsten common source forming step
Tungsten 200 fills (referring to Fig. 5 b), goes forward side by side without forming tungsten residual after the cmp of subsequent tungsten common source
(referring to Fig. 5 c).
To sum up, the filling of oxide material uses high-density plasma in top layer selection grid tangent line raceway groove of the invention
Vapour deposition (HDP-CVD) is learned, obtained fill oxide can effectively be resisted fluorine-containing in follow-up tungsten grid forming process
Harmful etching of gas removal, filled so as to avoid the formation of etching raceway groove by tungsten deposition, and then avoid unnecessary tungsten
Residual, so as to improve the performance of three-dimensional (3D) flash memories.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited to
This, any one skilled in the art the invention discloses technical scope in, the change that can readily occur in or replace
Change, should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
Shield scope is defined.
Claims (10)
1. a kind of oxide fill method of top layer selection grid tangent line, comprises the following steps：
Multilayer lamination structure is formed in substrate surface, specifically, first, there is provided substrate, the substrate surface are handed over formed with multilayer
The interlayer dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer that mistake stacks are formed between adjacent interlayer dielectric layer；Then,
The smooth surface of top layer interlayer dielectric layer is obtained using chemical mechanical milling tech；
One layer of cmp cutoff layer is deposited on the smooth surface；
Photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, being ground first in chemical machinery
Grind and form compound lithography layer on the surface of cutoff layer；Then needing to form selection grid tangent line (Top Select Gate Cut)
Position implement photoetching；
Performed etching to form top layer selection grid tangent line (Top Select Gate Cut), specifically, using conventional etching process
The raceway groove of top layer selection grid tangent line (Top Select Gate Cut) is formed in foregoing photoetching position, and removes the complex light
Layer is carved to expose the surface of the cmp cutoff layer；
Top layer selection grid tangent line (Top Select Gate Cut) raceway groove is filled, specifically, using high-density plasma
CVD method (High Density Plasma CVD, HDP-CVD) deposits filling top layer selection grid in the raceway groove
Tangent line oxide material；
Unnecessary top layer selection grid tangent line oxide material is removed, specifically, using chemical mechanical milling tech, top layer will be selected
Select what is formed when grid tangent line (Top Select Gate Cut) raceway groove is filled in cmp cut-off layer surface
Unnecessary top layer selection grid tangent line oxide material removes, to expose cmp cut-off layer surface and be formed smooth
Surface；
Remove the cmp cutoff layer.
2. according to the method for claim 1, it is characterised in that：
The inter-level dielectric layer material is oxide, and the sacrificial dielectric layer material is silicon nitride, so as to form ON stacked structures
(ON Stacks)。
3. according to the method for claim 1, it is characterised in that：
The cmp cutoff layer is silicon nitride hardmask layer (SiN HM).
4. according to the method for claim 3, it is characterised in that：
The removal cmp cutoff layer, using phosphoric acid (H3PO4) solution.
5. according to the method for claim 1, it is characterised in that：
The compound lithography layer includes amorphous carbon layer (A-C), SiON layers and the photoresist layer sequentially formed.
6. according to the method for claim 1, it is characterised in that：
It is described to etch a certain interlayer dielectric layer for resting on stacked structure.
7. according to the method for claim 6, it is characterised in that：
The etching rests on 2nd, 3rd or 4th interlayer dielectric layer of the stacked structure since top.
8. according to the method for claim 1, it is characterised in that：
Removal to unnecessary top layer selection grid tangent line (Top Select Gate Cut) raceway groove fill oxide, using
Chemical mechanical milling tech (CMP).
9. according to the method for claim 1, it is characterised in that：
Chemical mechanical milling tech (CMP) in the step of substrate surface forms multilayer lamination structure is relatively low for grinding rate
Cmp (Buffer CMP).
10. according to the method for claim 1, it is characterised in that：
After the cmp cutoff layer is removed, in addition to depositing trench connector oxide (CH Plug Oxide),
Specifically, deposit connector oxide, Yi Ji on the surface of top layer interlayer dielectric layer and top layer selection grid tangent line oxide material
Connector oxide surface forms silicon nitride hardmask layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711167889.2A CN107833892B (en) | 2017-11-21 | 2017-11-21 | A kind of oxide fill method of top layer selection grid tangent line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711167889.2A CN107833892B (en) | 2017-11-21 | 2017-11-21 | A kind of oxide fill method of top layer selection grid tangent line |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107833892A true CN107833892A (en) | 2018-03-23 |
| CN107833892B CN107833892B (en) | 2019-11-26 |
Family
ID=61653189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711167889.2A Active CN107833892B (en) | 2017-11-21 | 2017-11-21 | A kind of oxide fill method of top layer selection grid tangent line |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107833892B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109801922A (en) * | 2019-01-31 | 2019-05-24 | 长江存储科技有限责任公司 | A kind of method and three-dimensional storage forming three-dimensional storage |
| CN110379711A (en) * | 2019-06-04 | 2019-10-25 | 长江存储科技有限责任公司 | Planarization process method, the preparation method of three-dimensional storage and three-dimensional storage |
| CN111276486A (en) * | 2018-12-07 | 2020-06-12 | 长江存储科技有限责任公司 | Novel 3D NAND memory device and method of forming the same |
| WO2021035603A1 (en) * | 2019-08-29 | 2021-03-04 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory and fabrication method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150200203A1 (en) * | 2013-01-15 | 2015-07-16 | Kyung-tae Jang | Vertical Memory Devices and Methods of Manufacturing the Same |
| US20150340377A1 (en) * | 2013-03-14 | 2015-11-26 | Samsung Electronics Co., Ltd. | Vertical memory devices with vertical isolation structures and methods of fabricating the same |
| CN106684030A (en) * | 2015-11-06 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of shallow groove isolation structure |
-
2017
- 2017-11-21 CN CN201711167889.2A patent/CN107833892B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150200203A1 (en) * | 2013-01-15 | 2015-07-16 | Kyung-tae Jang | Vertical Memory Devices and Methods of Manufacturing the Same |
| US20150340377A1 (en) * | 2013-03-14 | 2015-11-26 | Samsung Electronics Co., Ltd. | Vertical memory devices with vertical isolation structures and methods of fabricating the same |
| CN106684030A (en) * | 2015-11-06 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of shallow groove isolation structure |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111276486A (en) * | 2018-12-07 | 2020-06-12 | 长江存储科技有限责任公司 | Novel 3D NAND memory device and method of forming the same |
| CN111276486B (en) * | 2018-12-07 | 2021-03-12 | 长江存储科技有限责任公司 | Novel 3D NAND memory device and method of forming the same |
| CN109801922A (en) * | 2019-01-31 | 2019-05-24 | 长江存储科技有限责任公司 | A kind of method and three-dimensional storage forming three-dimensional storage |
| CN109801922B (en) * | 2019-01-31 | 2020-10-20 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory and three-dimensional memory |
| CN110379711A (en) * | 2019-06-04 | 2019-10-25 | 长江存储科技有限责任公司 | Planarization process method, the preparation method of three-dimensional storage and three-dimensional storage |
| WO2021035603A1 (en) * | 2019-08-29 | 2021-03-04 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory and fabrication method thereof |
| US11271007B2 (en) | 2019-08-29 | 2022-03-08 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory and fabrication method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107833892B (en) | 2019-11-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107833892B (en) | A kind of oxide fill method of top layer selection grid tangent line | |
| US8241991B2 (en) | Method for forming interconnect structure having airgap | |
| TWI635578B (en) | Methods of fabricating an f-ram | |
| CN110364529A (en) | Semiconductor devices and its manufacturing method including ultralow K spacer | |
| CN109244075A (en) | The manufacturing method of 3D memory device | |
| CN104051347A (en) | Damascene conductor for a 3D device | |
| CN108831886A (en) | Three-dimensional storage | |
| CN107564916B (en) | A kind of flattening method of 3D nand memory part | |
| CN110289265A (en) | The forming method of 3D nand memory | |
| CN110289263A (en) | 3D nand memory and forming method thereof | |
| CN110197830A (en) | 3D nand memory and forming method thereof | |
| CN107731844A (en) | The engraving method of 3D memories | |
| CN208767278U (en) | Semiconductor devices | |
| CN107731741B (en) | A kind of process improving contact hole plug oxide recess | |
| CN108155192A (en) | Semiconductor devices and forming method thereof | |
| CN109244076A (en) | 3D memory device | |
| CN107731834A (en) | A kind of core space layer insulation oxide layer CMP method for 3D NAND | |
| CN107658308A (en) | A kind of lithographic etch process method of top layer selection grid tangent line | |
| CN102709229A (en) | Method for forming W plug | |
| CN103066014A (en) | Copper/ air gap preparation method | |
| CN112259543A (en) | Three-dimensional memory device and manufacturing method thereof | |
| CN108364953B (en) | The device guard method of three-dimensional storage part and its manufacturing process | |
| CN108470736B (en) | The forming method of three-dimensional flash memory and the amorphous silicon lid in three-dimensional flash memory channel hole | |
| WO2023024869A1 (en) | Semiconductor surface planarization method, manufactured semiconductor and use | |
| KR100950470B1 (en) | Method for forming storage electrode of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |