CN107658308A - A kind of lithographic etch process method of top layer selection grid tangent line - Google Patents
A kind of lithographic etch process method of top layer selection grid tangent line Download PDFInfo
- Publication number
- CN107658308A CN107658308A CN201710733223.2A CN201710733223A CN107658308A CN 107658308 A CN107658308 A CN 107658308A CN 201710733223 A CN201710733223 A CN 201710733223A CN 107658308 A CN107658308 A CN 107658308A
- Authority
- CN
- China
- Prior art keywords
- layer
- tangent line
- selection grid
- photoetching
- top layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a kind of lithographic etch process method of top layer selection grid tangent line, the processing step deposited by increasing low temperature oxide (LTO) material after photoetching, in a disguised form reduce photoetching critical size (PHCD), it is achieved thereby that reduce the critical size of top layer selection grid tangent line, to adapt to the needs of semiconductor device miniaturization.Employing low temperature oxide (LTO) is used as deposition materials simultaneously, so that the temperature control of the depositing temperature of the vapour deposition process (PECVD) of plasma enhanced chemical is at about 50 DEG C, well below 100 120 DEG C of the baking temperature (Bake Temperature) of Other substrate materials (Photo Resist), the phenomenon for occurring Other substrate materials softening in deposition materials can be avoided completely.In a manner of above-mentioned means are replaced and immerse lithography tool (Immersion Litho Tool), carry out economic and stable reduction photoetching critical size, and then reduce the critical size of top layer selection grid tangent line.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of preparation method of 3D NAND flash memory structures, is specially
A kind of photo etching process method for reducing top layer selection grid tangent line critical size.
Background technology
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges：Physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty and most ask being produced into for lower unit storage unit that planar flash memory runs into
This, a variety of three-dimensional (3D) flash memories structures are arisen at the historic moment, such as 3D NOR (3D or non-) flash memories and 3D NAND
(3D with non-) flash memory.
Wherein, storage element is used three dimensional pattern stacked in multi-layers by 3D NAND using its small size, Large Copacity as starting point
It is highly integrated be design concept, produce high unit area storage density, the memory of efficient storage unit performance,
The prevailing technology designed and produced as emerging memory.
Meanwhile it is by the way that memory cell is three-dimensionally disposed in into substrate to carry in current 3D NAND structures
High density of integration, wherein channel layer are stood vertically on substrate, and grid is divided into lower floor's selection gate, middle level control gate and top
Layer selection gate (Top Select Gate) three parts, by the way that signal is distributed in three groups of gate electrodes to reduce signal
Between crosstalk.Specifically, the device of the upper and lower is used as selection transistor --- larger vertical of gate height/thickness
MOSFET, gate dielectric layer are conventional individual layer high-g value；The device in middle level is used as memory cell string, gate height/thickness compared with
Small, gate dielectric layer is tunnel layer, accumulation layer, the stacked structure on barrier layer.
Wherein, top layer selection grid tangent line (Top Select Gate Cut) generally is provided with the middle part of finger memory block, with
The top layer selection grid (Top Select Gate) for referring to memory block is divided into two parts, and top layer selection grid tangent line generally by
Oxide material is formed, and is prepared using atom layer deposition process (ALD).Typically use top layer selection grid tangent line (Top
Select Gate Cut) etching technics, by ON stack top layer layer 2-3 (2-3Tiers) etch away, as stop
(Block) raceway groove, specific preparation technology flow comprise the following steps (referring to Fig. 1 a-1d)：
S1：Multilayer lamination structure is formed, referring specifically to Fig. 1 a, first, there is provided substrate 10, the substrate surface is formed with more
The interlayer dielectric layer 20 and sacrificial dielectric layer 30, the sacrificial dielectric layer 30 that layer is staggeredly stacked are formed at adjacent interlayer dielectric layer
Between 20；Then, using chemical mechanical milling tech so that the surface planarisation of top layer interlayer dielectric layer 20；
S2：Hard mask deposition is carried out to form top layer selection grid tangent line (Top Select Gate Cut), referring specifically to figure
1b, forms composite hard mask layer 40 on the surface of planarized processing, and the composite hard mask layer 40 includes what is sequentially formed
Amorphous carbon layer (A-C) 41 is used as anti-reflecting layer as the SiON layers 42 that light-absorption layer, amorphous carbon layer (A-C) surface are formed；
S3：Photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut), it is first referring specifically to Fig. 1 c
First, photoresist layer 50 is formed in SiON layer surfaces；Then needing to form selection grid tangent line (Top Select Gate Cut)
Implement photoetching to remove the photoresist layer 50 in position 60；
S4：Perform etching to form top layer selection grid tangent line (Top Select Gate Cut), referring specifically to Fig. 1 d, adopt
With the etching technics of routine, the ditch of top layer selection grid tangent line (Top Select Gate Cut) is formed in foregoing photoetching position 60
Road 70, and photoresist layer and composite hard mask layer are removed to expose the surface of top layer interlayer dielectric layer；
S5：Top layer selection grid tangent line (Top Select Gate Cut) raceway groove is filled, specially using atomic layer
Depositing operation (ALD) fills top layer selection grid tangent line oxide material (not shown) in raceway groove 70.
And in the photoetching process of top layer selection grid tangent line raceway groove in S3, first coat photoresist layer 50 and light is carried out to it
Carve, hard mask layer 40 is performed etching followed by the photoetching agent pattern after photoetching, finally using etch come hard mask
Pattern etches raceway groove 70.Thus, a photoetching critical size (PH CD) can be defined after the photoetching of photoresist layer 50, and
A hard mask etching critical size (HM CD) can be defined after hard mask etching, the two critical sizes (that is, close by photoetching
Key size and hard mask etching critical size) substantially just define the final critical size (Critical of raceway groove
Dimension)。
Continued miniaturization with semiconductor industry and three-dimensional (3D) flash memories is in progress, for the precision of critical size
It is required that also more and more higher, particularly when etching the raceway groove of top layer selection grid tangent line (Top Select Gate Cut), it is desirable to push up
The etch critical dimension (TSG Cut Etch CD) of layer selection grid tangent line is than contact hole etching critical size (CH Etch CD) also
Small, it is (uncommon that this certainly will propose higher requirement for the photoetching critical size (TSG Cut PH CD) of top layer selection grid tangent line
Hope and reach 60-80nm dimensional accuracy), and at present in photoetching process frequently with exposure tool (Litho Tool) such as KrF it is accurate
Molecular laser (wavelength 248nm) and ArF PRKs (wavelength 193nm), its photoetching critical size that can reach (PH CD)
The limit be respectively 130-150nm and 120nm or so, do not reach the photoetching critical size for top layer selection grid tangent line much
(TSG Cut PH CD) requirement.
Although immersion instrument (Immersion Tool) can also be used in the prior art with 193 nanometers of immersion stepping
Even technology is realized is as short as 80 nanometers of following photoetching critical sizes (Ph CD) in single layer mask, but so does and can bring
Problems with：On the one hand, it can make it that whole Processes and apparatus is increasingly complex cumbersome using the instrument of immersion (Immersion Tool),
Undoubtedly add preparation cost；On the other hand, it is too small and crucial to also result in depth of focus (Depth of Focus, abbreviation DOF)
The uniformity (CD Uniformity) of size is unmanageable.
Therefore, how the critical size (TSG Cut CD) of economic and stable reduction top layer selection grid tangent line is with satisfaction
Three-dimensional (3D) flash memories demand miniaturization, the direction of research is endeavoured by those skilled in the art always.
The content of the invention
It is an object of the invention to provide a kind of photoetching process of top layer selection grid tangent line, economical and stable can subtract
The photoetching critical size (TSG Cut CD) of small top layer selection grid tangent line, so as to meet to improve the need of 3D nand flash memories miniaturization
Ask.
To achieve these goals, the present invention proposes a kind of photo etching process method of top layer selection grid tangent line, wraps
Include following steps：
Multilayer lamination structure is formed, specifically, first, there is provided substrate, multi-layer intercrossed stacking is formed in the substrate surface
Interlayer dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer be formed between adjacent interlayer dielectric layer；Then, using change
Learn the surface planarisation that mechanical milling tech (CMP) causes top layer interlayer dielectric layer；
Hard mask deposition is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, through flat
Composite hard mask layer is formed on the surface of smoothization processing；
Photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, first, compound
Hard mask layer surface forms photoresist layer；Then needing to form selection grid tangent line (Top Select Gate Cut) position
Implement photoetching to remove the photoresist layer of relevant position to form photoetching raceway groove；
Photoetching raceway groove deposition is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, in shape
Into photoetching raceway groove bottom wall and side wall formed one layer of sedimentary, to form depositing trench；
Performed etching to form top layer selection grid tangent line (Top Select Gate Cut), specifically, using conventional quarter
Etching technique, along the depositing trench, etching forms top layer selection grid tangent line (Top Select Gate Cut) raceway groove downwards, and goes
Except sedimentary, photoresist layer and composite hard mask layer to expose the surface of top layer interlayer dielectric layer.
Further, composite hard mask layer includes the amorphous carbon layer (A-C) and amorphous carbon layer (A-C) table sequentially formed
The SiON layers that face is formed.
Further, chemical mechanical milling tech (CMP) in the step of forming multilayer lamination structure for grinding rate compared with
Low cmp (Buffer CMP).
Further, to be formed in the step of top layer selection grid tangent line (Top Select Gate Cut) carries out photoetching, adopt
It is exposed with KrF PRKs or ArF PRKs.
Further, to be formed in the step of top layer selection grid tangent line (Top Select Gate Cut) carries out photoetching, shape
It is 130-150nm into photoetching raceway diameter.
Further, photoetching raceway groove deposition is carried out to form top layer selection grid tangent line (Top Select Gate Cut)
In step, deposition materials are used as using low temperature oxide material (Low Temperature Oxide, LTO).
Further, photoetching raceway groove deposition is carried out to form top layer selection grid tangent line (Top Select Gate Cut)
In step, using plasma strengthens chemical vapour deposition process (PECVD) to carry out low temperature oxide material (Low
Temperature Oxide, LTO) deposition.
Further, the depositing temperature of the vapour deposition process (PECVD) of using plasma enhancing chemistry is about 50 DEG C.
Further, photoetching raceway groove deposition is carried out to form top layer selection grid tangent line (Top Select Gate Cut)
In step, the sidewall deposition thickness of low temperature oxide material (Low Temperature Oxide, LTO) is so that depositing trench
A diameter of 60-80nm.
Further, the low temperature oxide material (Low Temperature Oxide, LTO) is SiO2。
Compared with prior art, the beneficial effects are mainly as follows：
First, top layer selection grid tangent line photo etching process of the invention, increase low temperature oxide (LTO) after photoetching
The processing step of material deposition, passes through what is deposited in the range of ＞ 95% in photoresist layer surface, particularly photoetching trench sidewalls
The thickness of low temperature oxide (LTO) material, photoetching critical size (PH CD) in a disguised form is reduced, it is achieved thereby that reducing top layer
The critical size of selection grid tangent line, to adapt to the needs of semiconductor device miniaturization；
Second, employ low temperature oxide (LTO) and be used as deposition materials so that the vapour deposition of plasma enhanced chemical
The temperature control of the depositing temperature of method (PECVD) is at about 50 DEG C, well below Other substrate materials (Photo Resist)
100-120 DEG C of baking temperature (Bake Temperature), can avoid Other substrate materials occur in deposition materials completely
The phenomenon of softening；
3rd, in a manner of above-mentioned means are replaced and immerse lithography tool (Immersion Litho Tool), to pass through
Ji and stable reduction photoetching critical size, and then reduce the critical size of top layer selection grid tangent line.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 a-1d are the photo etching process schematic flow sheet of top layer selection grid tangent line in the prior art；
Fig. 2 a-2e are the photo etching process schematic flow sheet of top layer selection grid tangent line in the present invention；
Fig. 3 is the SEM photograph of LTO sedimentaries in the photo etching process of top layer selection grid tangent line in the present invention.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in accompanying drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expended
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 2 a-2e are refer to, in the present embodiment, it is proposed that a kind of technique side for improving contact hole plug oxide depression
Method, comprise the following steps：
S100, multilayer lamination structure is formed, specifically, first, carrying out step S110, there is provided substrate 100, in the substrate
Surface forms the interlayer dielectric layer 110 and sacrificial dielectric layer 120 of multi-layer intercrossed stacking, and the sacrificial dielectric layer 120 is formed at phase
Between adjacent interlayer dielectric layer 110；Then, step S120 is carried out, top layer interlayer is caused using chemical mechanical milling tech (CMP)
The surface 130 of dielectric layer 110 planarizes；
S200, hard mask deposition is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically,
Composite hard mask 140 is formed on the surface of planarized processing；
S300, photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, first, entering
Row step S310, photoresist layer 150 is formed on the surface of composite hard mask layer 140；Then, step S320 is carried out, is needing to be formed
Implement photoetching to remove the photoresist layer of relevant position with shape in the position of selection grid tangent line (Top Select Gate Cut)
Into photoetching raceway groove 160；
S400, photoetching raceway groove deposition is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically
One layer of sedimentary 170 to be formed in the bottom wall and side wall of the photoetching raceway groove 160 of formation, to form depositing trench 180；
S500, performed etching to form top layer selection grid tangent line (Top Select Gate Cut), specifically, using normal
The etching technics of rule, along the depositing trench 180, etching forms top layer selection grid tangent line (Top Select Gate Cut) downwards
Raceway groove 190, and sedimentary 170, photoresist layer 150 and composite hard mask layer 140 are removed to expose top layer interlayer dielectric layer 110
Surface.
Specifically, refer to Fig. 2 a, in the step s 100, multilayer lamination structure is formed on the surface of substrate 100, specifically
Comprise the following steps, carry out step S110 first, there is provided substrate 100, multi-layer intercrossed stacking is formed on the surface of substrate 100
Interlayer dielectric layer 110 and sacrificial dielectric layer 120, the sacrificial dielectric layer 120 be formed at adjacent interlayer dielectric layer 110 it
Between, wherein, the substrate 100 is silicon substrate, and the interlayer dielectric layer 110 is oxide, for example, tetraethyl orthosilicate (TEOS),
The sacrificial dielectric layer 120 is nitride, for example, silicon nitride (SiN)；Step S120 is then carried out, using cmp
Technique (CMP) obtains the surface 130 of the planarization of top layer interlayer dielectric layer 110, based on tetraethyl orthosilicate (TEOS) characteristic, step
Chemical mechanical milling tech (CMP) in rapid S120 is using the relatively low cmp (Buffer of grinding rate
CMP)。
Fig. 2 b are refer to, in step s 200, are carried out to form top layer selection grid tangent line (Top Select Gate Cut)
Hard mask deposits, specifically, forming composite hard mask 140 on the surface 130 of planarized processing, specifically includes following step
Suddenly, step S211 is carried out, amorphous carbon layer (A-C) 141 is formed on the surface 130 of planarization and is used as light-absorption layer；Carry out step
S212, form SiON layers 142 on the surface of amorphous carbon layer (A-C) and be used as anti-reflecting layer.
Fig. 2 c are refer to, in step S300, are carried out to form top layer selection grid tangent line (Top Select Gate Cut)
Photoetching (Photoetching), specifically, first, carrying out step S310, photoresist layer is formed on the surface of composite hard mask layer 140
150；Then, step S320 is carried out, is needing to form the implementation photoetching of the position of selection grid tangent line (Top Select Gate Cut)
To remove the photoresist layer of relevant position to form photoetching raceway groove 160.Wherein, using using KrF PRKs or ArF
PRK is exposed, and then a diameter of 130-150nm of the photoetching raceway groove 160 formed.
Fig. 2 d are refer to, in step S400, are carried out to form top layer selection grid tangent line (Top Select Gate Cut)
Photoetching raceway groove deposits, and one layer of sedimentary 170 is formed in the bottom wall and side wall of the photoetching raceway groove 160 of formation, to form depositing trench
180.Specially use low temperature oxide material (Low Temperature Oxide, LTO) SiO2, pass through plasma enhancing
The vapour deposition process (PECVD) of chemistry forms sedimentary 170, as a result of low temperature oxide material (LTO), can control
The temperature of the vapour deposition process (PECVD) of plasma enhanced chemical is 50 DEG C or so, so as to avoid in deposition process
Hot mastication baking temperature is 100-120 DEG C of photoresist layer 150.Meanwhile the thickness of sedimentary 170 is according to photoetching raceway groove 160
Size (diameter 120-150nm) and the critical size (CD) of final top layer selection grid tangent line determine, to reach photoetching raceway groove
160 diameter subtracts the thickness of twice of photoetching trench sidewalls sedimentary 170, and it is wanting for 60-80nm to reach etch critical dimension
Ask and be defined.
Fig. 2 e are refer to, in step S500, are carried out to form top layer selection grid tangent line (Top Select Gate Cut)
Etching, specifically, using conventional etching technics, along the depositing trench 180, etching forms top layer selection grid tangent line downwards
(Top Select Gate Cut) raceway groove 190, and sedimentary 170, photoresist layer 150 and composite hard mask layer 140 are removed to reveal
Go out the surface of top layer interlayer dielectric layer 110.
To sum up, the photo etching process method of top layer selection grid tangent line of the invention, by increasing cryogenic oxygen after photoetching
The processing step of compound (LTO) material deposition, in a disguised form reduces photoetching critical size (PH CD), it is achieved thereby that reducing top
The critical size of layer selection grid tangent line, to adapt to the needs of semiconductor device miniaturization.Employ low temperature oxide simultaneously
(LTO) deposition materials are used as so that the temperature-controllable of the depositing temperature of the vapour deposition process (PECVD) of plasma enhanced chemical
System is at about 50 DEG C, well below 100-120 DEG C of baking temperature (Bake of Other substrate materials (Photo Resist)
Temperature), the phenomenon for occurring Other substrate materials softening in deposition materials can be avoided completely.Replaced with above-mentioned means
Using the mode for immersing lithography tool (Immersion Litho Tool), carry out economic and stable reduction photoetching critical size,
And then reduce the critical size of top layer selection grid tangent line, to meet the development need of 3D NAND flash memory structures miniaturization.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (10)
1. a kind of photo etching process method of top layer selection grid tangent line, comprises the following steps：
Multilayer lamination structure is formed, specifically, first, there is provided substrate, the layer of multi-layer intercrossed stacking is formed in the substrate surface
Between dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer is formed between adjacent interlayer dielectric layer；Then, using chemical machine
Tool grinding technics (CMP) causes the surface planarisation of top layer interlayer dielectric layer；
Hard mask deposition is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, planarized
Composite hard mask layer is formed on the surface of processing；
Photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, first, being covered firmly compound
Mold layer surface forms photoresist layer；Then needing to form the implementation of the position of selection grid tangent line (Top Select Gate Cut)
Photoetching is to remove the photoresist layer of relevant position to form photoetching raceway groove；
Photoetching raceway groove deposition is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, in formation
The bottom wall and side wall of photoetching raceway groove form one layer of sedimentary, to form depositing trench；
Performed etching to form top layer selection grid tangent line (Top Select Gate Cut), specifically, using conventional etching work
Skill, along the depositing trench, etching forms top layer selection grid tangent line (Top Select Gate Cut) raceway groove downwards, and removes and sink
Lamination, photoresist layer and composite hard mask layer are to expose the surface of top layer interlayer dielectric layer.
2. process according to claim 1, it is characterised in that：
The composite hard mask layer is formed including the amorphous carbon layer (A-C) sequentially formed and amorphous carbon layer (A-C) surface
SiON layers.
3. process according to claim 1, it is characterised in that：
Chemical mechanical milling tech (CMP) in the step of forming multilayer lamination structure grinds for the relatively low chemical machinery of grinding rate
Grind (Buffer CMP).
4. process according to claim 1, it is characterised in that：
To be formed in the step of top layer selection grid tangent line (Top Select Gate Cut) carries out photoetching, swashed using KrF quasi-molecules
Light or ArF PRKs are exposed.
5. process according to claim 1, it is characterised in that：
To be formed in the step of top layer selection grid tangent line (Top Select Gate Cut) carries out photoetching, it is straight to form photoetching raceway groove
Footpath is 130-150nm.
6. process according to claim 1, it is characterised in that：
To be formed in the step of top layer selection grid tangent line (Top Select Gate Cut) carries out photoetching raceway groove deposition, use is low
Warm oxide material (Low Temperature Oxide, LTO) is used as deposition materials.
7. process according to claim 6, it is characterised in that：
Using plasma strengthens chemical vapour deposition process (PECVD) to carry out low temperature oxide material (Low
Temperature Oxide, LTO) deposition.
8. process according to claim 7, it is characterised in that：
The depositing temperature of the vapour deposition process (PECVD) of using plasma enhancing chemistry is about 50 DEG C.
9. process according to claim 6, it is characterised in that：
The sidewall deposition thickness of low temperature oxide material (Low Temperature Oxide, LTO) for cause depositing trench it is straight
Footpath is 60-80nm.
10. process according to claim 6, it is characterised in that：
The low temperature oxide material (Low Temperature Oxide, LTO) is SiO2。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710733223.2A CN107658308A (en) | 2017-08-24 | 2017-08-24 | A kind of lithographic etch process method of top layer selection grid tangent line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710733223.2A CN107658308A (en) | 2017-08-24 | 2017-08-24 | A kind of lithographic etch process method of top layer selection grid tangent line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107658308A true CN107658308A (en) | 2018-02-02 |
Family
ID=61128857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710733223.2A Pending CN107658308A (en) | 2017-08-24 | 2017-08-24 | A kind of lithographic etch process method of top layer selection grid tangent line |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107658308A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110176265A (en) * | 2019-04-29 | 2019-08-27 | 长江存储科技有限责任公司 | Multilayer Memory and preparation method thereof |
| US10854621B2 (en) * | 2019-02-26 | 2020-12-01 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device and method for forming the same |
| US10923401B2 (en) | 2018-10-26 | 2021-02-16 | International Business Machines Corporation | Gate cut critical dimension shrink and active gate defect healing using selective deposition |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194826A (en) * | 2010-03-03 | 2011-09-21 | 三星电子株式会社 | Three-dimensional semiconductor storing device and formation method thereof |
| US20120108068A1 (en) * | 2010-11-03 | 2012-05-03 | Texas Instruments Incorporated | Method for Patterning Sublithographic Features |
| CN104157654A (en) * | 2014-08-15 | 2014-11-19 | 中国科学院微电子研究所 | Three-dimensional memory and manufacturing method thereof |
| CN104201097A (en) * | 2014-09-02 | 2014-12-10 | 上海华力微电子有限公司 | Manufacturing method of small-size graph |
| US20150200203A1 (en) * | 2013-01-15 | 2015-07-16 | Kyung-tae Jang | Vertical Memory Devices and Methods of Manufacturing the Same |
-
2017
- 2017-08-24 CN CN201710733223.2A patent/CN107658308A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194826A (en) * | 2010-03-03 | 2011-09-21 | 三星电子株式会社 | Three-dimensional semiconductor storing device and formation method thereof |
| US20120108068A1 (en) * | 2010-11-03 | 2012-05-03 | Texas Instruments Incorporated | Method for Patterning Sublithographic Features |
| US20150200203A1 (en) * | 2013-01-15 | 2015-07-16 | Kyung-tae Jang | Vertical Memory Devices and Methods of Manufacturing the Same |
| CN104157654A (en) * | 2014-08-15 | 2014-11-19 | 中国科学院微电子研究所 | Three-dimensional memory and manufacturing method thereof |
| CN104201097A (en) * | 2014-09-02 | 2014-12-10 | 上海华力微电子有限公司 | Manufacturing method of small-size graph |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10923401B2 (en) | 2018-10-26 | 2021-02-16 | International Business Machines Corporation | Gate cut critical dimension shrink and active gate defect healing using selective deposition |
| US10854621B2 (en) * | 2019-02-26 | 2020-12-01 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device and method for forming the same |
| US11177270B2 (en) | 2019-02-26 | 2021-11-16 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device and method for forming the same |
| CN110176265A (en) * | 2019-04-29 | 2019-08-27 | 长江存储科技有限责任公司 | Multilayer Memory and preparation method thereof |
| CN110176265B (en) * | 2019-04-29 | 2021-06-04 | 长江存储科技有限责任公司 | Multi-layer memory and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10840097B2 (en) | Semiconductor methods and devices | |
| KR101860249B1 (en) | Method for multiplying pattern density by crossing multiple patterned layers | |
| KR101860251B1 (en) | Method for patterning a substrate for planarization | |
| US11107682B2 (en) | Method for patterning a substrate using a layer with multiple materials | |
| KR101311621B1 (en) | Method for forming uneven pattern | |
| KR102603019B1 (en) | Method for forming an etch mask for sub-resolution substrate patterning | |
| CN104733291B (en) | Method for integrated circuit patterns | |
| TWI409852B (en) | Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning | |
| TWI633583B (en) | Method and system for forming memory fin patterns | |
| TW201539744A (en) | A method for producing fin structures of a semiconductor device in a substrate | |
| CN107658308A (en) | A kind of lithographic etch process method of top layer selection grid tangent line | |
| CN109545790A (en) | The forming method in the channel hole of three-dimensional storage | |
| CN107833892B (en) | A kind of oxide fill method of top layer selection grid tangent line | |
| CN107731844A (en) | The engraving method of 3D memories | |
| CN102881648A (en) | Method for manufacturing metal interconnection structure | |
| TW201232645A (en) | Method for forming stair-step structures | |
| KR20220039755A (en) | Methods for increasing pattern density on a wafer | |
| KR20190073585A (en) | Substrate patterning method | |
| CN107731832A (en) | A kind of etching process of top layer selection grid tangent line | |
| TWI545618B (en) | Method for patterning a substrate for planarization | |
| JP7005325B2 (en) | How to Manufacture Templates, Equipment for Imprint Lithography and Semiconductor Devices | |
| CN107731831A (en) | A kind of process for improving contact hole plug oxide depression | |
| TWI836121B (en) | Method for increasing pattern density on a wafer | |
| CN108364858B (en) | Semiconductor devices and preparation method thereof | |
| CN111668091A (en) | Semiconductor device and method of forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180202 |
|
| RJ01 | Rejection of invention patent application after publication |